X-Git-Url: https://git.codelabs.ch/?p=libxhcidbg.git;a=blobdiff_plain;f=src%2Fhw-dbc.adb;h=6cd96208d43e03bf512c2b17e84433cee5934dc7;hp=b711b711c3068c2fcc9f2eadcdb22544bc5d5fda;hb=cd5533df1e049202bf7fef3ced40bd73fb498e90;hpb=9d4d4b92f6a736132805db7ae7338351c0ea151a diff --git a/src/hw-dbc.adb b/src/hw-dbc.adb index b711b71..6cd9620 100644 --- a/src/hw-dbc.adb +++ b/src/hw-dbc.adb @@ -28,7 +28,7 @@ with HW.DbC.TRBs; package body HW.DbC with - Refined_State => (State => (Reset_Intermission_End, Connected, Running, + Refined_State => (State => (Connected, Running, DbC_Run_Deadline, DbC_Poll_Deadline, DbC_Stat_Deadline, Events.State, Transfer_Info.State, Transfer_Rings.State), @@ -36,18 +36,14 @@ with Transfer_Rings.DMA)) is - Perform_Hardware_Reset : constant Boolean := True; Apply_Intel_Quirk : constant Boolean := True; - Debug_xCap : constant Boolean := False; + Debug_xCap : constant Boolean := False; - Reset_Intermission_MS : constant := 736; -- seems reliable above 722ms - Reset_Intermission_End : Time.T; - - Connected, - Running : Boolean; - DbC_Run_Deadline : Time.T; - DbC_Poll_Deadline : Time.T; - DbC_Stat_Deadline : Time.T; + Connected : Boolean := False; + Running : Boolean := False; + DbC_Run_Deadline : Time.T := Time.T_First; + DbC_Poll_Deadline : Time.T := Time.T_First; + DbC_Stat_Deadline : Time.T := Time.T_First; ---------------------------------------------------------------------------- @@ -69,10 +65,15 @@ is wData : Desc_Str; end record with Pack; + Null_String_Desc : constant String_Descriptor + := (bLength => 0, + bDescriptor_Type => 0, + wData => (others => 0)); + type Desc_Strings_Type is (String0, Manufacturer, Product, Serial_Number); type Desc_Strings_Array is array (Desc_Strings_Type) of String_Descriptor with Pack; - Desc_Strings : Desc_Strings_Array + Desc_Strings : Desc_Strings_Array := (others => Null_String_Desc) with Address => System'To_Address (DMA_Buffers.Descriptor_Strings_Base); @@ -155,11 +156,13 @@ is Success := not Timeout; end; exit when not Success; + pragma Warnings (GNATprove, Off, "statement has no effect"); for I in 0 .. 1234 loop null; -- Busy loop to reduce pressure on HC BIOS Owned -- Semaphore. It shouldn't generate an SMI but -- might congest the xHC? end loop; + pragma Warnings (GNATprove, On, "statement has no effect"); end loop; pragma Debug (not Success, Debug.Put_Line @@ -170,46 +173,6 @@ is end if; end BIOS_Handover; - procedure Reset_xHC (Success : out Boolean) - is - use type Word8; - HCH, - HCR : Word8; - Deadline : Time.T; - begin - Op_Regs.Write (Run_Stop, Word8'(0)); - Deadline := Time.MS_From_Now (1_000); - Success := True; - loop - Op_Regs.Read (HCH, HC_Halted); - exit when HCH = 1; - Success := not Time.Timed_Out (Deadline); - exit when not Success; - end loop; - pragma Debug (not Success, Debug.Put_Line - ("ERROR: xHC didn't halt within 1s.")); - - if Success then - Op_Regs.Write (Host_Controller_Reset, Word8'(1)); - Deadline := Time.MS_From_Now (1_000); - - -- Some Intel xHCI implementations are known to freak out rarely - -- (anything can happen up to global reset assertion) if the - -- Host Controller Reset bit is polled before the controller is - -- ready. - Time.M_Delay (1); -- Delay here or hell freezes over - - loop - Op_Regs.Read (HCR, Host_Controller_Reset); - exit when HCR = 0; - Success := not Time.Timed_Out (Deadline); - exit when not Success; - end loop; - pragma Debug (not Success, Debug.Put_Line - ("ERROR: xHC didn't finish reset within 1s.")); - end if; - end Reset_xHC; - procedure Reset (Initial_Reset : Boolean := False); procedure Init @@ -233,7 +196,11 @@ is loop Op_Regs.Read (CNR, Controller_Not_Ready); exit when CNR = 0; - Success := not Time.Timed_Out (Deadline); + declare + Timed_Out : constant Boolean := Time.Timed_Out (Deadline); + begin + Success := not Timed_Out; + end; exit when not Success; end loop; pragma Debug (not Success, Debug.Put_Line @@ -244,18 +211,14 @@ is BIOS_Handover (Success); end if; - if Perform_Hardware_Reset and then Success then - Reset_xHC (Success); - Reset_Intermission_End := Time.MS_From_Now (Reset_Intermission_MS); - else - Reset_Intermission_End := Time.Now; - end if; - if Success then xCap_Regs.Byte_Offset := 0; Find_Next_xCap (10, Success); end if; + pragma Debug (not Success, Debug.Put_Line + ("ERROR: Couldn't find xHCI debug capability.")); + if Success then Regs.Byte_Offset := xCap_Regs.Byte_Offset; @@ -272,10 +235,6 @@ is String_To_Desc (Desc_Strings (Serial_Number), "1"); Reset (Initial_Reset => True); - else - null; - pragma Debug (Debug.Put_Line - ("ERROR: Couldn't find xHCI debug capability.")); end if; end Init; @@ -356,7 +315,6 @@ is Regs.Write (Product_ID, Word16 (16#dbc1#)); Regs.Write (Device_Revision, Word16 (16#0001#)); - Time.Delay_Until (Reset_Intermission_End); Regs.Write (DbC_Enable, Word8'(1)); loop Regs.Read (DCE, DbC_Enable); @@ -377,13 +335,13 @@ is procedure Poll (Now : Boolean := False) is use type Word8; - use type Word64; + Temp8 : Word8; Timed_Out : Boolean; begin if Regs.Byte_Offset /= 0 then - Timed_Out := Now or else Time.Timed_Out (DbC_Poll_Deadline); - if Timed_Out then + Timed_Out := Time.Timed_Out (DbC_Poll_Deadline); + if Now or else Timed_Out then Regs.Read (Temp8, DbC_Enable); if Temp8 = 1 then Regs.Read (Temp8, Current_Connect_Status); @@ -426,8 +384,6 @@ is end if; end if; else - Reset_Intermission_End := - Time.MS_From_Now (Reset_Intermission_MS); pragma Debug (Debug.Put_Line ("DbC got disabled, huh?")); Reset; end if;