From b871b6cf4ba4da0c62e198bb25c0bbc8af739ee4 Mon Sep 17 00:00:00 2001 From: Adrian-Ken Rueegsegger Date: Wed, 10 May 2017 13:59:47 +0200 Subject: [PATCH] Do not perform hardware reset The debug capability interface is independent from the "regular" xHCI interface, so a hardware reset is not necessary. This simplifies the initialization and triggering potential issues if the reset timeout is too small for a given hardware platform. Signed-off-by: Adrian-Ken Rueegsegger --- src/hw-dbc.adb | 56 +------------------------------------------------- 1 file changed, 1 insertion(+), 55 deletions(-) diff --git a/src/hw-dbc.adb b/src/hw-dbc.adb index 5c5709a..40026ff 100644 --- a/src/hw-dbc.adb +++ b/src/hw-dbc.adb @@ -28,7 +28,7 @@ with HW.DbC.TRBs; package body HW.DbC with - Refined_State => (State => (Reset_Intermission_End, Connected, Running, + Refined_State => (State => (Connected, Running, DbC_Run_Deadline, DbC_Poll_Deadline, DbC_Stat_Deadline, Events.State, Transfer_Info.State, Transfer_Rings.State), @@ -36,13 +36,9 @@ with Transfer_Rings.DMA)) is - Perform_Hardware_Reset : constant Boolean := True; Apply_Intel_Quirk : constant Boolean := True; Debug_xCap : constant Boolean := False; - Reset_Intermission_MS : constant := 736; -- seems reliable above 722ms - Reset_Intermission_End : Time.T; - Connected, Running : Boolean; DbC_Run_Deadline : Time.T; @@ -170,46 +166,6 @@ is end if; end BIOS_Handover; - procedure Reset_xHC (Success : out Boolean) - is - use type Word8; - HCH, - HCR : Word8; - Deadline : Time.T; - begin - Op_Regs.Write (Run_Stop, Word8'(0)); - Deadline := Time.MS_From_Now (1_000); - Success := True; - loop - Op_Regs.Read (HCH, HC_Halted); - exit when HCH = 1; - Success := not Time.Timed_Out (Deadline); - exit when not Success; - end loop; - pragma Debug (not Success, Debug.Put_Line - ("ERROR: xHC didn't halt within 1s.")); - - if Success then - Op_Regs.Write (Host_Controller_Reset, Word8'(1)); - Deadline := Time.MS_From_Now (1_000); - - -- Some Intel xHCI implementations are known to freak out rarely - -- (anything can happen up to global reset assertion) if the - -- Host Controller Reset bit is polled before the controller is - -- ready. - Time.M_Delay (1); -- Delay here or hell freezes over - - loop - Op_Regs.Read (HCR, Host_Controller_Reset); - exit when HCR = 0; - Success := not Time.Timed_Out (Deadline); - exit when not Success; - end loop; - pragma Debug (not Success, Debug.Put_Line - ("ERROR: xHC didn't finish reset within 1s.")); - end if; - end Reset_xHC; - procedure Reset (Initial_Reset : Boolean := False); procedure Init @@ -244,13 +200,6 @@ is BIOS_Handover (Success); end if; - if Perform_Hardware_Reset and then Success then - Reset_xHC (Success); - Reset_Intermission_End := Time.MS_From_Now (Reset_Intermission_MS); - else - Reset_Intermission_End := Time.Now; - end if; - if Success then xCap_Regs.Byte_Offset := 0; Find_Next_xCap (10, Success); @@ -355,7 +304,6 @@ is Regs.Write (Product_ID, Word16 (16#dbc1#)); Regs.Write (Device_Revision, Word16 (16#0001#)); - Time.Delay_Until (Reset_Intermission_End); Regs.Write (DbC_Enable, Word8'(1)); loop Regs.Read (DCE, DbC_Enable); @@ -425,8 +373,6 @@ is end if; end if; else - Reset_Intermission_End := - Time.MS_From_Now (Reset_Intermission_MS); pragma Debug (Debug.Put_Line ("DbC got disabled, huh?")); Reset; end if; -- 2.30.2