Merge tag 'davinci-for-v4.18/dt' of git://git.kernel.org/pub/scm/linux/kernel/git...
[muen/linux.git] / Documentation / devicetree / bindings / memory-controllers / nvidia,tegra30-mc.txt
1 NVIDIA Tegra Memory Controller device tree bindings
2 ===================================================
3
4 memory-controller node
5 ----------------------
6
7 Required properties:
8 - compatible: Should be "nvidia,tegra<chip>-mc"
9 - reg: Physical base address and length of the controller's registers.
10 - clocks: Must contain an entry for each entry in clock-names.
11   See ../clocks/clock-bindings.txt for details.
12 - clock-names: Must include the following entries:
13   - mc: the module's clock input
14 - interrupts: The interrupt outputs from the controller.
15
16 Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
17 - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
18   the SWGROUP of the master.
19
20 This device implements an IOMMU that complies with the generic IOMMU binding.
21 See ../iommu/iommu.txt for details.
22
23 emc-timings subnode
24 -------------------
25
26 The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
27 register PMC_STRAPPING_OPT_A).
28
29 Required properties for "emc-timings" nodes :
30 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
31
32 timing subnode
33 --------------
34
35 Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
36
37 Required properties for timing nodes :
38 - clock-frequency : Should contain the memory clock rate in Hz.
39 - nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
40 (see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
41 specified, according to the board documentation:
42
43         MC_EMEM_ARB_CFG
44         MC_EMEM_ARB_OUTSTANDING_REQ
45         MC_EMEM_ARB_TIMING_RCD
46         MC_EMEM_ARB_TIMING_RP
47         MC_EMEM_ARB_TIMING_RC
48         MC_EMEM_ARB_TIMING_RAS
49         MC_EMEM_ARB_TIMING_FAW
50         MC_EMEM_ARB_TIMING_RRD
51         MC_EMEM_ARB_TIMING_RAP2PRE
52         MC_EMEM_ARB_TIMING_WAP2PRE
53         MC_EMEM_ARB_TIMING_R2R
54         MC_EMEM_ARB_TIMING_W2W
55         MC_EMEM_ARB_TIMING_R2W
56         MC_EMEM_ARB_TIMING_W2R
57         MC_EMEM_ARB_DA_TURNS
58         MC_EMEM_ARB_DA_COVERS
59         MC_EMEM_ARB_MISC0
60         MC_EMEM_ARB_MISC1
61         MC_EMEM_ARB_RING1_THROTTLE
62
63 Example SoC include file:
64
65 / {
66         mc: memory-controller@70019000 {
67                 compatible = "nvidia,tegra124-mc";
68                 reg = <0x0 0x70019000 0x0 0x1000>;
69                 clocks = <&tegra_car TEGRA124_CLK_MC>;
70                 clock-names = "mc";
71
72                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
73
74                 #iommu-cells = <1>;
75         };
76
77         sdhci@700b0000 {
78                 compatible = "nvidia,tegra124-sdhci";
79                 ...
80                 iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
81         };
82 };
83
84 Example board file:
85
86 / {
87         memory-controller@70019000 {
88                 emc-timings-3 {
89                         nvidia,ram-code = <3>;
90
91                         timing-12750000 {
92                                 clock-frequency = <12750000>;
93
94                                 nvidia,emem-configuration = <
95                                         0x40040001 /* MC_EMEM_ARB_CFG */
96                                         0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
97                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
98                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
99                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
100                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
101                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
102                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
103                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
104                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
105                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
106                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
107                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
108                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
109                                         0x06030203 /* MC_EMEM_ARB_DA_TURNS */
110                                         0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
111                                         0x77e30303 /* MC_EMEM_ARB_MISC0 */
112                                         0x70000f03 /* MC_EMEM_ARB_MISC1 */
113                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
114                                 >;
115                         };
116                 };
117         };
118 };