Merge tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[muen/linux.git] / Documentation / devicetree / bindings / pinctrl / allwinner,sunxi-pinctrl.txt
1 * Allwinner A1X Pin Controller
2
3 The pins controlled by sunXi pin controller are organized in banks,
4 each bank has 32 pins.  Each pin has 7 multiplexing functions, with
5 the first two functions being GPIO in and out. The configuration on
6 the pins includes drive strength and pull-up.
7
8 Required properties:
9 - compatible: Should be one of the following (depending on your SoC):
10   "allwinner,sun4i-a10-pinctrl"
11   "allwinner,sun5i-a10s-pinctrl"
12   "allwinner,sun5i-a13-pinctrl"
13   "allwinner,sun6i-a31-pinctrl"
14   "allwinner,sun6i-a31s-pinctrl"
15   "allwinner,sun6i-a31-r-pinctrl"
16   "allwinner,sun7i-a20-pinctrl"
17   "allwinner,sun8i-a23-pinctrl"
18   "allwinner,sun8i-a23-r-pinctrl"
19   "allwinner,sun8i-a33-pinctrl"
20   "allwinner,sun9i-a80-pinctrl"
21   "allwinner,sun9i-a80-r-pinctrl"
22   "allwinner,sun8i-a83t-pinctrl"
23   "allwinner,sun8i-a83t-r-pinctrl"
24   "allwinner,sun8i-h3-pinctrl"
25   "allwinner,sun8i-h3-r-pinctrl"
26   "allwinner,sun8i-r40-pinctrl"
27   "allwinner,sun50i-a64-pinctrl"
28   "allwinner,sun50i-a64-r-pinctrl"
29   "allwinner,sun50i-h5-pinctrl"
30   "allwinner,sun50i-h6-pinctrl"
31   "allwinner,sun50i-h6-r-pinctrl"
32   "nextthing,gr8-pinctrl"
33
34 - reg: Should contain the register physical address and length for the
35   pin controller.
36
37 - clocks: phandle to the clocks feeding the pin controller:
38   - "apb": the gated APB parent clock
39   - "hosc": the high frequency oscillator in the system
40   - "losc": the low frequency oscillator in the system
41
42 Note: For backward compatibility reasons, the hosc and losc clocks are only
43 required if you need to use the optional input-debounce property. Any new
44 device tree should set them.
45
46 Optional properties:
47   - input-debounce: Array of debouncing periods in microseconds. One period per
48     irq bank found in the controller. 0 if no setup required.
49
50
51 Please refer to pinctrl-bindings.txt in this directory for details of the
52 common pinctrl bindings used by client devices.
53
54 A pinctrl node should contain at least one subnodes representing the
55 pinctrl groups available on the machine. Each subnode will list the
56 pins it needs, and how they should be configured, with regard to muxer
57 configuration, drive strength and pullups. If one of these options is
58 not set, its actual value will be unspecified.
59
60 Allwinner A1X Pin Controller supports the generic pin multiplexing and
61 configuration bindings. For details on each properties, you can refer to
62  ./pinctrl-bindings.txt.
63
64 Required sub-node properties:
65   - pins
66   - function
67
68 Optional sub-node properties:
69   - bias-disable
70   - bias-pull-up
71   - bias-pull-down
72   - drive-strength
73
74 *** Deprecated pin configuration and multiplexing binding
75
76 Required subnode-properties:
77
78 - allwinner,pins: List of strings containing the pin name.
79 - allwinner,function: Function to mux the pins listed above to.
80
81 Optional subnode-properties:
82 - allwinner,drive: Integer. Represents the current sent to the pin
83     0: 10 mA
84     1: 20 mA
85     2: 30 mA
86     3: 40 mA
87 - allwinner,pull: Integer.
88     0: No resistor
89     1: Pull-up resistor
90     2: Pull-down resistor
91
92 Examples:
93
94 pio: pinctrl@1c20800 {
95         compatible = "allwinner,sun5i-a13-pinctrl";
96         reg = <0x01c20800 0x400>;
97         #address-cells = <1>;
98         #size-cells = <0>;
99
100         uart1_pins_a: uart1@0 {
101                 allwinner,pins = "PE10", "PE11";
102                 allwinner,function = "uart1";
103                 allwinner,drive = <0>;
104                 allwinner,pull = <0>;
105         };
106
107         uart1_pins_b: uart1@1 {
108                 allwinner,pins = "PG3", "PG4";
109                 allwinner,function = "uart1";
110                 allwinner,drive = <0>;
111                 allwinner,pull = <0>;
112         };
113 };
114
115
116 GPIO and interrupt controller
117 -----------------------------
118
119 This hardware also acts as a GPIO controller and an interrupt
120 controller.
121
122 Consumers that would want to refer to one or the other (or both)
123 should provide through the usual *-gpios and interrupts properties a
124 cell with 3 arguments, first the number of the bank, then the pin
125 inside that bank, and finally the flags for the GPIO/interrupts.
126
127 Example:
128
129 xio: gpio@38 {
130         compatible = "nxp,pcf8574a";
131         reg = <0x38>;
132
133         gpio-controller;
134         #gpio-cells = <2>;
135
136         interrupt-parent = <&pio>;
137         interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
138         interrupt-controller;
139         #interrupt-cells = <2>;
140 };
141
142 reg_usb1_vbus: usb1-vbus {
143         compatible = "regulator-fixed";
144         regulator-name = "usb1-vbus";
145         regulator-min-microvolt = <5000000>;
146         regulator-max-microvolt = <5000000>;
147         gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
148 };