ARM: dts: realview: Fix some more duplicate regulator nodes
[muen/linux.git] / arch / arm / boot / dts / arm-realview-pb11mp.dts
1 /*
2  * Copyright 2015 Linaro Ltd
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22
23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "skeleton.dtsi"
27
28 / {
29         model = "ARM RealView PB11MPcore";
30         compatible = "arm,realview-pb11mp";
31
32         chosen { };
33
34         aliases {
35                 serial0 = &pb11mp_serial0;
36                 serial1 = &pb11mp_serial1;
37                 serial2 = &pb11mp_serial2;
38                 serial3 = &pb11mp_serial3;
39         };
40
41         memory {
42                 /*
43                  * The PB11MPCore has 512 MiB memory @ 0x70000000
44                  * and the first 256 are also remapped @ 0x00000000
45                  */
46                 reg = <0x70000000 0x20000000>;
47         };
48
49         cpus {
50                 #address-cells = <1>;
51                 #size-cells = <0>;
52                 enable-method = "arm,realview-smp";
53
54                 MP11_0: cpu@0 {
55                         device_type = "cpu";
56                         compatible = "arm,arm11mpcore";
57                         reg = <0>;
58                         next-level-cache = <&L2>;
59                 };
60
61                 MP11_1: cpu@1 {
62                         device_type = "cpu";
63                         compatible = "arm,arm11mpcore";
64                         reg = <1>;
65                         next-level-cache = <&L2>;
66                 };
67
68                 MP11_2: cpu@2 {
69                         device_type = "cpu";
70                         compatible = "arm,arm11mpcore";
71                         reg = <2>;
72                         next-level-cache = <&L2>;
73                 };
74
75                 MP11_3: cpu@3 {
76                         device_type = "cpu";
77                         compatible = "arm,arm11mpcore";
78                         reg = <3>;
79                         next-level-cache = <&L2>;
80                 };
81         };
82
83         /* Primary TestChip GIC synthesized with the CPU */
84         intc_tc11mp: interrupt-controller@1f000100 {
85                 compatible = "arm,tc11mp-gic";
86                 #interrupt-cells = <3>;
87                 #address-cells = <1>;
88                 interrupt-controller;
89                 reg = <0x1f001000 0x1000>,
90                       <0x1f000100 0x100>;
91         };
92
93         L2: l2-cache {
94                 compatible = "arm,l220-cache";
95                 reg = <0x1f002000 0x1000>;
96                 interrupt-parent = <&intc_tc11mp>;
97                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
98                              <0 30 IRQ_TYPE_LEVEL_HIGH>,
99                              <0 31 IRQ_TYPE_LEVEL_HIGH>;
100                 cache-unified;
101                 cache-level = <2>;
102                 /*
103                  * Override default cache size, sets and
104                  * associativity as these may be erroneously set
105                  * up by boot loader(s), probably for safety
106                  * since th outer sync operation can cause the
107                  * cache to hang unless disabled.
108                  */
109                 cache-size = <1048576>; // 1MB
110                 cache-sets = <4096>;
111                 cache-line-size = <32>;
112                 arm,shared-override;
113                 arm,parity-enable;
114                 arm,outer-sync-disable;
115         };
116
117         scu@1f000000 {
118                 compatible = "arm,arm11mp-scu";
119                 reg = <0x1f000000 0x100>;
120         };
121
122         timer@1f000600 {
123                 compatible = "arm,arm11mp-twd-timer";
124                 reg = <0x1f000600 0x20>;
125                 interrupt-parent = <&intc_tc11mp>;
126                 interrupts = <1 13 0xf04>;
127         };
128
129         watchdog@1f000620 {
130                 compatible = "arm,arm11mp-twd-wdt";
131                 reg = <0x1f000620 0x20>;
132                 interrupt-parent = <&intc_tc11mp>;
133                 interrupts = <1 14 0xf04>;
134         };
135
136         /* PMU with one IRQ line per core */
137         pmu {
138                 compatible = "arm,arm11mpcore-pmu";
139                 interrupt-parent = <&intc_tc11mp>;
140                 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
141                              <0 18 IRQ_TYPE_LEVEL_HIGH>,
142                              <0 19 IRQ_TYPE_LEVEL_HIGH>,
143                              <0 20 IRQ_TYPE_LEVEL_HIGH>;
144                 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
145         };
146
147         /* The voltage to the MMC card is hardwired at 3.3V */
148         vmmc: regulator-vmmc {
149                 compatible = "regulator-fixed";
150                 regulator-name = "vmmc";
151                 regulator-min-microvolt = <3300000>;
152                 regulator-max-microvolt = <3300000>;
153                 regulator-boot-on;
154         };
155
156         veth: regulator-veth {
157                 compatible = "regulator-fixed";
158                 regulator-name = "veth";
159                 regulator-min-microvolt = <3300000>;
160                 regulator-max-microvolt = <3300000>;
161                 regulator-boot-on;
162         };
163
164         xtal24mhz: xtal24mhz@24M {
165                 #clock-cells = <0>;
166                 compatible = "fixed-clock";
167                 clock-frequency = <24000000>;
168         };
169
170         refclk32khz: refclk32khz {
171                 compatible = "fixed-clock";
172                 #clock-cells = <0>;
173                 clock-frequency = <32768>;
174         };
175
176         timclk: timclk@1M {
177                 #clock-cells = <0>;
178                 compatible = "fixed-factor-clock";
179                 clock-div = <24>;
180                 clock-mult = <1>;
181                 clocks = <&xtal24mhz>;
182         };
183
184         mclk: mclk@24M {
185                 #clock-cells = <0>;
186                 compatible = "fixed-factor-clock";
187                 clock-div = <1>;
188                 clock-mult = <1>;
189                 clocks = <&xtal24mhz>;
190         };
191
192         kmiclk: kmiclk@24M {
193                 #clock-cells = <0>;
194                 compatible = "fixed-factor-clock";
195                 clock-div = <1>;
196                 clock-mult = <1>;
197                 clocks = <&xtal24mhz>;
198         };
199
200         sspclk: sspclk@24M {
201                 #clock-cells = <0>;
202                 compatible = "fixed-factor-clock";
203                 clock-div = <1>;
204                 clock-mult = <1>;
205                 clocks = <&xtal24mhz>;
206         };
207
208         uartclk: uartclk@24M {
209                 #clock-cells = <0>;
210                 compatible = "fixed-factor-clock";
211                 clock-div = <1>;
212                 clock-mult = <1>;
213                 clocks = <&xtal24mhz>;
214         };
215
216         wdogclk: wdogclk@24M {
217                 #clock-cells = <0>;
218                 compatible = "fixed-factor-clock";
219                 clock-div = <1>;
220                 clock-mult = <1>;
221                 clocks = <&xtal24mhz>;
222         };
223
224         /* FIXME: this actually hangs off the PLL clocks */
225         pclk: pclk@0 {
226                 #clock-cells = <0>;
227                 compatible = "fixed-clock";
228                 clock-frequency = <0>;
229         };
230
231         flash0@40000000 {
232                 /* 2 * 32MiB NOR Flash memory */
233                 compatible = "arm,versatile-flash", "cfi-flash";
234                 reg = <0x40000000 0x04000000>;
235                 bank-width = <4>;
236         };
237
238         flash1@44000000 {
239                 // 2 * 32MiB NOR Flash memory
240                 compatible = "arm,versatile-flash", "cfi-flash";
241                 reg = <0x44000000 0x04000000>;
242                 bank-width = <4>;
243         };
244
245         bridge {
246                 compatible = "ti,ths8134a", "ti,ths8134";
247                 #address-cells = <1>;
248                 #size-cells = <0>;
249
250                 ports {
251                         #address-cells = <1>;
252                         #size-cells = <0>;
253
254                         port@0 {
255                                 reg = <0>;
256
257                                 vga_bridge_in: endpoint {
258                                         remote-endpoint = <&clcd_pads>;
259                                 };
260                         };
261
262                         port@1 {
263                                 reg = <1>;
264
265                                 vga_bridge_out: endpoint {
266                                         remote-endpoint = <&vga_con_in>;
267                                 };
268                         };
269                 };
270         };
271
272         vga {
273                 /*
274                  * This DDC I2C is connected directly to the DVI portions
275                  * of the connector, so it's not really working when the
276                  * monitor is connected to the VGA connector.
277                  */
278                 compatible = "vga-connector";
279                 ddc-i2c-bus = <&i2c1>;
280
281                 port {
282                         vga_con_in: endpoint {
283                                 remote-endpoint = <&vga_bridge_out>;
284                         };
285                 };
286         };
287
288         soc {
289                 #address-cells = <1>;
290                 #size-cells = <1>;
291                 compatible = "arm,realview-pb11mp-soc", "simple-bus";
292                 regmap = <&pb11mp_syscon>;
293                 ranges;
294
295                 pb11mp_syscon: syscon@10000000 {
296                         compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
297                         reg = <0x10000000 0x1000>;
298
299                         led@08.0 {
300                                 compatible = "register-bit-led";
301                                 offset = <0x08>;
302                                 mask = <0x01>;
303                                 label = "versatile:0";
304                                 linux,default-trigger = "heartbeat";
305                                 default-state = "on";
306                         };
307                         led@08.1 {
308                                 compatible = "register-bit-led";
309                                 offset = <0x08>;
310                                 mask = <0x02>;
311                                 label = "versatile:1";
312                                 linux,default-trigger = "mmc0";
313                                 default-state = "off";
314                         };
315                         led@08.2 {
316                                 compatible = "register-bit-led";
317                                 offset = <0x08>;
318                                 mask = <0x04>;
319                                 label = "versatile:2";
320                                 linux,default-trigger = "cpu0";
321                                 default-state = "off";
322                         };
323                         led@08.3 {
324                                 compatible = "register-bit-led";
325                                 offset = <0x08>;
326                                 mask = <0x08>;
327                                 label = "versatile:3";
328                                 linux,default-trigger = "cpu1";
329                                 default-state = "off";
330                         };
331                         led@08.4 {
332                                 compatible = "register-bit-led";
333                                 offset = <0x08>;
334                                 mask = <0x10>;
335                                 label = "versatile:4";
336                                 linux,default-trigger = "cpu2";
337                                 default-state = "off";
338                         };
339                         led@08.5 {
340                                 compatible = "register-bit-led";
341                                 offset = <0x08>;
342                                 mask = <0x20>;
343                                 label = "versatile:5";
344                                 linux,default-trigger = "cpu3";
345                                 default-state = "off";
346                         };
347                         led@08.6 {
348                                 compatible = "register-bit-led";
349                                 offset = <0x08>;
350                                 mask = <0x40>;
351                                 label = "versatile:6";
352                                 default-state = "off";
353                         };
354                         led@08.7 {
355                                 compatible = "register-bit-led";
356                                 offset = <0x08>;
357                                 mask = <0x80>;
358                                 label = "versatile:7";
359                                 default-state = "off";
360                         };
361
362                         oscclk0: osc0@0c {
363                                 compatible = "arm,syscon-icst307";
364                                 #clock-cells = <0>;
365                                 lock-offset = <0x20>;
366                                 vco-offset = <0x0C>;
367                                 clocks = <&xtal24mhz>;
368                         };
369                         oscclk1: osc1@10 {
370                                 compatible = "arm,syscon-icst307";
371                                 #clock-cells = <0>;
372                                 lock-offset = <0x20>;
373                                 vco-offset = <0x10>;
374                                 clocks = <&xtal24mhz>;
375                         };
376                         oscclk2: osc2@14 {
377                                 compatible = "arm,syscon-icst307";
378                                 #clock-cells = <0>;
379                                 lock-offset = <0x20>;
380                                 vco-offset = <0x14>;
381                                 clocks = <&xtal24mhz>;
382                         };
383                         oscclk3: osc3@18 {
384                                 compatible = "arm,syscon-icst307";
385                                 #clock-cells = <0>;
386                                 lock-offset = <0x20>;
387                                 vco-offset = <0x18>;
388                                 clocks = <&xtal24mhz>;
389                         };
390                         oscclk4: osc4@1c {
391                                 compatible = "arm,syscon-icst307";
392                                 #clock-cells = <0>;
393                                 lock-offset = <0x20>;
394                                 vco-offset = <0x1c>;
395                                 clocks = <&xtal24mhz>;
396                         };
397                         oscclk5: osc5@d4 {
398                                 compatible = "arm,syscon-icst307";
399                                 #clock-cells = <0>;
400                                 lock-offset = <0x20>;
401                                 vco-offset = <0xd4>;
402                                 clocks = <&xtal24mhz>;
403                         };
404                         oscclk6: osc6@d8 {
405                                 compatible = "arm,syscon-icst307";
406                                 #clock-cells = <0>;
407                                 lock-offset = <0x20>;
408                                 vco-offset = <0xd8>;
409                                 clocks = <&xtal24mhz>;
410                         };
411                 };
412
413                 sp810_syscon: sysctl@10001000 {
414                         compatible = "arm,sp810", "arm,primecell";
415                         reg = <0x10001000 0x1000>;
416                         clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
417                         clock-names = "refclk", "timclk", "apb_pclk";
418                         #clock-cells = <1>;
419                         clock-output-names = "timerclk0",
420                                              "timerclk1",
421                                              "timerclk2",
422                                              "timerclk3";
423                         assigned-clocks = <&sp810_syscon 0>,
424                                           <&sp810_syscon 1>,
425                                           <&sp810_syscon 2>,
426                                           <&sp810_syscon 3>;
427                         assigned-clock-parents = <&timclk>,
428                                                <&timclk>,
429                                                <&timclk>,
430                                                <&timclk>;
431                 };
432
433                 i2c0: i2c@10002000 {
434                         #address-cells = <1>;
435                         #size-cells = <0>;
436                         compatible = "arm,versatile-i2c";
437                         reg = <0x10002000 0x1000>;
438
439                         rtc@68 {
440                                 compatible = "dallas,ds1338";
441                                 reg = <0x68>;
442                         };
443                 };
444
445                 aaci: aaci@10004000 {
446                         compatible = "arm,pl041", "arm,primecell";
447                         reg = <0x10004000 0x1000>;
448                         interrupt-parent = <&intc_tc11mp>;
449                         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
450                         clocks = <&pclk>;
451                         clock-names = "apb_pclk";
452                 };
453
454                 mci: mmcsd@10005000 {
455                         compatible = "arm,pl18x", "arm,primecell";
456                         reg = <0x10005000 0x1000>;
457                         interrupt-parent = <&intc_tc11mp>;
458                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
459                                         <0 15 IRQ_TYPE_LEVEL_HIGH>;
460                         /* Due to frequent FIFO overruns, use just 500 kHz */
461                         max-frequency = <500000>;
462                         bus-width = <4>;
463                         cap-sd-highspeed;
464                         cap-mmc-highspeed;
465                         clocks = <&mclk>, <&pclk>;
466                         clock-names = "mclk", "apb_pclk";
467                         vmmc-supply = <&vmmc>;
468                         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
469                         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
470                 };
471
472                 kmi0: kmi@10006000 {
473                         compatible = "arm,pl050", "arm,primecell";
474                         reg = <0x10006000 0x1000>;
475                         interrupt-parent = <&intc_tc11mp>;
476                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
477                         clocks = <&kmiclk>, <&pclk>;
478                         clock-names = "KMIREFCLK", "apb_pclk";
479                 };
480
481                 kmi1: kmi@10007000 {
482                         compatible = "arm,pl050", "arm,primecell";
483                         reg = <0x10007000 0x1000>;
484                         interrupt-parent = <&intc_tc11mp>;
485                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
486                         clocks = <&kmiclk>, <&pclk>;
487                         clock-names = "KMIREFCLK", "apb_pclk";
488                 };
489
490                 pb11mp_serial0: serial@10009000 {
491                         compatible = "arm,pl011", "arm,primecell";
492                         reg = <0x10009000 0x1000>;
493                         interrupt-parent = <&intc_tc11mp>;
494                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
495                         clocks = <&uartclk>, <&pclk>;
496                         clock-names = "uartclk", "apb_pclk";
497                 };
498
499                 pb11mp_serial1: serial@1000a000 {
500                         compatible = "arm,pl011", "arm,primecell";
501                         reg = <0x1000a000 0x1000>;
502                         interrupt-parent = <&intc_tc11mp>;
503                         interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
504                         clocks = <&uartclk>, <&pclk>;
505                         clock-names = "uartclk", "apb_pclk";
506                 };
507
508                 pb11mp_serial2: serial@1000b000 {
509                         compatible = "arm,pl011", "arm,primecell";
510                         reg = <0x1000b000 0x1000>;
511                         interrupt-parent = <&intc_pb11mp>;
512                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
513                         clocks = <&uartclk>, <&pclk>;
514                         clock-names = "uartclk", "apb_pclk";
515                 };
516
517                 pb11mp_serial3: serial@1000c000 {
518                         compatible = "arm,pl011", "arm,primecell";
519                         reg = <0x1000c000 0x1000>;
520                         interrupt-parent = <&intc_pb11mp>;
521                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
522                         clocks = <&uartclk>, <&pclk>;
523                         clock-names = "uartclk", "apb_pclk";
524                 };
525
526                 spi@1000d000 {
527                         compatible = "arm,pl022", "arm,primecell";
528                         reg = <0x1000d000 0x1000>;
529                         interrupt-parent = <&intc_pb11mp>;
530                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
531                         clocks = <&sspclk>, <&pclk>;
532                         clock-names = "SSPCLK", "apb_pclk";
533                 };
534
535                 watchdog@1000f000 {
536                         compatible = "arm,sp805", "arm,primecell";
537                         reg = <0x1000f000 0x1000>;
538                         interrupt-parent = <&intc_pb11mp>;
539                         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
540                         clocks = <&wdogclk>, <&pclk>;
541                         clock-names = "wdogclk", "apb_pclk";
542                         status = "disabled";
543                 };
544
545                 watchdog@10010000 {
546                         compatible = "arm,sp805", "arm,primecell";
547                         reg = <0x10010000 0x1000>;
548                         interrupt-parent = <&intc_pb11mp>;
549                         interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
550                         clocks = <&wdogclk>, <&pclk>;
551                         clock-names = "wdogclk", "apb_pclk";
552                 };
553
554                 timer01: timer@10011000 {
555                         compatible = "arm,sp804", "arm,primecell";
556                         reg = <0x10011000 0x1000>;
557                         interrupt-parent = <&intc_tc11mp>;
558                         interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
559                         arm,sp804-has-irq = <1>;
560                         clocks = <&sp810_syscon 0>,
561                                  <&sp810_syscon 1>,
562                                  <&pclk>;
563                         clock-names = "timerclk0",
564                                     "timerclk1",
565                                     "apb_pclk";
566                 };
567
568                 timer23: timer@10012000 {
569                         compatible = "arm,sp804", "arm,primecell";
570                         reg = <0x10012000 0x1000>;
571                         interrupt-parent = <&intc_tc11mp>;
572                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
573                         arm,sp804-has-irq = <1>;
574                         clocks = <&sp810_syscon 2>,
575                                  <&sp810_syscon 3>,
576                                  <&pclk>;
577                         clock-names = "timerclk2",
578                                     "timerclk3",
579                                     "apb_pclk";
580                 };
581
582                 gpio0: gpio@10013000 {
583                         compatible = "arm,pl061", "arm,primecell";
584                         reg = <0x10013000 0x1000>;
585                         gpio-controller;
586                         interrupt-parent = <&intc_pb11mp>;
587                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
588                         #gpio-cells = <2>;
589                         interrupt-controller;
590                         #interrupt-cells = <2>;
591                         clocks = <&pclk>;
592                         clock-names = "apb_pclk";
593                 };
594
595                 gpio1: gpio@10014000 {
596                         compatible = "arm,pl061", "arm,primecell";
597                         reg = <0x10014000 0x1000>;
598                         gpio-controller;
599                         interrupt-parent = <&intc_pb11mp>;
600                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
601                         #gpio-cells = <2>;
602                         interrupt-controller;
603                         #interrupt-cells = <2>;
604                         clocks = <&pclk>;
605                         clock-names = "apb_pclk";
606                 };
607
608                 gpio2: gpio@10015000 {
609                         compatible = "arm,pl061", "arm,primecell";
610                         reg = <0x10015000 0x1000>;
611                         gpio-controller;
612                         interrupt-parent = <&intc_pb11mp>;
613                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
614                         #gpio-cells = <2>;
615                         interrupt-controller;
616                         #interrupt-cells = <2>;
617                         clocks = <&pclk>;
618                         clock-names = "apb_pclk";
619                 };
620
621                 i2c1: i2c@10016000 {
622                         #address-cells = <1>;
623                         #size-cells = <0>;
624                         compatible = "arm,versatile-i2c";
625                         reg = <0x10016000 0x1000>;
626                 };
627
628                 rtc: rtc@10017000 {
629                         compatible = "arm,pl031", "arm,primecell";
630                         reg = <0x10017000 0x1000>;
631                         interrupt-parent = <&intc_tc11mp>;
632                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
633                         clocks = <&pclk>;
634                         clock-names = "apb_pclk";
635                 };
636
637                 timer45: timer@10018000 {
638                         compatible = "arm,sp804", "arm,primecell";
639                         reg = <0x10018000 0x1000>;
640                         clocks = <&timclk>, <&pclk>;
641                         clock-names = "timer", "apb_pclk";
642                         status = "disabled";
643                 };
644
645                 timer67: timer@10019000 {
646                         compatible = "arm,sp804", "arm,primecell";
647                         reg = <0x10019000 0x1000>;
648                         clocks = <&timclk>, <&pclk>;
649                         clock-names = "timer", "apb_pclk";
650                         status = "disabled";
651                 };
652
653
654                 clcd@10020000 {
655                         compatible = "arm,pl111", "arm,primecell";
656                         reg = <0x10020000 0x1000>;
657                         interrupt-parent = <&intc_pb11mp>;
658                         interrupt-names = "combined";
659                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
660                         clocks = <&oscclk4>, <&pclk>;
661                         clock-names = "clcdclk", "apb_pclk";
662                         /* 1024x768 16bpp @65MHz works fine */
663                         max-memory-bandwidth = <95000000>;
664
665                         port {
666                                 clcd_pads: endpoint {
667                                         remote-endpoint = <&vga_bridge_in>;
668                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
669                                 };
670                         };
671                 };
672
673                 /*
674                  * This GIC on the Platform Baseboard is cascaded off the
675                  * TestChip GIC
676                  */
677                 intc_pb11mp: interrupt-controller@1e000000 {
678                         compatible = "arm,arm11mp-gic";
679                         #interrupt-cells = <3>;
680                         #address-cells = <1>;
681                         interrupt-controller;
682                         reg = <0x1e001000 0x1000>,
683                               <0x1e000000 0x100>;
684                         interrupt-parent = <&intc_tc11mp>;
685                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
686                 };
687
688                 /* SMSC 9118 ethernet with PHY and EEPROM */
689                 ethernet@4e000000 {
690                         compatible = "smsc,lan9118", "smsc,lan9115";
691                         reg = <0x4e000000 0x10000>;
692                         interrupt-parent = <&intc_tc11mp>;
693                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
694                         phy-mode = "mii";
695                         reg-io-width = <4>;
696                         smsc,irq-active-high;
697                         smsc,irq-push-pull;
698                         vdd33a-supply = <&veth>;
699                         vddvario-supply = <&veth>;
700                 };
701
702                 usb@4f000000 {
703                         compatible = "nxp,usb-isp1761";
704                         reg = <0x4f000000 0x20000>;
705                         interrupt-parent = <&intc_tc11mp>;
706                         interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
707                         port1-otg;
708                 };
709         };
710 };