ARM: dts: imx1: Fix memory node duplication
[muen/linux.git] / arch / arm / boot / dts / imx27-phytec-phycard-s-som.dtsi
1 /*
2  * Copyright 2012 Sascha Hauer, Uwe Kleine-K├Ânig, Steffen Trumtrar
3  * and Markus Pargmann, Pengutronix
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
12
13 /dts-v1/;
14 #include "imx27.dtsi"
15
16 / {
17         model = "Phytec pca100";
18         compatible = "phytec,imx27-pca100", "fsl,imx27";
19
20         memory@a0000000 {
21                 reg = <0xa0000000 0x08000000>; /* 128MB */
22         };
23 };
24
25 &cspi1 {
26         cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
27                    <&gpio4 27 GPIO_ACTIVE_HIGH>;
28         status = "okay";
29 };
30
31 &fec {
32         pinctrl-names = "default";
33         pinctrl-0 = <&pinctrl_fec1>;
34         status = "okay";
35 };
36
37 &i2c2 {
38         pinctrl-names = "default";
39         pinctrl-0 = <&pinctrl_i2c2>;
40         status = "okay";
41
42         at24@52 {
43                 compatible = "atmel,24c32";
44                 pagesize = <32>;
45                 reg = <0x52>;
46         };
47 };
48
49 &iomuxc {
50         imx27-phycard-s-som {
51                 pinctrl_fec1: fec1grp {
52                         fsl,pins = <
53                                 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
54                                 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
55                                 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
56                                 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
57                                 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
58                                 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
59                                 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
60                                 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
61                                 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
62                                 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
63                                 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
64                                 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
65                                 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
66                                 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
67                                 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
68                                 MX27_PAD_ATA_DATA13__FEC_COL 0x0
69                                 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
70                                 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
71                         >;
72                 };
73
74                 pinctrl_i2c2: i2c2grp {
75                         fsl,pins = <
76                                 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
77                                 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
78                         >;
79                 };
80
81                 pinctrl_nfc: nfcgrp {
82                         fsl,pins = <
83                                 MX27_PAD_NFRB__NFRB 0x0
84                                 MX27_PAD_NFCLE__NFCLE 0x0
85                                 MX27_PAD_NFWP_B__NFWP_B 0x0
86                                 MX27_PAD_NFCE_B__NFCE_B 0x0
87                                 MX27_PAD_NFALE__NFALE 0x0
88                                 MX27_PAD_NFRE_B__NFRE_B 0x0
89                                 MX27_PAD_NFWE_B__NFWE_B 0x0
90                         >;
91                 };
92         };
93 };
94
95 &nfc {
96         pinctrl-names = "default";
97         pinctrl-0 = <&pinctrl_nfc>;
98         nand-bus-width = <8>;
99         nand-ecc-mode = "hw";
100         nand-on-flash-bbt;
101         status = "okay";
102 };