ARM: dts: imx27: Fix memory node duplication
[muen/linux.git] / arch / arm / boot / dts / imx27-phytec-phycore-som.dtsi
1 /*
2  * Copyright 2012 Sascha Hauer, Pengutronix
3  *
4  * The code contained herein is licensed under the GNU General Public
5  * License. You may obtain a copy of the GNU General Public License
6  * Version 2 or later at the following locations:
7  *
8  * http://www.opensource.org/licenses/gpl-license.html
9  * http://www.gnu.org/copyleft/gpl.html
10  */
11
12 /dts-v1/;
13 #include "imx27.dtsi"
14
15 / {
16         model = "Phytec pcm038";
17         compatible = "phytec,imx27-pcm038", "fsl,imx27";
18
19         memory@a0000000 {
20                 device_type = "memory";
21                 reg = <0xa0000000 0x08000000>;
22         };
23
24         regulators {
25                 compatible = "simple-bus";
26                 #address-cells = <1>;
27                 #size-cells = <0>;
28
29                 reg_3v3: regulator@0 {
30                         compatible = "regulator-fixed";
31                         reg = <0>;
32                         regulator-name = "3V3";
33                         regulator-min-microvolt = <3300000>;
34                         regulator-max-microvolt = <3300000>;
35                 };
36
37                 reg_5v0: regulator@1 {
38                         compatible = "regulator-fixed";
39                         reg = <1>;
40                         regulator-name = "5V0";
41                         regulator-min-microvolt = <5000000>;
42                         regulator-max-microvolt = <5000000>;
43                 };
44         };
45
46         usbphy {
47                 compatible = "simple-bus";
48                 #address-cells = <1>;
49                 #size-cells = <0>;
50
51                 usbphy0: usbphy@0 {
52                         compatible = "usb-nop-xceiv";
53                         reg = <0>;
54                         vcc-supply = <&sw3_reg>;
55                         clocks = <&clks IMX27_CLK_DUMMY>;
56                         clock-names = "main_clk";
57                         #phy-cells = <0>;
58                 };
59         };
60 };
61
62 &audmux {
63         status = "okay";
64
65         /* SSI0 <=> PINS_4 (MC13783 Audio) */
66         ssi0 {
67                 fsl,audmux-port = <0>;
68                 fsl,port-config = <0xcb205000>;
69         };
70
71         pins4 {
72                 fsl,audmux-port = <2>;
73                 fsl,port-config = <0x00001000>;
74         };
75 };
76
77 &cspi1 {
78         pinctrl-names = "default";
79         pinctrl-0 = <&pinctrl_cspi1>;
80         cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
81         status = "okay";
82
83         pmic: mc13783@0 {
84                 compatible = "fsl,mc13783";
85                 pinctrl-names = "default";
86                 pinctrl-0 = <&pinctrl_pmic>;
87                 reg = <0>;
88                 spi-cs-high;
89                 spi-max-frequency = <20000000>;
90                 interrupt-parent = <&gpio2>;
91                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
92                 fsl,mc13xxx-uses-adc;
93                 fsl,mc13xxx-uses-rtc;
94
95                 pmicleds: leds {
96                         #address-cells = <1>;
97                         #size-cells = <0>;
98                         led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
99                 };
100
101                 regulators {
102                         /* SW1A and SW1B joined operation */
103                         sw1_reg: sw1a {
104                                 regulator-min-microvolt = <1200000>;
105                                 regulator-max-microvolt = <1520000>;
106                                 regulator-always-on;
107                                 regulator-boot-on;
108                         };
109
110                         /* SW2A and SW2B joined operation */
111                         sw2_reg: sw2a {
112                                 regulator-min-microvolt = <1800000>;
113                                 regulator-max-microvolt = <1800000>;
114                                 regulator-always-on;
115                                 regulator-boot-on;
116                         };
117
118                         sw3_reg: sw3 {
119                                 regulator-min-microvolt = <5000000>;
120                                 regulator-max-microvolt = <5000000>;
121                                 regulator-always-on;
122                                 regulator-boot-on;
123                         };
124
125                         vaudio_reg: vaudio {
126                                 regulator-always-on;
127                                 regulator-boot-on;
128                         };
129
130                         violo_reg: violo {
131                                 regulator-min-microvolt = <1800000>;
132                                 regulator-max-microvolt = <1800000>;
133                                 regulator-always-on;
134                                 regulator-boot-on;
135                         };
136
137                         viohi_reg: viohi {
138                                 regulator-always-on;
139                                 regulator-boot-on;
140                         };
141
142                         vgen_reg: vgen {
143                                 regulator-min-microvolt = <1500000>;
144                                 regulator-max-microvolt = <1500000>;
145                                 regulator-always-on;
146                                 regulator-boot-on;
147                         };
148
149                         vcam_reg: vcam {
150                                 regulator-min-microvolt = <2800000>;
151                                 regulator-max-microvolt = <2800000>;
152                         };
153
154                         vrf1_reg: vrf1 {
155                                 regulator-min-microvolt = <2775000>;
156                                 regulator-max-microvolt = <2775000>;
157                                 regulator-always-on;
158                                 regulator-boot-on;
159                         };
160
161                         vrf2_reg: vrf2 {
162                                 regulator-min-microvolt = <2775000>;
163                                 regulator-max-microvolt = <2775000>;
164                                 regulator-always-on;
165                                 regulator-boot-on;
166                         };
167
168                         vmmc1_reg: vmmc1 {
169                                 regulator-min-microvolt = <1600000>;
170                                 regulator-max-microvolt = <3000000>;
171                         };
172
173                         gpo1_reg: gpo1 { };
174
175                         pwgt1spi_reg: pwgt1spi {
176                                 regulator-always-on;
177                         };
178                 };
179         };
180 };
181
182 &fec {
183         phy-mode = "mii";
184         phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
185         phy-supply = <&reg_3v3>;
186         pinctrl-names = "default";
187         pinctrl-0 = <&pinctrl_fec1>;
188         status = "okay";
189 };
190
191 &i2c2 {
192         clock-frequency = <400000>;
193         pinctrl-names = "default";
194         pinctrl-0 = <&pinctrl_i2c2>;
195         status = "okay";
196
197         at24@52 {
198                 compatible = "atmel,24c32";
199                 pagesize = <32>;
200                 reg = <0x52>;
201         };
202
203         pcf8563@51 {
204                 compatible = "nxp,pcf8563";
205                 reg = <0x51>;
206         };
207
208         lm75@4a {
209                 compatible = "national,lm75";
210                 reg = <0x4a>;
211         };
212 };
213
214 &iomuxc {
215         imx27_phycore_som {
216                 pinctrl_cspi1: cspi1grp {
217                         fsl,pins = <
218                                 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
219                                 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
220                                 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
221                                 MX27_PAD_CSPI1_SS0__GPIO4_28    0x0 /* SPI1 CS0 */
222                         >;
223                 };
224
225                 pinctrl_fec1: fec1grp {
226                         fsl,pins = <
227                                 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
228                                 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
229                                 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
230                                 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
231                                 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
232                                 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
233                                 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
234                                 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
235                                 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
236                                 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
237                                 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
238                                 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
239                                 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
240                                 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
241                                 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
242                                 MX27_PAD_ATA_DATA13__FEC_COL 0x0
243                                 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
244                                 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
245                                 MX27_PAD_SSI3_TXDAT__GPIO3_30   0x0 /* FEC RST */
246                         >;
247                 };
248
249                 pinctrl_i2c2: i2c2grp {
250                         fsl,pins = <
251                                 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
252                                 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
253                         >;
254                 };
255
256                 pinctrl_nfc: nfcgrp {
257                         fsl,pins = <
258                                 MX27_PAD_NFRB__NFRB 0x0
259                                 MX27_PAD_NFCLE__NFCLE 0x0
260                                 MX27_PAD_NFWP_B__NFWP_B 0x0
261                                 MX27_PAD_NFCE_B__NFCE_B 0x0
262                                 MX27_PAD_NFALE__NFALE 0x0
263                                 MX27_PAD_NFRE_B__NFRE_B 0x0
264                                 MX27_PAD_NFWE_B__NFWE_B 0x0
265                         >;
266                 };
267
268                 pinctrl_pmic: pmicgrp {
269                         fsl,pins = <
270                                 MX27_PAD_USB_PWR__GPIO2_23      0x0 /* PMIC IRQ */
271                         >;
272                 };
273
274                 pinctrl_ssi1: ssi1grp {
275                         fsl,pins = <
276                                 MX27_PAD_SSI1_FS__SSI1_FS 0x0
277                                 MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
278                                 MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
279                                 MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
280                         >;
281                 };
282
283                 pinctrl_usbotg: usbotggrp {
284                         fsl,pins = <
285                                 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
286                                 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
287                                 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
288                                 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
289                                 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
290                                 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
291                                 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
292                                 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
293                                 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
294                                 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
295                                 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
296                                 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
297                         >;
298                 };
299         };
300 };
301
302 &nfc {
303         pinctrl-names = "default";
304         pinctrl-0 = <&pinctrl_nfc>;
305         nand-bus-width = <8>;
306         nand-ecc-mode = "hw";
307         nand-on-flash-bbt;
308         status = "okay";
309 };
310
311 &ssi1 {
312         pinctrl-names = "default";
313         pinctrl-0 = <&pinctrl_ssi1>;
314         status = "okay";
315 };
316
317 &usbotg {
318         pinctrl-names = "default";
319         pinctrl-0 = <&pinctrl_usbotg>;
320         dr_mode = "otg";
321         phy_type = "ulpi";
322         fsl,usbphy = <&usbphy0>;
323         vbus-supply = <&sw3_reg>;
324         disable-over-current;
325         status = "okay";
326 };
327
328 &weim {
329         status = "okay";
330
331         nor: nor@0,0 {
332                 compatible = "cfi-flash";
333                 reg = <0 0x00000000 0x02000000>;
334                 bank-width = <2>;
335                 linux,mtd-name = "physmap-flash.0";
336                 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
337                 #address-cells = <1>;
338                 #size-cells = <1>;
339         };
340
341         sram: sram@1,0 {
342                 compatible = "mtd-ram";
343                 reg = <1 0x00000000 0x00800000>;
344                 bank-width = <2>;
345                 linux,mtd-name = "mtd-ram.0";
346                 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
347                 #address-cells = <1>;
348                 #size-cells = <1>;
349         };
350 };