ARM: dts: imx6ul: Add flexcan stop mode wakeup support
[muen/linux.git] / arch / arm / boot / dts / imx6ul.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
10
11 / {
12         #address-cells = <1>;
13         #size-cells = <1>;
14         /*
15          * The decompressor and also some bootloaders rely on a
16          * pre-existing /chosen node to be available to insert the
17          * command line and merge other ATAGS info.
18          */
19         chosen {};
20
21         aliases {
22                 ethernet0 = &fec1;
23                 ethernet1 = &fec2;
24                 gpio0 = &gpio1;
25                 gpio1 = &gpio2;
26                 gpio2 = &gpio3;
27                 gpio3 = &gpio4;
28                 gpio4 = &gpio5;
29                 i2c0 = &i2c1;
30                 i2c1 = &i2c2;
31                 i2c2 = &i2c3;
32                 i2c3 = &i2c4;
33                 mmc0 = &usdhc1;
34                 mmc1 = &usdhc2;
35                 serial0 = &uart1;
36                 serial1 = &uart2;
37                 serial2 = &uart3;
38                 serial3 = &uart4;
39                 serial4 = &uart5;
40                 serial5 = &uart6;
41                 serial6 = &uart7;
42                 serial7 = &uart8;
43                 sai1 = &sai1;
44                 sai2 = &sai2;
45                 sai3 = &sai3;
46                 spi0 = &ecspi1;
47                 spi1 = &ecspi2;
48                 spi2 = &ecspi3;
49                 spi3 = &ecspi4;
50                 usbphy0 = &usbphy1;
51                 usbphy1 = &usbphy2;
52         };
53
54         cpus {
55                 #address-cells = <1>;
56                 #size-cells = <0>;
57
58                 cpu0: cpu@0 {
59                         compatible = "arm,cortex-a7";
60                         device_type = "cpu";
61                         reg = <0>;
62                         clock-latency = <61036>; /* two CLK32 periods */
63                         #cooling-cells = <2>;
64                         operating-points = <
65                                 /* kHz  uV */
66                                 696000  1275000
67                                 528000  1175000
68                                 396000  1025000
69                                 198000  950000
70                         >;
71                         fsl,soc-operating-points = <
72                                 /* KHz  uV */
73                                 696000  1275000
74                                 528000  1175000
75                                 396000  1175000
76                                 198000  1175000
77                         >;
78                         clocks = <&clks IMX6UL_CLK_ARM>,
79                                  <&clks IMX6UL_CLK_PLL2_BUS>,
80                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
81                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
82                                  <&clks IMX6UL_CLK_STEP>,
83                                  <&clks IMX6UL_CLK_PLL1_SW>,
84                                  <&clks IMX6UL_CLK_PLL1_SYS>;
85                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
86                                       "secondary_sel", "step", "pll1_sw",
87                                       "pll1_sys";
88                         arm-supply = <&reg_arm>;
89                         soc-supply = <&reg_soc>;
90                         nvmem-cells = <&cpu_speed_grade>;
91                         nvmem-cell-names = "speed_grade";
92                 };
93         };
94
95         intc: interrupt-controller@a01000 {
96                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
97                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
98                 #interrupt-cells = <3>;
99                 interrupt-controller;
100                 interrupt-parent = <&intc>;
101                 reg = <0x00a01000 0x1000>,
102                       <0x00a02000 0x2000>,
103                       <0x00a04000 0x2000>,
104                       <0x00a06000 0x2000>;
105         };
106
107         timer {
108                 compatible = "arm,armv7-timer";
109                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
110                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
111                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
112                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
113                 interrupt-parent = <&intc>;
114                 status = "disabled";
115         };
116
117         ckil: clock-cli {
118                 compatible = "fixed-clock";
119                 #clock-cells = <0>;
120                 clock-frequency = <32768>;
121                 clock-output-names = "ckil";
122         };
123
124         osc: clock-osc {
125                 compatible = "fixed-clock";
126                 #clock-cells = <0>;
127                 clock-frequency = <24000000>;
128                 clock-output-names = "osc";
129         };
130
131         ipp_di0: clock-di0 {
132                 compatible = "fixed-clock";
133                 #clock-cells = <0>;
134                 clock-frequency = <0>;
135                 clock-output-names = "ipp_di0";
136         };
137
138         ipp_di1: clock-di1 {
139                 compatible = "fixed-clock";
140                 #clock-cells = <0>;
141                 clock-frequency = <0>;
142                 clock-output-names = "ipp_di1";
143         };
144
145         tempmon: tempmon {
146                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
147                 interrupt-parent = <&gpc>;
148                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
149                 fsl,tempmon = <&anatop>;
150                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
151                 nvmem-cell-names = "calib", "temp_grade";
152                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
153         };
154
155         pmu {
156                 compatible = "arm,cortex-a7-pmu";
157                 interrupt-parent = <&gpc>;
158                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
159         };
160
161         soc {
162                 #address-cells = <1>;
163                 #size-cells = <1>;
164                 compatible = "simple-bus";
165                 interrupt-parent = <&gpc>;
166                 ranges;
167
168                 ocram: sram@900000 {
169                         compatible = "mmio-sram";
170                         reg = <0x00900000 0x20000>;
171                 };
172
173                 dma_apbh: dma-apbh@1804000 {
174                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
175                         reg = <0x01804000 0x2000>;
176                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
177                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
178                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
179                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
180                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
181                         #dma-cells = <1>;
182                         dma-channels = <4>;
183                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
184                 };
185
186                 gpmi: gpmi-nand@1806000         {
187                         compatible = "fsl,imx6q-gpmi-nand";
188                         #address-cells = <1>;
189                         #size-cells = <1>;
190                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
191                         reg-names = "gpmi-nand", "bch";
192                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
193                         interrupt-names = "bch";
194                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
195                                  <&clks IMX6UL_CLK_GPMI_APB>,
196                                  <&clks IMX6UL_CLK_GPMI_BCH>,
197                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
198                                  <&clks IMX6UL_CLK_PER_BCH>;
199                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
200                                       "gpmi_bch_apb", "per1_bch";
201                         dmas = <&dma_apbh 0>;
202                         dma-names = "rx-tx";
203                         status = "disabled";
204                 };
205
206                 aips1: aips-bus@2000000 {
207                         compatible = "fsl,aips-bus", "simple-bus";
208                         #address-cells = <1>;
209                         #size-cells = <1>;
210                         reg = <0x02000000 0x100000>;
211                         ranges;
212
213                         spba-bus@2000000 {
214                                 compatible = "fsl,spba-bus", "simple-bus";
215                                 #address-cells = <1>;
216                                 #size-cells = <1>;
217                                 reg = <0x02000000 0x40000>;
218                                 ranges;
219
220                                 ecspi1: spi@2008000 {
221                                         #address-cells = <1>;
222                                         #size-cells = <0>;
223                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
224                                         reg = <0x02008000 0x4000>;
225                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
226                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
227                                                  <&clks IMX6UL_CLK_ECSPI1>;
228                                         clock-names = "ipg", "per";
229                                         status = "disabled";
230                                 };
231
232                                 ecspi2: spi@200c000 {
233                                         #address-cells = <1>;
234                                         #size-cells = <0>;
235                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
236                                         reg = <0x0200c000 0x4000>;
237                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
239                                                  <&clks IMX6UL_CLK_ECSPI2>;
240                                         clock-names = "ipg", "per";
241                                         status = "disabled";
242                                 };
243
244                                 ecspi3: spi@2010000 {
245                                         #address-cells = <1>;
246                                         #size-cells = <0>;
247                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
248                                         reg = <0x02010000 0x4000>;
249                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
250                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
251                                                  <&clks IMX6UL_CLK_ECSPI3>;
252                                         clock-names = "ipg", "per";
253                                         status = "disabled";
254                                 };
255
256                                 ecspi4: spi@2014000 {
257                                         #address-cells = <1>;
258                                         #size-cells = <0>;
259                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
260                                         reg = <0x02014000 0x4000>;
261                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
262                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
263                                                  <&clks IMX6UL_CLK_ECSPI4>;
264                                         clock-names = "ipg", "per";
265                                         status = "disabled";
266                                 };
267
268                                 uart7: serial@2018000 {
269                                         compatible = "fsl,imx6ul-uart",
270                                                      "fsl,imx6q-uart";
271                                         reg = <0x02018000 0x4000>;
272                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
273                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
274                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
275                                         clock-names = "ipg", "per";
276                                         status = "disabled";
277                                 };
278
279                                 uart1: serial@2020000 {
280                                         compatible = "fsl,imx6ul-uart",
281                                                      "fsl,imx6q-uart";
282                                         reg = <0x02020000 0x4000>;
283                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
284                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
285                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
286                                         clock-names = "ipg", "per";
287                                         status = "disabled";
288                                 };
289
290                                 uart8: serial@2024000 {
291                                         compatible = "fsl,imx6ul-uart",
292                                                      "fsl,imx6q-uart";
293                                         reg = <0x02024000 0x4000>;
294                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
295                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
296                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
297                                         clock-names = "ipg", "per";
298                                         status = "disabled";
299                                 };
300
301                                 sai1: sai@2028000 {
302                                         #sound-dai-cells = <0>;
303                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
304                                         reg = <0x02028000 0x4000>;
305                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
306                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
307                                                  <&clks IMX6UL_CLK_SAI1>,
308                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
309                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
310                                         dmas = <&sdma 35 24 0>,
311                                                <&sdma 36 24 0>;
312                                         dma-names = "rx", "tx";
313                                         status = "disabled";
314                                 };
315
316                                 sai2: sai@202c000 {
317                                         #sound-dai-cells = <0>;
318                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
319                                         reg = <0x0202c000 0x4000>;
320                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
321                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
322                                                  <&clks IMX6UL_CLK_SAI2>,
323                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
324                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
325                                         dmas = <&sdma 37 24 0>,
326                                                <&sdma 38 24 0>;
327                                         dma-names = "rx", "tx";
328                                         status = "disabled";
329                                 };
330
331                                 sai3: sai@2030000 {
332                                         #sound-dai-cells = <0>;
333                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
334                                         reg = <0x02030000 0x4000>;
335                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
336                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
337                                                  <&clks IMX6UL_CLK_SAI3>,
338                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
339                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
340                                         dmas = <&sdma 39 24 0>,
341                                                <&sdma 40 24 0>;
342                                         dma-names = "rx", "tx";
343                                         status = "disabled";
344                                 };
345                         };
346
347                         tsc: tsc@2040000 {
348                                 compatible = "fsl,imx6ul-tsc";
349                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
350                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
351                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
352                                 clocks = <&clks IMX6UL_CLK_IPG>,
353                                          <&clks IMX6UL_CLK_ADC2>;
354                                 clock-names = "tsc", "adc";
355                                 status = "disabled";
356                         };
357
358                         pwm1: pwm@2080000 {
359                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
360                                 reg = <0x02080000 0x4000>;
361                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
362                                 clocks = <&clks IMX6UL_CLK_PWM1>,
363                                          <&clks IMX6UL_CLK_PWM1>;
364                                 clock-names = "ipg", "per";
365                                 #pwm-cells = <2>;
366                                 status = "disabled";
367                         };
368
369                         pwm2: pwm@2084000 {
370                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
371                                 reg = <0x02084000 0x4000>;
372                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
373                                 clocks = <&clks IMX6UL_CLK_PWM2>,
374                                          <&clks IMX6UL_CLK_PWM2>;
375                                 clock-names = "ipg", "per";
376                                 #pwm-cells = <2>;
377                                 status = "disabled";
378                         };
379
380                         pwm3: pwm@2088000 {
381                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
382                                 reg = <0x02088000 0x4000>;
383                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
384                                 clocks = <&clks IMX6UL_CLK_PWM3>,
385                                          <&clks IMX6UL_CLK_PWM3>;
386                                 clock-names = "ipg", "per";
387                                 #pwm-cells = <2>;
388                                 status = "disabled";
389                         };
390
391                         pwm4: pwm@208c000 {
392                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
393                                 reg = <0x0208c000 0x4000>;
394                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
395                                 clocks = <&clks IMX6UL_CLK_PWM4>,
396                                          <&clks IMX6UL_CLK_PWM4>;
397                                 clock-names = "ipg", "per";
398                                 #pwm-cells = <2>;
399                                 status = "disabled";
400                         };
401
402                         can1: flexcan@2090000 {
403                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
404                                 reg = <0x02090000 0x4000>;
405                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
406                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
407                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
408                                 clock-names = "ipg", "per";
409                                 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
410                                 status = "disabled";
411                         };
412
413                         can2: flexcan@2094000 {
414                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
415                                 reg = <0x02094000 0x4000>;
416                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
417                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
418                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
419                                 clock-names = "ipg", "per";
420                                 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
421                                 status = "disabled";
422                         };
423
424                         gpt1: gpt@2098000 {
425                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
426                                 reg = <0x02098000 0x4000>;
427                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
428                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
429                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
430                                 clock-names = "ipg", "per";
431                         };
432
433                         gpio1: gpio@209c000 {
434                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
435                                 reg = <0x0209c000 0x4000>;
436                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
437                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
438                                 clocks = <&clks IMX6UL_CLK_GPIO1>;
439                                 gpio-controller;
440                                 #gpio-cells = <2>;
441                                 interrupt-controller;
442                                 #interrupt-cells = <2>;
443                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
444                                               <&iomuxc 16 33 16>;
445                         };
446
447                         gpio2: gpio@20a0000 {
448                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
449                                 reg = <0x020a0000 0x4000>;
450                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
451                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
452                                 clocks = <&clks IMX6UL_CLK_GPIO2>;
453                                 gpio-controller;
454                                 #gpio-cells = <2>;
455                                 interrupt-controller;
456                                 #interrupt-cells = <2>;
457                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
458                         };
459
460                         gpio3: gpio@20a4000 {
461                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
462                                 reg = <0x020a4000 0x4000>;
463                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
464                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
465                                 clocks = <&clks IMX6UL_CLK_GPIO3>;
466                                 gpio-controller;
467                                 #gpio-cells = <2>;
468                                 interrupt-controller;
469                                 #interrupt-cells = <2>;
470                                 gpio-ranges = <&iomuxc 0 65 29>;
471                         };
472
473                         gpio4: gpio@20a8000 {
474                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
475                                 reg = <0x020a8000 0x4000>;
476                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
477                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
478                                 clocks = <&clks IMX6UL_CLK_GPIO4>;
479                                 gpio-controller;
480                                 #gpio-cells = <2>;
481                                 interrupt-controller;
482                                 #interrupt-cells = <2>;
483                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
484                         };
485
486                         gpio5: gpio@20ac000 {
487                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
488                                 reg = <0x020ac000 0x4000>;
489                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
490                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
491                                 clocks = <&clks IMX6UL_CLK_GPIO5>;
492                                 gpio-controller;
493                                 #gpio-cells = <2>;
494                                 interrupt-controller;
495                                 #interrupt-cells = <2>;
496                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
497                         };
498
499                         fec2: ethernet@20b4000 {
500                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
501                                 reg = <0x020b4000 0x4000>;
502                                 interrupt-names = "int0", "pps";
503                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
504                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
505                                 clocks = <&clks IMX6UL_CLK_ENET>,
506                                          <&clks IMX6UL_CLK_ENET_AHB>,
507                                          <&clks IMX6UL_CLK_ENET_PTP>,
508                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
509                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
510                                 clock-names = "ipg", "ahb", "ptp",
511                                               "enet_clk_ref", "enet_out";
512                                 fsl,num-tx-queues=<1>;
513                                 fsl,num-rx-queues=<1>;
514                                 status = "disabled";
515                         };
516
517                         kpp: kpp@20b8000 {
518                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
519                                 reg = <0x020b8000 0x4000>;
520                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
521                                 clocks = <&clks IMX6UL_CLK_KPP>;
522                                 status = "disabled";
523                         };
524
525                         wdog1: wdog@20bc000 {
526                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
527                                 reg = <0x020bc000 0x4000>;
528                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
529                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
530                         };
531
532                         wdog2: wdog@20c0000 {
533                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
534                                 reg = <0x020c0000 0x4000>;
535                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
536                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
537                                 status = "disabled";
538                         };
539
540                         clks: ccm@20c4000 {
541                                 compatible = "fsl,imx6ul-ccm";
542                                 reg = <0x020c4000 0x4000>;
543                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
544                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
545                                 #clock-cells = <1>;
546                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
547                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
548                         };
549
550                         anatop: anatop@20c8000 {
551                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
552                                              "syscon", "simple-bus";
553                                 reg = <0x020c8000 0x1000>;
554                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
555                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
556                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
557
558                                 reg_3p0: regulator-3p0 {
559                                         compatible = "fsl,anatop-regulator";
560                                         regulator-name = "vdd3p0";
561                                         regulator-min-microvolt = <2625000>;
562                                         regulator-max-microvolt = <3400000>;
563                                         anatop-reg-offset = <0x120>;
564                                         anatop-vol-bit-shift = <8>;
565                                         anatop-vol-bit-width = <5>;
566                                         anatop-min-bit-val = <0>;
567                                         anatop-min-voltage = <2625000>;
568                                         anatop-max-voltage = <3400000>;
569                                         anatop-enable-bit = <0>;
570                                 };
571
572                                 reg_arm: regulator-vddcore {
573                                         compatible = "fsl,anatop-regulator";
574                                         regulator-name = "cpu";
575                                         regulator-min-microvolt = <725000>;
576                                         regulator-max-microvolt = <1450000>;
577                                         regulator-always-on;
578                                         anatop-reg-offset = <0x140>;
579                                         anatop-vol-bit-shift = <0>;
580                                         anatop-vol-bit-width = <5>;
581                                         anatop-delay-reg-offset = <0x170>;
582                                         anatop-delay-bit-shift = <24>;
583                                         anatop-delay-bit-width = <2>;
584                                         anatop-min-bit-val = <1>;
585                                         anatop-min-voltage = <725000>;
586                                         anatop-max-voltage = <1450000>;
587                                 };
588
589                                 reg_soc: regulator-vddsoc {
590                                         compatible = "fsl,anatop-regulator";
591                                         regulator-name = "vddsoc";
592                                         regulator-min-microvolt = <725000>;
593                                         regulator-max-microvolt = <1450000>;
594                                         regulator-always-on;
595                                         anatop-reg-offset = <0x140>;
596                                         anatop-vol-bit-shift = <18>;
597                                         anatop-vol-bit-width = <5>;
598                                         anatop-delay-reg-offset = <0x170>;
599                                         anatop-delay-bit-shift = <28>;
600                                         anatop-delay-bit-width = <2>;
601                                         anatop-min-bit-val = <1>;
602                                         anatop-min-voltage = <725000>;
603                                         anatop-max-voltage = <1450000>;
604                                 };
605                         };
606
607                         usbphy1: usbphy@20c9000 {
608                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
609                                 reg = <0x020c9000 0x1000>;
610                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
611                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
612                                 phy-3p0-supply = <&reg_3p0>;
613                                 fsl,anatop = <&anatop>;
614                         };
615
616                         usbphy2: usbphy@20ca000 {
617                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
618                                 reg = <0x020ca000 0x1000>;
619                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
620                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
621                                 phy-3p0-supply = <&reg_3p0>;
622                                 fsl,anatop = <&anatop>;
623                         };
624
625                         snvs: snvs@20cc000 {
626                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
627                                 reg = <0x020cc000 0x4000>;
628
629                                 snvs_rtc: snvs-rtc-lp {
630                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
631                                         regmap = <&snvs>;
632                                         offset = <0x34>;
633                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
634                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
635                                 };
636
637                                 snvs_poweroff: snvs-poweroff {
638                                         compatible = "syscon-poweroff";
639                                         regmap = <&snvs>;
640                                         offset = <0x38>;
641                                         value = <0x60>;
642                                         mask = <0x60>;
643                                         status = "disabled";
644                                 };
645
646                                 snvs_pwrkey: snvs-powerkey {
647                                         compatible = "fsl,sec-v4.0-pwrkey";
648                                         regmap = <&snvs>;
649                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
650                                         linux,keycode = <KEY_POWER>;
651                                         wakeup-source;
652                                 };
653
654                                 snvs_lpgpr: snvs-lpgpr {
655                                         compatible = "fsl,imx6ul-snvs-lpgpr";
656                                 };
657                         };
658
659                         epit1: epit@20d0000 {
660                                 reg = <0x020d0000 0x4000>;
661                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
662                         };
663
664                         epit2: epit@20d4000 {
665                                 reg = <0x020d4000 0x4000>;
666                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
667                         };
668
669                         src: src@20d8000 {
670                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
671                                 reg = <0x020d8000 0x4000>;
672                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
673                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
674                                 #reset-cells = <1>;
675                         };
676
677                         gpc: gpc@20dc000 {
678                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
679                                 reg = <0x020dc000 0x4000>;
680                                 interrupt-controller;
681                                 #interrupt-cells = <3>;
682                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
683                                 interrupt-parent = <&intc>;
684                         };
685
686                         iomuxc: iomuxc@20e0000 {
687                                 compatible = "fsl,imx6ul-iomuxc";
688                                 reg = <0x020e0000 0x4000>;
689                         };
690
691                         gpr: iomuxc-gpr@20e4000 {
692                                 compatible = "fsl,imx6ul-iomuxc-gpr",
693                                              "fsl,imx6q-iomuxc-gpr", "syscon";
694                                 reg = <0x020e4000 0x4000>;
695                         };
696
697                         gpt2: gpt@20e8000 {
698                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
699                                 reg = <0x020e8000 0x4000>;
700                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
701                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
702                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
703                                 clock-names = "ipg", "per";
704                         };
705
706                         sdma: sdma@20ec000 {
707                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
708                                              "fsl,imx35-sdma";
709                                 reg = <0x020ec000 0x4000>;
710                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
711                                 clocks = <&clks IMX6UL_CLK_SDMA>,
712                                          <&clks IMX6UL_CLK_SDMA>;
713                                 clock-names = "ipg", "ahb";
714                                 #dma-cells = <3>;
715                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
716                         };
717
718                         pwm5: pwm@20f0000 {
719                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
720                                 reg = <0x020f0000 0x4000>;
721                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
722                                 clocks = <&clks IMX6UL_CLK_PWM5>,
723                                          <&clks IMX6UL_CLK_PWM5>;
724                                 clock-names = "ipg", "per";
725                                 #pwm-cells = <2>;
726                                 status = "disabled";
727                         };
728
729                         pwm6: pwm@20f4000 {
730                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
731                                 reg = <0x020f4000 0x4000>;
732                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
733                                 clocks = <&clks IMX6UL_CLK_PWM6>,
734                                          <&clks IMX6UL_CLK_PWM6>;
735                                 clock-names = "ipg", "per";
736                                 #pwm-cells = <2>;
737                                 status = "disabled";
738                         };
739
740                         pwm7: pwm@20f8000 {
741                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
742                                 reg = <0x020f8000 0x4000>;
743                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
744                                 clocks = <&clks IMX6UL_CLK_PWM7>,
745                                          <&clks IMX6UL_CLK_PWM7>;
746                                 clock-names = "ipg", "per";
747                                 #pwm-cells = <2>;
748                                 status = "disabled";
749                         };
750
751                         pwm8: pwm@20fc000 {
752                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
753                                 reg = <0x020fc000 0x4000>;
754                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
755                                 clocks = <&clks IMX6UL_CLK_PWM8>,
756                                          <&clks IMX6UL_CLK_PWM8>;
757                                 clock-names = "ipg", "per";
758                                 #pwm-cells = <2>;
759                                 status = "disabled";
760                         };
761                 };
762
763                 aips2: aips-bus@2100000 {
764                         compatible = "fsl,aips-bus", "simple-bus";
765                         #address-cells = <1>;
766                         #size-cells = <1>;
767                         reg = <0x02100000 0x100000>;
768                         ranges;
769
770                         crypto: caam@2140000 {
771                                 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
772                                 #address-cells = <1>;
773                                 #size-cells = <1>;
774                                 reg = <0x2140000 0x3c000>;
775                                 ranges = <0 0x2140000 0x3c000>;
776                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
777                                 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
778                                          <&clks IMX6UL_CLK_CAAM_MEM>;
779                                 clock-names = "ipg", "aclk", "mem";
780
781                                 sec_jr0: jr0@1000 {
782                                         compatible = "fsl,sec-v4.0-job-ring";
783                                         reg = <0x1000 0x1000>;
784                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
785                                 };
786
787                                 sec_jr1: jr1@2000 {
788                                         compatible = "fsl,sec-v4.0-job-ring";
789                                         reg = <0x2000 0x1000>;
790                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
791                                 };
792
793                                 sec_jr2: jr2@3000 {
794                                         compatible = "fsl,sec-v4.0-job-ring";
795                                         reg = <0x3000 0x1000>;
796                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
797                                 };
798                         };
799
800                         usbotg1: usb@2184000 {
801                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
802                                 reg = <0x02184000 0x200>;
803                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
804                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
805                                 fsl,usbphy = <&usbphy1>;
806                                 fsl,usbmisc = <&usbmisc 0>;
807                                 fsl,anatop = <&anatop>;
808                                 ahb-burst-config = <0x0>;
809                                 tx-burst-size-dword = <0x10>;
810                                 rx-burst-size-dword = <0x10>;
811                                 status = "disabled";
812                         };
813
814                         usbotg2: usb@2184200 {
815                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
816                                 reg = <0x02184200 0x200>;
817                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
818                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
819                                 fsl,usbphy = <&usbphy2>;
820                                 fsl,usbmisc = <&usbmisc 1>;
821                                 ahb-burst-config = <0x0>;
822                                 tx-burst-size-dword = <0x10>;
823                                 rx-burst-size-dword = <0x10>;
824                                 status = "disabled";
825                         };
826
827                         usbmisc: usbmisc@2184800 {
828                                 #index-cells = <1>;
829                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
830                                 reg = <0x02184800 0x200>;
831                         };
832
833                         fec1: ethernet@2188000 {
834                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
835                                 reg = <0x02188000 0x4000>;
836                                 interrupt-names = "int0", "pps";
837                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
838                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
839                                 clocks = <&clks IMX6UL_CLK_ENET>,
840                                          <&clks IMX6UL_CLK_ENET_AHB>,
841                                          <&clks IMX6UL_CLK_ENET_PTP>,
842                                          <&clks IMX6UL_CLK_ENET_REF>,
843                                          <&clks IMX6UL_CLK_ENET_REF>;
844                                 clock-names = "ipg", "ahb", "ptp",
845                                               "enet_clk_ref", "enet_out";
846                                 fsl,num-tx-queues=<1>;
847                                 fsl,num-rx-queues=<1>;
848                                 status = "disabled";
849                         };
850
851                         usdhc1: usdhc@2190000 {
852                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
853                                 reg = <0x02190000 0x4000>;
854                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
855                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
856                                          <&clks IMX6UL_CLK_USDHC1>,
857                                          <&clks IMX6UL_CLK_USDHC1>;
858                                 clock-names = "ipg", "ahb", "per";
859                                 bus-width = <4>;
860                                 status = "disabled";
861                         };
862
863                         usdhc2: usdhc@2194000 {
864                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
865                                 reg = <0x02194000 0x4000>;
866                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
867                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
868                                          <&clks IMX6UL_CLK_USDHC2>,
869                                          <&clks IMX6UL_CLK_USDHC2>;
870                                 clock-names = "ipg", "ahb", "per";
871                                 bus-width = <4>;
872                                 status = "disabled";
873                         };
874
875                         adc1: adc@2198000 {
876                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
877                                 reg = <0x02198000 0x4000>;
878                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
879                                 clocks = <&clks IMX6UL_CLK_ADC1>;
880                                 num-channels = <2>;
881                                 clock-names = "adc";
882                                 fsl,adck-max-frequency = <30000000>, <40000000>,
883                                                          <20000000>;
884                                 status = "disabled";
885                         };
886
887                         i2c1: i2c@21a0000 {
888                                 #address-cells = <1>;
889                                 #size-cells = <0>;
890                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
891                                 reg = <0x021a0000 0x4000>;
892                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
893                                 clocks = <&clks IMX6UL_CLK_I2C1>;
894                                 status = "disabled";
895                         };
896
897                         i2c2: i2c@21a4000 {
898                                 #address-cells = <1>;
899                                 #size-cells = <0>;
900                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
901                                 reg = <0x021a4000 0x4000>;
902                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
903                                 clocks = <&clks IMX6UL_CLK_I2C2>;
904                                 status = "disabled";
905                         };
906
907                         i2c3: i2c@21a8000 {
908                                 #address-cells = <1>;
909                                 #size-cells = <0>;
910                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
911                                 reg = <0x021a8000 0x4000>;
912                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
913                                 clocks = <&clks IMX6UL_CLK_I2C3>;
914                                 status = "disabled";
915                         };
916
917                         mmdc: mmdc@21b0000 {
918                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
919                                 reg = <0x021b0000 0x4000>;
920                                 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
921                         };
922
923                         weim: weim@21b8000 {
924                                 #address-cells = <2>;
925                                 #size-cells = <1>;
926                                 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
927                                 reg = <0x021b8000 0x4000>;
928                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
929                                 clocks = <&clks IMX6UL_CLK_EIM>;
930                                 fsl,weim-cs-gpr = <&gpr>;
931                                 status = "disabled";
932                         };
933
934                         ocotp: ocotp-ctrl@21bc000 {
935                                 #address-cells = <1>;
936                                 #size-cells = <1>;
937                                 compatible = "fsl,imx6ul-ocotp", "syscon";
938                                 reg = <0x021bc000 0x4000>;
939                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
940
941                                 tempmon_calib: calib@38 {
942                                         reg = <0x38 4>;
943                                 };
944
945                                 tempmon_temp_grade: temp-grade@20 {
946                                         reg = <0x20 4>;
947                                 };
948
949                                 cpu_speed_grade: speed-grade@10 {
950                                         reg = <0x10 4>;
951                                 };
952                         };
953
954                         lcdif: lcdif@21c8000 {
955                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
956                                 reg = <0x021c8000 0x4000>;
957                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
958                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
959                                          <&clks IMX6UL_CLK_LCDIF_APB>,
960                                          <&clks IMX6UL_CLK_DUMMY>;
961                                 clock-names = "pix", "axi", "disp_axi";
962                                 status = "disabled";
963                         };
964
965                         qspi: spi@21e0000 {
966                                 #address-cells = <1>;
967                                 #size-cells = <0>;
968                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
969                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
970                                 reg-names = "QuadSPI", "QuadSPI-memory";
971                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
972                                 clocks = <&clks IMX6UL_CLK_QSPI>,
973                                          <&clks IMX6UL_CLK_QSPI>;
974                                 clock-names = "qspi_en", "qspi";
975                                 status = "disabled";
976                         };
977
978                         wdog3: wdog@21e4000 {
979                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
980                                 reg = <0x021e4000 0x4000>;
981                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
982                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
983                                 status = "disabled";
984                         };
985
986                         uart2: serial@21e8000 {
987                                 compatible = "fsl,imx6ul-uart",
988                                              "fsl,imx6q-uart";
989                                 reg = <0x021e8000 0x4000>;
990                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
991                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
992                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
993                                 clock-names = "ipg", "per";
994                                 status = "disabled";
995                         };
996
997                         uart3: serial@21ec000 {
998                                 compatible = "fsl,imx6ul-uart",
999                                              "fsl,imx6q-uart";
1000                                 reg = <0x021ec000 0x4000>;
1001                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1002                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1003                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
1004                                 clock-names = "ipg", "per";
1005                                 status = "disabled";
1006                         };
1007
1008                         uart4: serial@21f0000 {
1009                                 compatible = "fsl,imx6ul-uart",
1010                                              "fsl,imx6q-uart";
1011                                 reg = <0x021f0000 0x4000>;
1012                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1014                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
1015                                 clock-names = "ipg", "per";
1016                                 status = "disabled";
1017                         };
1018
1019                         uart5: serial@21f4000 {
1020                                 compatible = "fsl,imx6ul-uart",
1021                                              "fsl,imx6q-uart";
1022                                 reg = <0x021f4000 0x4000>;
1023                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1024                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1025                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1026                                 clock-names = "ipg", "per";
1027                                 status = "disabled";
1028                         };
1029
1030                         i2c4: i2c@21f8000 {
1031                                 #address-cells = <1>;
1032                                 #size-cells = <0>;
1033                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1034                                 reg = <0x021f8000 0x4000>;
1035                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1036                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1037                                 status = "disabled";
1038                         };
1039
1040                         uart6: serial@21fc000 {
1041                                 compatible = "fsl,imx6ul-uart",
1042                                              "fsl,imx6q-uart";
1043                                 reg = <0x021fc000 0x4000>;
1044                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1045                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1046                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1047                                 clock-names = "ipg", "per";
1048                                 status = "disabled";
1049                         };
1050                 };
1051         };
1052 };