ARM: dts: imx7: Correct mask for GIC PPI interrupts
[muen/linux.git] / arch / arm / boot / dts / imx7d.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
5
6 #include "imx7s.dtsi"
7 #include <dt-bindings/reset/imx7-reset.h>
8
9 / {
10         cpus {
11                 cpu0: cpu@0 {
12                         clock-frequency = <996000000>;
13                         operating-points-v2 = <&cpu0_opp_table>;
14                         #cooling-cells = <2>;
15                 };
16
17                 cpu1: cpu@1 {
18                         compatible = "arm,cortex-a7";
19                         device_type = "cpu";
20                         reg = <1>;
21                         clock-frequency = <996000000>;
22                         operating-points-v2 = <&cpu0_opp_table>;
23                         cpu-idle-states = <&cpu_sleep_wait>;
24                 };
25         };
26
27         timer {
28                 compatible = "arm,armv7-timer";
29                 interrupt-parent = <&intc>;
30                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
31                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
32                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
33                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
34         };
35
36         cpu0_opp_table: opp-table {
37                 compatible = "operating-points-v2";
38                 opp-shared;
39
40                 opp-792000000 {
41                         opp-hz = /bits/ 64 <792000000>;
42                         opp-microvolt = <975000>;
43                         clock-latency-ns = <150000>;
44                 };
45
46                 opp-996000000 {
47                         opp-hz = /bits/ 64 <996000000>;
48                         opp-microvolt = <1075000>;
49                         clock-latency-ns = <150000>;
50                         opp-suspend;
51                 };
52         };
53
54         usbphynop2: usbphynop2 {
55                 compatible = "usb-nop-xceiv";
56                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
57                 clock-names = "main_clk";
58                 #phy-cells = <0>;
59         };
60
61         soc {
62                 etm@3007d000 {
63                         compatible = "arm,coresight-etm3x", "arm,primecell";
64                         reg = <0x3007d000 0x1000>;
65
66                         /*
67                          * System will hang if added nosmp in kernel command line
68                          * without arm,primecell-periphid because amba bus try to
69                          * read id and core1 power off at this time.
70                          */
71                         arm,primecell-periphid = <0xbb956>;
72                         cpu = <&cpu1>;
73                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
74                         clock-names = "apb_pclk";
75
76                         out-ports {
77                                 port {
78                                         etm1_out_port: endpoint {
79                                                 remote-endpoint = <&ca_funnel_in_port1>;
80                                         };
81                                 };
82                         };
83                 };
84
85                 intc: interrupt-controller@31001000 {
86                         compatible = "arm,cortex-a7-gic";
87                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
88                         #interrupt-cells = <3>;
89                         interrupt-controller;
90                         interrupt-parent = <&intc>;
91                         reg = <0x31001000 0x1000>,
92                               <0x31002000 0x2000>,
93                               <0x31004000 0x2000>,
94                               <0x31006000 0x2000>;
95                 };
96         };
97 };
98
99 &aips3 {
100         usbotg2: usb@30b20000 {
101                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
102                 reg = <0x30b20000 0x200>;
103                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
104                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
105                 fsl,usbphy = <&usbphynop2>;
106                 fsl,usbmisc = <&usbmisc2 0>;
107                 phy-clkgate-delay-us = <400>;
108                 status = "disabled";
109         };
110
111         usbmisc2: usbmisc@30b20200 {
112                 #index-cells = <1>;
113                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
114                 reg = <0x30b20200 0x200>;
115         };
116
117         fec2: ethernet@30bf0000 {
118                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
119                 reg = <0x30bf0000 0x10000>;
120                 interrupt-names = "int0", "int1", "int2", "pps";
121                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
122                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
123                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
124                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
125                 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
126                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
127                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
128                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
129                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
130                 clock-names = "ipg", "ahb", "ptp",
131                         "enet_clk_ref", "enet_out";
132                 fsl,num-tx-queues=<3>;
133                 fsl,num-rx-queues=<3>;
134                 status = "disabled";
135         };
136
137         pcie: pcie@33800000 {
138                 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
139                 reg = <0x33800000 0x4000>,
140                       <0x4ff00000 0x80000>;
141                 reg-names = "dbi", "config";
142                 #address-cells = <3>;
143                 #size-cells = <2>;
144                 device_type = "pci";
145                 bus-range = <0x00 0xff>;
146                 ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
147                           0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
148                 num-lanes = <1>;
149                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
150                 interrupt-names = "msi";
151                 #interrupt-cells = <1>;
152                 interrupt-map-mask = <0 0 0 0x7>;
153                 /*
154                  * Reference manual lists pci irqs incorrectly
155                  * Real hardware ordering is same as imx6: D+MSI, C, B, A
156                  */
157                 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
158                                 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
159                                 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
160                                 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
161                 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
162                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
163                          <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
164                 clock-names = "pcie", "pcie_bus", "pcie_phy";
165                 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
166                                   <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
167                 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
168                                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
169
170                 fsl,max-link-speed = <2>;
171                 power-domains = <&pgc_pcie_phy>;
172                 resets = <&src IMX7_RESET_PCIEPHY>,
173                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
174                          <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
175                 reset-names = "pciephy", "apps", "turnoff";
176                 status = "disabled";
177         };
178 };
179
180 &ca_funnel_in_ports {
181         #address-cells = <1>;
182         #size-cells = <0>;
183
184         port@1 {
185                 reg = <1>;
186                 ca_funnel_in_port1: endpoint {
187                         remote-endpoint = <&etm1_out_port>;
188                 };
189         };
190 };