826224bf7f4fe8f8320671a15845c37beb06cdd4
[muen/linux.git] / arch / arm / boot / dts / imx7d.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
5
6 #include "imx7s.dtsi"
7 #include <dt-bindings/reset/imx7-reset.h>
8
9 / {
10         cpus {
11                 cpu0: cpu@0 {
12                         clock-frequency = <996000000>;
13                         operating-points-v2 = <&cpu0_opp_table>;
14                         #cooling-cells = <2>;
15                 };
16
17                 cpu1: cpu@1 {
18                         compatible = "arm,cortex-a7";
19                         device_type = "cpu";
20                         reg = <1>;
21                         clock-frequency = <996000000>;
22                         operating-points-v2 = <&cpu0_opp_table>;
23                         cpu-idle-states = <&cpu_sleep_wait>;
24                 };
25         };
26
27         cpu0_opp_table: opp-table {
28                 compatible = "operating-points-v2";
29                 opp-shared;
30
31                 opp-792000000 {
32                         opp-hz = /bits/ 64 <792000000>;
33                         opp-microvolt = <975000>;
34                         clock-latency-ns = <150000>;
35                 };
36
37                 opp-996000000 {
38                         opp-hz = /bits/ 64 <996000000>;
39                         opp-microvolt = <1075000>;
40                         clock-latency-ns = <150000>;
41                         opp-suspend;
42                 };
43         };
44
45         usbphynop2: usbphynop2 {
46                 compatible = "usb-nop-xceiv";
47                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
48                 clock-names = "main_clk";
49                 #phy-cells = <0>;
50         };
51
52         soc {
53                 etm@3007d000 {
54                         compatible = "arm,coresight-etm3x", "arm,primecell";
55                         reg = <0x3007d000 0x1000>;
56
57                         /*
58                          * System will hang if added nosmp in kernel command line
59                          * without arm,primecell-periphid because amba bus try to
60                          * read id and core1 power off at this time.
61                          */
62                         arm,primecell-periphid = <0xbb956>;
63                         cpu = <&cpu1>;
64                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
65                         clock-names = "apb_pclk";
66
67                         out-ports {
68                                 port {
69                                         etm1_out_port: endpoint {
70                                                 remote-endpoint = <&ca_funnel_in_port1>;
71                                         };
72                                 };
73                         };
74                 };
75         };
76 };
77
78 &aips3 {
79         usbotg2: usb@30b20000 {
80                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
81                 reg = <0x30b20000 0x200>;
82                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
83                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
84                 fsl,usbphy = <&usbphynop2>;
85                 fsl,usbmisc = <&usbmisc2 0>;
86                 phy-clkgate-delay-us = <400>;
87                 status = "disabled";
88         };
89
90         usbmisc2: usbmisc@30b20200 {
91                 #index-cells = <1>;
92                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
93                 reg = <0x30b20200 0x200>;
94         };
95
96         fec2: ethernet@30bf0000 {
97                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
98                 reg = <0x30bf0000 0x10000>;
99                 interrupt-names = "int0", "int1", "int2", "pps";
100                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
101                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
102                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
103                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
104                 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
105                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
106                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
107                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
108                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
109                 clock-names = "ipg", "ahb", "ptp",
110                         "enet_clk_ref", "enet_out";
111                 fsl,num-tx-queues=<3>;
112                 fsl,num-rx-queues=<3>;
113                 status = "disabled";
114         };
115
116         pcie: pcie@33800000 {
117                 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
118                 reg = <0x33800000 0x4000>,
119                       <0x4ff00000 0x80000>;
120                 reg-names = "dbi", "config";
121                 #address-cells = <3>;
122                 #size-cells = <2>;
123                 device_type = "pci";
124                 bus-range = <0x00 0xff>;
125                 ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
126                           0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
127                 num-lanes = <1>;
128                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
129                 interrupt-names = "msi";
130                 #interrupt-cells = <1>;
131                 interrupt-map-mask = <0 0 0 0x7>;
132                 /*
133                  * Reference manual lists pci irqs incorrectly
134                  * Real hardware ordering is same as imx6: D+MSI, C, B, A
135                  */
136                 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
137                                 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
138                                 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
139                                 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
140                 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
141                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
142                          <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
143                 clock-names = "pcie", "pcie_bus", "pcie_phy";
144                 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
145                                   <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
146                 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
147                                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
148
149                 fsl,max-link-speed = <2>;
150                 power-domains = <&pgc_pcie_phy>;
151                 resets = <&src IMX7_RESET_PCIEPHY>,
152                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
153                          <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
154                 reset-names = "pciephy", "apps", "turnoff";
155                 status = "disabled";
156         };
157 };
158
159 &ca_funnel_in_ports {
160         #address-cells = <1>;
161         #size-cells = <0>;
162
163         port@1 {
164                 reg = <1>;
165                 ca_funnel_in_port1: endpoint {
166                         remote-endpoint = <&etm1_out_port>;
167                 };
168         };
169 };