477901c2061ce82673769265f62f4147e50cdeb3
[muen/linux.git] / arch / arm / boot / dts / imx7s.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
5
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx7d-pinfunc.h"
12
13 / {
14         #address-cells = <1>;
15         #size-cells = <1>;
16         /*
17          * The decompressor and also some bootloaders rely on a
18          * pre-existing /chosen node to be available to insert the
19          * command line and merge other ATAGS info.
20          */
21         chosen {};
22
23         aliases {
24                 gpio0 = &gpio1;
25                 gpio1 = &gpio2;
26                 gpio2 = &gpio3;
27                 gpio3 = &gpio4;
28                 gpio4 = &gpio5;
29                 gpio5 = &gpio6;
30                 gpio6 = &gpio7;
31                 i2c0 = &i2c1;
32                 i2c1 = &i2c2;
33                 i2c2 = &i2c3;
34                 i2c3 = &i2c4;
35                 mmc0 = &usdhc1;
36                 mmc1 = &usdhc2;
37                 mmc2 = &usdhc3;
38                 serial0 = &uart1;
39                 serial1 = &uart2;
40                 serial2 = &uart3;
41                 serial3 = &uart4;
42                 serial4 = &uart5;
43                 serial5 = &uart6;
44                 serial6 = &uart7;
45                 spi0 = &ecspi1;
46                 spi1 = &ecspi2;
47                 spi2 = &ecspi3;
48                 spi3 = &ecspi4;
49         };
50
51         cpus {
52                 #address-cells = <1>;
53                 #size-cells = <0>;
54
55                 idle-states {
56                         entry-method = "psci";
57
58                         cpu_sleep_wait: cpu-sleep-wait {
59                                 compatible = "arm,idle-state";
60                                 arm,psci-suspend-param = <0x0010000>;
61                                 local-timer-stop;
62                                 entry-latency-us = <100>;
63                                 exit-latency-us = <50>;
64                                 min-residency-us = <1000>;
65                         };
66                 };
67
68                 cpu0: cpu@0 {
69                         compatible = "arm,cortex-a7";
70                         device_type = "cpu";
71                         reg = <0>;
72                         clock-frequency = <792000000>;
73                         clock-latency = <61036>; /* two CLK32 periods */
74                         clocks = <&clks IMX7D_CLK_ARM>;
75                         cpu-idle-states = <&cpu_sleep_wait>;
76                 };
77         };
78
79         ckil: clock-cki {
80                 compatible = "fixed-clock";
81                 #clock-cells = <0>;
82                 clock-frequency = <32768>;
83                 clock-output-names = "ckil";
84         };
85
86         osc: clock-osc {
87                 compatible = "fixed-clock";
88                 #clock-cells = <0>;
89                 clock-frequency = <24000000>;
90                 clock-output-names = "osc";
91         };
92
93         usbphynop1: usbphynop1 {
94                 compatible = "usb-nop-xceiv";
95                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
96                 clock-names = "main_clk";
97                 #phy-cells = <0>;
98         };
99
100         usbphynop3: usbphynop3 {
101                 compatible = "usb-nop-xceiv";
102                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
103                 clock-names = "main_clk";
104                 #phy-cells = <0>;
105         };
106
107         pmu {
108                 compatible = "arm,cortex-a7-pmu";
109                 interrupt-parent = <&gpc>;
110                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
111                 interrupt-affinity = <&cpu0>;
112         };
113
114         replicator {
115                 /*
116                  * non-configurable replicators don't show up on the
117                  * AMBA bus.  As such no need to add "arm,primecell"
118                  */
119                 compatible = "arm,coresight-replicator";
120
121                 out-ports {
122                         #address-cells = <1>;
123                         #size-cells = <0>;
124                                 /* replicator output ports */
125                         port@0 {
126                                 reg = <0>;
127                                 replicator_out_port0: endpoint {
128                                         remote-endpoint = <&tpiu_in_port>;
129                                 };
130                         };
131
132                         port@1 {
133                                 reg = <1>;
134                                 replicator_out_port1: endpoint {
135                                         remote-endpoint = <&etr_in_port>;
136                                 };
137                         };
138                 };
139
140                 in-ports {
141                         port {
142                                 replicator_in_port0: endpoint {
143                                         remote-endpoint = <&etf_out_port>;
144                                 };
145                         };
146                 };
147         };
148
149         tempmon: tempmon {
150                 compatible = "fsl,imx7d-tempmon";
151                 interrupt-parent = <&gpc>;
152                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
153                 fsl,tempmon =<&anatop>;
154                 nvmem-cells = <&tempmon_calib>,
155                         <&tempmon_temp_grade>;
156                 nvmem-cell-names = "calib", "temp_grade";
157                 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
158         };
159
160         timer {
161                 compatible = "arm,armv7-timer";
162                 interrupt-parent = <&intc>;
163                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
164                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
165                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
166                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
167         };
168
169         soc {
170                 #address-cells = <1>;
171                 #size-cells = <1>;
172                 compatible = "simple-bus";
173                 interrupt-parent = <&gpc>;
174                 ranges;
175
176                 funnel@30041000 {
177                         compatible = "arm,coresight-funnel", "arm,primecell";
178                         reg = <0x30041000 0x1000>;
179                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
180                         clock-names = "apb_pclk";
181
182                         ca_funnel_in_ports: in-ports {
183                                 port {
184                                         ca_funnel_in_port0: endpoint {
185                                                 remote-endpoint = <&etm0_out_port>;
186                                         };
187                                 };
188
189                                 /* the other input ports are not connect to anything */
190                         };
191
192                         out-ports {
193                                 port {
194                                         ca_funnel_out_port0: endpoint {
195                                                 remote-endpoint = <&hugo_funnel_in_port0>;
196                                         };
197                                 };
198
199                         };
200                 };
201
202                 etm@3007c000 {
203                         compatible = "arm,coresight-etm3x", "arm,primecell";
204                         reg = <0x3007c000 0x1000>;
205                         cpu = <&cpu0>;
206                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
207                         clock-names = "apb_pclk";
208
209                         out-ports {
210                                 port {
211                                         etm0_out_port: endpoint {
212                                                 remote-endpoint = <&ca_funnel_in_port0>;
213                                         };
214                                 };
215                         };
216                 };
217
218                 funnel@30083000 {
219                         compatible = "arm,coresight-funnel", "arm,primecell";
220                         reg = <0x30083000 0x1000>;
221                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
222                         clock-names = "apb_pclk";
223
224                         in-ports {
225                                 #address-cells = <1>;
226                                 #size-cells = <0>;
227
228                                 port@0 {
229                                         reg = <0>;
230                                         hugo_funnel_in_port0: endpoint {
231                                                 remote-endpoint = <&ca_funnel_out_port0>;
232                                         };
233                                 };
234
235                                 port@1 {
236                                         reg = <1>;
237                                         hugo_funnel_in_port1: endpoint {
238                                                 /* M4 input */
239                                         };
240                                 };
241                                 /* the other input ports are not connect to anything */
242                         };
243
244                         out-ports {
245                                 port {
246                                         hugo_funnel_out_port0: endpoint {
247                                                 remote-endpoint = <&etf_in_port>;
248                                         };
249                                 };
250                         };
251                 };
252
253                 etf@30084000 {
254                         compatible = "arm,coresight-tmc", "arm,primecell";
255                         reg = <0x30084000 0x1000>;
256                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
257                         clock-names = "apb_pclk";
258
259                         in-ports {
260                                 port {
261                                         etf_in_port: endpoint {
262                                                 remote-endpoint = <&hugo_funnel_out_port0>;
263                                         };
264                                 };
265                         };
266
267                         out-ports {
268                                 port {
269                                         etf_out_port: endpoint {
270                                                 remote-endpoint = <&replicator_in_port0>;
271                                         };
272                                 };
273                         };
274                 };
275
276                 etr@30086000 {
277                         compatible = "arm,coresight-tmc", "arm,primecell";
278                         reg = <0x30086000 0x1000>;
279                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
280                         clock-names = "apb_pclk";
281
282                         in-ports {
283                                 port {
284                                         etr_in_port: endpoint {
285                                                 remote-endpoint = <&replicator_out_port1>;
286                                         };
287                                 };
288                         };
289                 };
290
291                 tpiu@30087000 {
292                         compatible = "arm,coresight-tpiu", "arm,primecell";
293                         reg = <0x30087000 0x1000>;
294                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
295                         clock-names = "apb_pclk";
296
297                         in-ports {
298                                 port {
299                                         tpiu_in_port: endpoint {
300                                                 remote-endpoint = <&replicator_out_port0>;
301                                         };
302                                 };
303                         };
304                 };
305
306                 intc: interrupt-controller@31001000 {
307                         compatible = "arm,cortex-a7-gic";
308                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
309                         #interrupt-cells = <3>;
310                         interrupt-controller;
311                         interrupt-parent = <&intc>;
312                         reg = <0x31001000 0x1000>,
313                               <0x31002000 0x2000>,
314                               <0x31004000 0x2000>,
315                               <0x31006000 0x2000>;
316                 };
317
318                 aips1: aips-bus@30000000 {
319                         compatible = "fsl,aips-bus", "simple-bus";
320                         #address-cells = <1>;
321                         #size-cells = <1>;
322                         reg = <0x30000000 0x400000>;
323                         ranges;
324
325                         gpio1: gpio@30200000 {
326                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
327                                 reg = <0x30200000 0x10000>;
328                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
329                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
330                                 gpio-controller;
331                                 #gpio-cells = <2>;
332                                 interrupt-controller;
333                                 #interrupt-cells = <2>;
334                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
335                         };
336
337                         gpio2: gpio@30210000 {
338                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
339                                 reg = <0x30210000 0x10000>;
340                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
341                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
342                                 gpio-controller;
343                                 #gpio-cells = <2>;
344                                 interrupt-controller;
345                                 #interrupt-cells = <2>;
346                                 gpio-ranges = <&iomuxc 0 13 32>;
347                         };
348
349                         gpio3: gpio@30220000 {
350                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
351                                 reg = <0x30220000 0x10000>;
352                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
353                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
354                                 gpio-controller;
355                                 #gpio-cells = <2>;
356                                 interrupt-controller;
357                                 #interrupt-cells = <2>;
358                                 gpio-ranges = <&iomuxc 0 45 29>;
359                         };
360
361                         gpio4: gpio@30230000 {
362                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
363                                 reg = <0x30230000 0x10000>;
364                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
365                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
366                                 gpio-controller;
367                                 #gpio-cells = <2>;
368                                 interrupt-controller;
369                                 #interrupt-cells = <2>;
370                                 gpio-ranges = <&iomuxc 0 74 24>;
371                         };
372
373                         gpio5: gpio@30240000 {
374                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
375                                 reg = <0x30240000 0x10000>;
376                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
377                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
378                                 gpio-controller;
379                                 #gpio-cells = <2>;
380                                 interrupt-controller;
381                                 #interrupt-cells = <2>;
382                                 gpio-ranges = <&iomuxc 0 98 18>;
383                         };
384
385                         gpio6: gpio@30250000 {
386                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
387                                 reg = <0x30250000 0x10000>;
388                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
389                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
390                                 gpio-controller;
391                                 #gpio-cells = <2>;
392                                 interrupt-controller;
393                                 #interrupt-cells = <2>;
394                                 gpio-ranges = <&iomuxc 0 116 23>;
395                         };
396
397                         gpio7: gpio@30260000 {
398                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
399                                 reg = <0x30260000 0x10000>;
400                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
401                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
402                                 gpio-controller;
403                                 #gpio-cells = <2>;
404                                 interrupt-controller;
405                                 #interrupt-cells = <2>;
406                                 gpio-ranges = <&iomuxc 0 139 16>;
407                         };
408
409                         wdog1: wdog@30280000 {
410                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
411                                 reg = <0x30280000 0x10000>;
412                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
413                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
414                         };
415
416                         wdog2: wdog@30290000 {
417                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
418                                 reg = <0x30290000 0x10000>;
419                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
420                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
421                                 status = "disabled";
422                         };
423
424                         wdog3: wdog@302a0000 {
425                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
426                                 reg = <0x302a0000 0x10000>;
427                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
428                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
429                                 status = "disabled";
430                         };
431
432                         wdog4: wdog@302b0000 {
433                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
434                                 reg = <0x302b0000 0x10000>;
435                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
436                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
437                                 status = "disabled";
438                         };
439
440                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
441                                 compatible = "fsl,imx7d-iomuxc-lpsr";
442                                 reg = <0x302c0000 0x10000>;
443                                 fsl,input-sel = <&iomuxc>;
444                         };
445
446                         gpt1: gpt@302d0000 {
447                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
448                                 reg = <0x302d0000 0x10000>;
449                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
450                                 clocks = <&clks IMX7D_CLK_DUMMY>,
451                                          <&clks IMX7D_GPT1_ROOT_CLK>;
452                                 clock-names = "ipg", "per";
453                         };
454
455                         gpt2: gpt@302e0000 {
456                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
457                                 reg = <0x302e0000 0x10000>;
458                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
459                                 clocks = <&clks IMX7D_CLK_DUMMY>,
460                                          <&clks IMX7D_GPT2_ROOT_CLK>;
461                                 clock-names = "ipg", "per";
462                                 status = "disabled";
463                         };
464
465                         gpt3: gpt@302f0000 {
466                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
467                                 reg = <0x302f0000 0x10000>;
468                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
469                                 clocks = <&clks IMX7D_CLK_DUMMY>,
470                                          <&clks IMX7D_GPT3_ROOT_CLK>;
471                                 clock-names = "ipg", "per";
472                                 status = "disabled";
473                         };
474
475                         gpt4: gpt@30300000 {
476                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
477                                 reg = <0x30300000 0x10000>;
478                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
479                                 clocks = <&clks IMX7D_CLK_DUMMY>,
480                                          <&clks IMX7D_GPT4_ROOT_CLK>;
481                                 clock-names = "ipg", "per";
482                                 status = "disabled";
483                         };
484
485                         kpp: kpp@30320000 {
486                                 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
487                                 reg = <0x30320000 0x10000>;
488                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
489                                 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
490                                 status = "disabled";
491                         };
492
493                         iomuxc: iomuxc@30330000 {
494                                 compatible = "fsl,imx7d-iomuxc";
495                                 reg = <0x30330000 0x10000>;
496                         };
497
498                         gpr: iomuxc-gpr@30340000 {
499                                 compatible = "fsl,imx7d-iomuxc-gpr",
500                                         "fsl,imx6q-iomuxc-gpr", "syscon";
501                                 reg = <0x30340000 0x10000>;
502                         };
503
504                         ocotp: ocotp-ctrl@30350000 {
505                                 #address-cells = <1>;
506                                 #size-cells = <1>;
507                                 compatible = "fsl,imx7d-ocotp", "syscon";
508                                 reg = <0x30350000 0x10000>;
509                                 clocks = <&clks IMX7D_OCOTP_CLK>;
510
511                                 tempmon_calib: calib@3c {
512                                         reg = <0x3c 0x4>;
513                                 };
514
515                                 tempmon_temp_grade: temp-grade@10 {
516                                         reg = <0x10 0x4>;
517                                 };
518                         };
519
520                         anatop: anatop@30360000 {
521                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
522                                         "syscon", "simple-bus";
523                                 reg = <0x30360000 0x10000>;
524                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
525                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
526
527                                 reg_1p0d: regulator-vdd1p0d {
528                                         compatible = "fsl,anatop-regulator";
529                                         regulator-name = "vdd1p0d";
530                                         regulator-min-microvolt = <800000>;
531                                         regulator-max-microvolt = <1200000>;
532                                         anatop-reg-offset = <0x210>;
533                                         anatop-vol-bit-shift = <8>;
534                                         anatop-vol-bit-width = <5>;
535                                         anatop-min-bit-val = <8>;
536                                         anatop-min-voltage = <800000>;
537                                         anatop-max-voltage = <1200000>;
538                                         anatop-enable-bit = <0>;
539                                 };
540
541                                 reg_1p2: regulator-vdd1p2 {
542                                         compatible = "fsl,anatop-regulator";
543                                         regulator-name = "vdd1p2";
544                                         regulator-min-microvolt = <1100000>;
545                                         regulator-max-microvolt = <1300000>;
546                                         anatop-reg-offset = <0x220>;
547                                         anatop-vol-bit-shift = <8>;
548                                         anatop-vol-bit-width = <5>;
549                                         anatop-min-bit-val = <0x14>;
550                                         anatop-min-voltage = <1100000>;
551                                         anatop-max-voltage = <1300000>;
552                                         anatop-enable-bit = <0>;
553                                 };
554                         };
555
556                         snvs: snvs@30370000 {
557                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
558                                 reg = <0x30370000 0x10000>;
559
560                                 snvs_rtc: snvs-rtc-lp {
561                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
562                                         regmap = <&snvs>;
563                                         offset = <0x34>;
564                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
565                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
566                                         clocks = <&clks IMX7D_SNVS_CLK>;
567                                         clock-names = "snvs-rtc";
568                                 };
569
570                                 snvs_pwrkey: snvs-powerkey {
571                                         compatible = "fsl,sec-v4.0-pwrkey";
572                                         regmap = <&snvs>;
573                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
574                                         linux,keycode = <KEY_POWER>;
575                                         wakeup-source;
576                                 };
577                         };
578
579                         clks: ccm@30380000 {
580                                 compatible = "fsl,imx7d-ccm";
581                                 reg = <0x30380000 0x10000>;
582                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
583                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
584                                 #clock-cells = <1>;
585                                 clocks = <&ckil>, <&osc>;
586                                 clock-names = "ckil", "osc";
587                         };
588
589                         src: src@30390000 {
590                                 compatible = "fsl,imx7d-src", "syscon";
591                                 reg = <0x30390000 0x10000>;
592                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
593                                 #reset-cells = <1>;
594                         };
595
596                         gpc: gpc@303a0000 {
597                                 compatible = "fsl,imx7d-gpc";
598                                 reg = <0x303a0000 0x10000>;
599                                 interrupt-controller;
600                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
601                                 #interrupt-cells = <3>;
602                                 interrupt-parent = <&intc>;
603                                 #power-domain-cells = <1>;
604
605                                 pgc {
606                                         #address-cells = <1>;
607                                         #size-cells = <0>;
608
609                                         pgc_pcie_phy: pgc-power-domain@1 {
610                                                 #power-domain-cells = <0>;
611                                                 reg = <1>;
612                                                 power-supply = <&reg_1p0d>;
613                                         };
614                                 };
615                         };
616                 };
617
618                 aips2: aips-bus@30400000 {
619                         compatible = "fsl,aips-bus", "simple-bus";
620                         #address-cells = <1>;
621                         #size-cells = <1>;
622                         reg = <0x30400000 0x400000>;
623                         ranges;
624
625                         adc1: adc@30610000 {
626                                 compatible = "fsl,imx7d-adc";
627                                 reg = <0x30610000 0x10000>;
628                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
629                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
630                                 clock-names = "adc";
631                                 status = "disabled";
632                         };
633
634                         adc2: adc@30620000 {
635                                 compatible = "fsl,imx7d-adc";
636                                 reg = <0x30620000 0x10000>;
637                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
638                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
639                                 clock-names = "adc";
640                                 status = "disabled";
641                         };
642
643                         ecspi4: spi@30630000 {
644                                 #address-cells = <1>;
645                                 #size-cells = <0>;
646                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
647                                 reg = <0x30630000 0x10000>;
648                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
649                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
650                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
651                                 clock-names = "ipg", "per";
652                                 status = "disabled";
653                         };
654
655                         pwm1: pwm@30660000 {
656                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
657                                 reg = <0x30660000 0x10000>;
658                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
659                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
660                                          <&clks IMX7D_PWM1_ROOT_CLK>;
661                                 clock-names = "ipg", "per";
662                                 #pwm-cells = <3>;
663                                 status = "disabled";
664                         };
665
666                         pwm2: pwm@30670000 {
667                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
668                                 reg = <0x30670000 0x10000>;
669                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
670                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
671                                          <&clks IMX7D_PWM2_ROOT_CLK>;
672                                 clock-names = "ipg", "per";
673                                 #pwm-cells = <3>;
674                                 status = "disabled";
675                         };
676
677                         pwm3: pwm@30680000 {
678                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
679                                 reg = <0x30680000 0x10000>;
680                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
681                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
682                                          <&clks IMX7D_PWM3_ROOT_CLK>;
683                                 clock-names = "ipg", "per";
684                                 #pwm-cells = <3>;
685                                 status = "disabled";
686                         };
687
688                         pwm4: pwm@30690000 {
689                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
690                                 reg = <0x30690000 0x10000>;
691                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
693                                          <&clks IMX7D_PWM4_ROOT_CLK>;
694                                 clock-names = "ipg", "per";
695                                 #pwm-cells = <3>;
696                                 status = "disabled";
697                         };
698
699                         lcdif: lcdif@30730000 {
700                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
701                                 reg = <0x30730000 0x10000>;
702                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
703                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
704                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
705                                 clock-names = "pix", "axi";
706                                 status = "disabled";
707                         };
708                 };
709
710                 aips3: aips-bus@30800000 {
711                         compatible = "fsl,aips-bus", "simple-bus";
712                         #address-cells = <1>;
713                         #size-cells = <1>;
714                         reg = <0x30800000 0x400000>;
715                         ranges;
716
717                         spba-bus@30800000 {
718                                 compatible = "fsl,spba-bus", "simple-bus";
719                                 #address-cells = <1>;
720                                 #size-cells = <1>;
721                                 reg = <0x30800000 0x100000>;
722                                 ranges;
723
724                                 ecspi1: spi@30820000 {
725                                         #address-cells = <1>;
726                                         #size-cells = <0>;
727                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
728                                         reg = <0x30820000 0x10000>;
729                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
730                                         clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
731                                                 <&clks IMX7D_ECSPI1_ROOT_CLK>;
732                                         clock-names = "ipg", "per";
733                                         status = "disabled";
734                                 };
735
736                                 ecspi2: spi@30830000 {
737                                         #address-cells = <1>;
738                                         #size-cells = <0>;
739                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
740                                         reg = <0x30830000 0x10000>;
741                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
742                                         clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
743                                                 <&clks IMX7D_ECSPI2_ROOT_CLK>;
744                                         clock-names = "ipg", "per";
745                                         status = "disabled";
746                                 };
747
748                                 ecspi3: spi@30840000 {
749                                         #address-cells = <1>;
750                                         #size-cells = <0>;
751                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
752                                         reg = <0x30840000 0x10000>;
753                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
754                                         clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
755                                                 <&clks IMX7D_ECSPI3_ROOT_CLK>;
756                                         clock-names = "ipg", "per";
757                                         status = "disabled";
758                                 };
759
760                                 uart1: serial@30860000 {
761                                         compatible = "fsl,imx7d-uart",
762                                                      "fsl,imx6q-uart";
763                                         reg = <0x30860000 0x10000>;
764                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
765                                         clocks = <&clks IMX7D_UART1_ROOT_CLK>,
766                                                 <&clks IMX7D_UART1_ROOT_CLK>;
767                                         clock-names = "ipg", "per";
768                                         status = "disabled";
769                                 };
770
771                                 uart2: serial@30890000 {
772                                         compatible = "fsl,imx7d-uart",
773                                                      "fsl,imx6q-uart";
774                                         reg = <0x30890000 0x10000>;
775                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
776                                         clocks = <&clks IMX7D_UART2_ROOT_CLK>,
777                                                 <&clks IMX7D_UART2_ROOT_CLK>;
778                                         clock-names = "ipg", "per";
779                                         status = "disabled";
780                                 };
781
782                                 uart3: serial@30880000 {
783                                         compatible = "fsl,imx7d-uart",
784                                                      "fsl,imx6q-uart";
785                                         reg = <0x30880000 0x10000>;
786                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
787                                         clocks = <&clks IMX7D_UART3_ROOT_CLK>,
788                                                 <&clks IMX7D_UART3_ROOT_CLK>;
789                                         clock-names = "ipg", "per";
790                                         status = "disabled";
791                                 };
792
793                                 sai1: sai@308a0000 {
794                                         #sound-dai-cells = <0>;
795                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
796                                         reg = <0x308a0000 0x10000>;
797                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
798                                         clocks = <&clks IMX7D_SAI1_IPG_CLK>,
799                                                  <&clks IMX7D_SAI1_ROOT_CLK>,
800                                                  <&clks IMX7D_CLK_DUMMY>,
801                                                  <&clks IMX7D_CLK_DUMMY>;
802                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
803                                         dma-names = "rx", "tx";
804                                         dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
805                                         status = "disabled";
806                                 };
807
808                                 sai2: sai@308b0000 {
809                                         #sound-dai-cells = <0>;
810                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
811                                         reg = <0x308b0000 0x10000>;
812                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
813                                         clocks = <&clks IMX7D_SAI2_IPG_CLK>,
814                                                  <&clks IMX7D_SAI2_ROOT_CLK>,
815                                                  <&clks IMX7D_CLK_DUMMY>,
816                                                  <&clks IMX7D_CLK_DUMMY>;
817                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
818                                         dma-names = "rx", "tx";
819                                         dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
820                                         status = "disabled";
821                                 };
822
823                                 sai3: sai@308c0000 {
824                                         #sound-dai-cells = <0>;
825                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
826                                         reg = <0x308c0000 0x10000>;
827                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
828                                         clocks = <&clks IMX7D_SAI3_IPG_CLK>,
829                                                  <&clks IMX7D_SAI3_ROOT_CLK>,
830                                                  <&clks IMX7D_CLK_DUMMY>,
831                                                  <&clks IMX7D_CLK_DUMMY>;
832                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
833                                         dma-names = "rx", "tx";
834                                         dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
835                                         status = "disabled";
836                                 };
837                         };
838
839                         crypto: caam@30900000 {
840                                 compatible = "fsl,sec-v4.0";
841                                 #address-cells = <1>;
842                                 #size-cells = <1>;
843                                 reg = <0x30900000 0x40000>;
844                                 ranges = <0 0x30900000 0x40000>;
845                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
846                                 clocks = <&clks IMX7D_CAAM_CLK>,
847                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
848                                 clock-names = "ipg", "aclk";
849
850                                 sec_jr0: jr0@1000 {
851                                         compatible = "fsl,sec-v4.0-job-ring";
852                                         reg = <0x1000 0x1000>;
853                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
854                                 };
855
856                                 sec_jr1: jr1@2000 {
857                                         compatible = "fsl,sec-v4.0-job-ring";
858                                         reg = <0x2000 0x1000>;
859                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
860                                 };
861
862                                 sec_jr2: jr1@3000 {
863                                         compatible = "fsl,sec-v4.0-job-ring";
864                                         reg = <0x3000 0x1000>;
865                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
866                                 };
867                         };
868
869                         flexcan1: can@30a00000 {
870                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
871                                 reg = <0x30a00000 0x10000>;
872                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
873                                 clocks = <&clks IMX7D_CLK_DUMMY>,
874                                         <&clks IMX7D_CAN1_ROOT_CLK>;
875                                 clock-names = "ipg", "per";
876                                 status = "disabled";
877                         };
878
879                         flexcan2: can@30a10000 {
880                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
881                                 reg = <0x30a10000 0x10000>;
882                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
883                                 clocks = <&clks IMX7D_CLK_DUMMY>,
884                                         <&clks IMX7D_CAN2_ROOT_CLK>;
885                                 clock-names = "ipg", "per";
886                                 status = "disabled";
887                         };
888
889                         i2c1: i2c@30a20000 {
890                                 #address-cells = <1>;
891                                 #size-cells = <0>;
892                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
893                                 reg = <0x30a20000 0x10000>;
894                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
895                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
896                                 status = "disabled";
897                         };
898
899                         i2c2: i2c@30a30000 {
900                                 #address-cells = <1>;
901                                 #size-cells = <0>;
902                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
903                                 reg = <0x30a30000 0x10000>;
904                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
905                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
906                                 status = "disabled";
907                         };
908
909                         i2c3: i2c@30a40000 {
910                                 #address-cells = <1>;
911                                 #size-cells = <0>;
912                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
913                                 reg = <0x30a40000 0x10000>;
914                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
915                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
916                                 status = "disabled";
917                         };
918
919                         i2c4: i2c@30a50000 {
920                                 #address-cells = <1>;
921                                 #size-cells = <0>;
922                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
923                                 reg = <0x30a50000 0x10000>;
924                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
925                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
926                                 status = "disabled";
927                         };
928
929                         uart4: serial@30a60000 {
930                                 compatible = "fsl,imx7d-uart",
931                                              "fsl,imx6q-uart";
932                                 reg = <0x30a60000 0x10000>;
933                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
934                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
935                                         <&clks IMX7D_UART4_ROOT_CLK>;
936                                 clock-names = "ipg", "per";
937                                 status = "disabled";
938                         };
939
940                         uart5: serial@30a70000 {
941                                 compatible = "fsl,imx7d-uart",
942                                              "fsl,imx6q-uart";
943                                 reg = <0x30a70000 0x10000>;
944                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
945                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
946                                         <&clks IMX7D_UART5_ROOT_CLK>;
947                                 clock-names = "ipg", "per";
948                                 status = "disabled";
949                         };
950
951                         uart6: serial@30a80000 {
952                                 compatible = "fsl,imx7d-uart",
953                                              "fsl,imx6q-uart";
954                                 reg = <0x30a80000 0x10000>;
955                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
956                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
957                                         <&clks IMX7D_UART6_ROOT_CLK>;
958                                 clock-names = "ipg", "per";
959                                 status = "disabled";
960                         };
961
962                         uart7: serial@30a90000 {
963                                 compatible = "fsl,imx7d-uart",
964                                              "fsl,imx6q-uart";
965                                 reg = <0x30a90000 0x10000>;
966                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
967                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
968                                         <&clks IMX7D_UART7_ROOT_CLK>;
969                                 clock-names = "ipg", "per";
970                                 status = "disabled";
971                         };
972
973                         mu0a: mailbox@30aa0000 {
974                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
975                                 reg = <0x30aa0000 0x10000>;
976                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
977                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
978                                 #mbox-cells = <2>;
979                                 status = "disabled";
980                         };
981
982                         mu0b: mailbox@30ab0000 {
983                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
984                                 reg = <0x30ab0000 0x10000>;
985                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
986                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
987                                 #mbox-cells = <2>;
988                                 fsl,mu-side-b;
989                                 status = "disabled";
990                         };
991
992                         usbotg1: usb@30b10000 {
993                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
994                                 reg = <0x30b10000 0x200>;
995                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
996                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
997                                 fsl,usbphy = <&usbphynop1>;
998                                 fsl,usbmisc = <&usbmisc1 0>;
999                                 phy-clkgate-delay-us = <400>;
1000                                 status = "disabled";
1001                         };
1002
1003                         usbh: usb@30b30000 {
1004                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1005                                 reg = <0x30b30000 0x200>;
1006                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1007                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1008                                 fsl,usbphy = <&usbphynop3>;
1009                                 fsl,usbmisc = <&usbmisc3 0>;
1010                                 phy_type = "hsic";
1011                                 dr_mode = "host";
1012                                 phy-clkgate-delay-us = <400>;
1013                                 status = "disabled";
1014                         };
1015
1016                         usbmisc1: usbmisc@30b10200 {
1017                                 #index-cells = <1>;
1018                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1019                                 reg = <0x30b10200 0x200>;
1020                         };
1021
1022                         usbmisc3: usbmisc@30b30200 {
1023                                 #index-cells = <1>;
1024                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1025                                 reg = <0x30b30200 0x200>;
1026                         };
1027
1028                         usdhc1: usdhc@30b40000 {
1029                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1030                                 reg = <0x30b40000 0x10000>;
1031                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1032                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1033                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1034                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
1035                                 clock-names = "ipg", "ahb", "per";
1036                                 bus-width = <4>;
1037                                 status = "disabled";
1038                         };
1039
1040                         usdhc2: usdhc@30b50000 {
1041                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1042                                 reg = <0x30b50000 0x10000>;
1043                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1044                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1045                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1046                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
1047                                 clock-names = "ipg", "ahb", "per";
1048                                 bus-width = <4>;
1049                                 status = "disabled";
1050                         };
1051
1052                         usdhc3: usdhc@30b60000 {
1053                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1054                                 reg = <0x30b60000 0x10000>;
1055                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1056                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1057                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1058                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
1059                                 clock-names = "ipg", "ahb", "per";
1060                                 bus-width = <4>;
1061                                 status = "disabled";
1062                         };
1063
1064                         sdma: sdma@30bd0000 {
1065                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1066                                 reg = <0x30bd0000 0x10000>;
1067                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1068                                 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1069                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1070                                 clock-names = "ipg", "ahb";
1071                                 #dma-cells = <3>;
1072                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1073                         };
1074
1075                         fec1: ethernet@30be0000 {
1076                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1077                                 reg = <0x30be0000 0x10000>;
1078                                 interrupt-names = "int0", "int1", "int2", "pps";
1079                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1080                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1081                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1082                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1083                                 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1084                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1085                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1086                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1087                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1088                                 clock-names = "ipg", "ahb", "ptp",
1089                                         "enet_clk_ref", "enet_out";
1090                                 fsl,num-tx-queues=<3>;
1091                                 fsl,num-rx-queues=<3>;
1092                                 status = "disabled";
1093                         };
1094                 };
1095
1096                 dma_apbh: dma-apbh@33000000 {
1097                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1098                         reg = <0x33000000 0x2000>;
1099                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1100                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1101                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1102                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1103                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1104                         #dma-cells = <1>;
1105                         dma-channels = <4>;
1106                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1107                 };
1108
1109                 gpmi: gpmi-nand@33002000{
1110                         compatible = "fsl,imx7d-gpmi-nand";
1111                         #address-cells = <1>;
1112                         #size-cells = <1>;
1113                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1114                         reg-names = "gpmi-nand", "bch";
1115                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1116                         interrupt-names = "bch";
1117                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1118                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1119                         clock-names = "gpmi_io", "gpmi_bch_apb";
1120                         dmas = <&dma_apbh 0>;
1121                         dma-names = "rx-tx";
1122                         status = "disabled";
1123                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1124                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1125                 };
1126         };
1127 };