arch/arm/boot/dts/meson8.dtsi

   1 /*
   2  * Copyright 2014 Carlo Caione <carlo@caione.org>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public License
  20  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include <dt-bindings/clock/meson8b-clkc.h>
  47 #include <dt-bindings/gpio/meson8-gpio.h>
  48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include "meson.dtsi"
  51
  52 / {
  53         model = "Amlogic Meson8 SoC";
  54         compatible = "amlogic,meson8";
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@200 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a9";
  63                         next-level-cache = <&L2>;
  64                         reg = <0x200>;
  65                         enable-method = "amlogic,meson8-smp";
  66                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  67                 };
  68
  69                 cpu1: cpu@201 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a9";
  72                         next-level-cache = <&L2>;
  73                         reg = <0x201>;
  74                         enable-method = "amlogic,meson8-smp";
  75                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  76                 };
  77
  78                 cpu2: cpu@202 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a9";
  81                         next-level-cache = <&L2>;
  82                         reg = <0x202>;
  83                         enable-method = "amlogic,meson8-smp";
  84                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  85                 };
  86
  87                 cpu3: cpu@203 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a9";
  90                         next-level-cache = <&L2>;
  91                         reg = <0x203>;
  92                         enable-method = "amlogic,meson8-smp";
  93                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  94                 };
  95         };
  96
  97         pmu {
  98                 compatible = "arm,cortex-a9-pmu";
  99                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 100                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 101                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 102                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 103                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 104         };
 105
 106         reserved-memory {
 107                 #address-cells = <1>;
 108                 #size-cells = <1>;
 109                 ranges;
 110
 111                 /* 2 MiB reserved for Hardware ROM Firmware? */
 112                 hwrom@0 {
 113                         reg = <0x0 0x200000>;
 114                         no-map;
 115                 };
 116
 117                 /*
 118                  * 1 MiB reserved for the "ARM Power Firmware": this is ARM
 119                  * code which is responsible for system suspend. It loads a
 120                  * piece of ARC code ("arc_power" in the vendor u-boot tree)
 121                  * into SRAM, executes that and shuts down the (last) ARM core.
 122                  * The arc_power firmware then checks various wakeup sources
 123                  * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
 124                  * simply the power key) and re-starts the ARM core once it
 125                  * detects a wakeup request.
 126                  */
 127                 power-firmware@4f00000 {
 128                         reg = <0x4f00000 0x100000>;
 129                         no-map;
 130                 };
 131         };
 132
 133         scu@c4300000 {
 134                 compatible = "arm,cortex-a9-scu";
 135                 reg = <0xc4300000 0x100>;
 136         };
 137 }; /* end of / */
 138
 139 &aobus {
 140         pmu: pmu@e0 {
 141                 compatible = "amlogic,meson8-pmu", "syscon";
 142                 reg = <0xe0 0x8>;
 143         };
 144
 145         pinctrl_aobus: pinctrl@84 {
 146                 compatible = "amlogic,meson8-aobus-pinctrl";
 147                 reg = <0x84 0xc>;
 148                 #address-cells = <1>;
 149                 #size-cells = <1>;
 150                 ranges;
 151
 152                 gpio_ao: ao-bank@14 {
 153                         reg = <0x14 0x4>,
 154                               <0x2c 0x4>,
 155                               <0x24 0x8>;
 156                         reg-names = "mux", "pull", "gpio";
 157                         gpio-controller;
 158                         #gpio-cells = <2>;
 159                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 160                 };
 161
 162                 uart_ao_a_pins: uart_ao_a {
 163                         mux {
 164                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 165                                 function = "uart_ao";
 166                                 bias-disable;
 167                         };
 168                 };
 169
 170                 i2c_ao_pins: i2c_mst_ao {
 171                         mux {
 172                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 173                                 function = "i2c_mst_ao";
 174                                 bias-disable;
 175                         };
 176                 };
 177
 178                 ir_recv_pins: remote {
 179                         mux {
 180                                 groups = "remote_input";
 181                                 function = "remote";
 182                                 bias-disable;
 183                         };
 184                 };
 185
 186                 pwm_f_ao_pins: pwm-f-ao {
 187                         mux {
 188                                 groups = "pwm_f_ao";
 189                                 function = "pwm_f_ao";
 190                                 bias-disable;
 191                         };
 192                 };
 193         };
 194 };
 195
 196 &cbus {
 197         clkc: clock-controller@4000 {
 198                 #clock-cells = <1>;
 199                 #reset-cells = <1>;
 200                 compatible = "amlogic,meson8-clkc";
 201                 reg = <0x8000 0x4>, <0x4000 0x400>;
 202         };
 203
 204         reset: reset-controller@4404 {
 205                 compatible = "amlogic,meson8b-reset";
 206                 reg = <0x4404 0x9c>;
 207                 #reset-cells = <1>;
 208         };
 209
 210         analog_top: analog-top@81a8 {
 211                 compatible = "amlogic,meson8-analog-top", "syscon";
 212                 reg = <0x81a8 0x14>;
 213         };
 214
 215         pwm_ef: pwm@86c0 {
 216                 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 217                 reg = <0x86c0 0x10>;
 218                 #pwm-cells = <3>;
 219                 status = "disabled";
 220         };
 221
 222         pinctrl_cbus: pinctrl@9880 {
 223                 compatible = "amlogic,meson8-cbus-pinctrl";
 224                 reg = <0x9880 0x10>;
 225                 #address-cells = <1>;
 226                 #size-cells = <1>;
 227                 ranges;
 228
 229                 gpio: banks@80b0 {
 230                         reg = <0x80b0 0x28>,
 231                               <0x80e8 0x18>,
 232                               <0x8120 0x18>,
 233                               <0x8030 0x30>;
 234                         reg-names = "mux", "pull", "pull-enable", "gpio";
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 238                 };
 239
 240                 sd_a_pins: sd-a {
 241                         mux {
 242                                 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
 243                                         "sd_d3_a", "sd_clk_a", "sd_cmd_a";
 244                                 function = "sd_a";
 245                                 bias-disable;
 246                         };
 247                 };
 248
 249                 sd_b_pins: sd-b {
 250                         mux {
 251                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 252                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 253                                 function = "sd_b";
 254                                 bias-disable;
 255                         };
 256                 };
 257
 258                 sd_c_pins: sd-c {
 259                         mux {
 260                                 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
 261                                         "sd_d3_c", "sd_clk_c", "sd_cmd_c";
 262                                 function = "sd_c";
 263                                 bias-disable;
 264                         };
 265                 };
 266
 267                 spi_nor_pins: nor {
 268                         mux {
 269                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 270                                 function = "nor";
 271                                 bias-disable;
 272                         };
 273                 };
 274
 275                 eth_pins: ethernet {
 276                         mux {
 277                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 278                                          "eth_txd1", "eth_txd0",
 279                                          "eth_rx_clk_in", "eth_rx_dv",
 280                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 281                                          "eth_mdc";
 282                                 function = "ethernet";
 283                                 bias-disable;
 284                         };
 285                 };
 286
 287                 pwm_e_pins: pwm-e {
 288                         mux {
 289                                 groups = "pwm_e";
 290                                 function = "pwm_e";
 291                                 bias-disable;
 292                         };
 293                 };
 294
 295                 uart_a1_pins: uart-a1 {
 296                         mux {
 297                                 groups = "uart_tx_a1",
 298                                        "uart_rx_a1";
 299                                 function = "uart_a";
 300                                 bias-disable;
 301                         };
 302                 };
 303
 304                 uart_a1_cts_rts_pins: uart-a1-cts-rts {
 305                         mux {
 306                                 groups = "uart_cts_a1",
 307                                        "uart_rts_a1";
 308                                 function = "uart_a";
 309                                 bias-disable;
 310                         };
 311                 };
 312         };
 313 };
 314
 315 &ahb_sram {
 316         smp-sram@1ff80 {
 317                 compatible = "amlogic,meson8-smp-sram";
 318                 reg = <0x1ff80 0x8>;
 319         };
 320 };
 321
 322 &efuse {
 323         compatible = "amlogic,meson8-efuse";
 324         clocks = <&clkc CLKID_EFUSE>;
 325         clock-names = "core";
 326 };
 327
 328 &ethmac {
 329         clocks = <&clkc CLKID_ETH>;
 330         clock-names = "stmmaceth";
 331 };
 332
 333 &gpio_intc {
 334         compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
 335         status = "okay";
 336 };
 337
 338 &hwrng {
 339         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
 340         clocks = <&clkc CLKID_RNG0>;
 341         clock-names = "core";
 342 };
 343
 344 &i2c_AO {
 345         clocks = <&clkc CLKID_CLK81>;
 346 };
 347
 348 &i2c_A {
 349         clocks = <&clkc CLKID_CLK81>;
 350 };
 351
 352 &i2c_B {
 353         clocks = <&clkc CLKID_CLK81>;
 354 };
 355
 356 &L2 {
 357         arm,data-latency = <3 3 3>;
 358         arm,tag-latency = <2 2 2>;
 359         arm,filter-ranges = <0x100000 0xc0000000>;
 360         prefetch-data = <1>;
 361         prefetch-instr = <1>;
 362         arm,shared-override;
 363 };
 364
 365 &pwm_ab {
 366         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 367 };
 368
 369 &pwm_cd {
 370         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 371 };
 372
 373 &saradc {
 374         compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
 375         clocks = <&clkc CLKID_XTAL>,
 376                 <&clkc CLKID_SAR_ADC>;
 377         clock-names = "clkin", "core";
 378 };
 379
 380 &sdio {
 381         compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
 382         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 383         clock-names = "core", "clkin";
 384 };
 385
 386 &spifc {
 387         clocks = <&clkc CLKID_CLK81>;
 388 };
 389
 390 &uart_AO {
 391         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 392         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 393         clock-names = "baud", "xtal", "pclk";
 394 };
 395
 396 &uart_A {
 397         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 398         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 399         clock-names = "baud", "xtal", "pclk";
 400 };
 401
 402 &uart_B {
 403         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 404         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 405         clock-names = "baud", "xtal", "pclk";
 406 };
 407
 408 &uart_C {
 409         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 410         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 411         clock-names = "baud", "xtal", "pclk";
 412 };
 413
 414 &usb0 {
 415         compatible = "amlogic,meson8-usb", "snps,dwc2";
 416         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 417         clock-names = "otg";
 418 };
 419
 420 &usb1 {
 421         compatible = "amlogic,meson8-usb", "snps,dwc2";
 422         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 423         clock-names = "otg";
 424 };
 425
 426 &usb0_phy {
 427         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 428         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 429         clock-names = "usb_general", "usb";
 430         resets = <&reset RESET_USB_OTG>;
 431 };
 432
 433 &usb1_phy {
 434         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 435         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 436         clock-names = "usb_general", "usb";
 437         resets = <&reset RESET_USB_OTG>;
 438 };