ARM: dts: meson: add the clock inputs for the Meson timer
[muen/linux.git] / arch / arm / boot / dts / meson8b.dtsi
1 /*
2  * Copyright 2015 Endless Mobile, Inc.
3  * Author: Carlo Caione <carlo@endlessm.com>
4  *
5  * This file is dual-licensed: you can use it either under the terms
6  * of the GPL or the X11 license, at your option. Note that this dual
7  * licensing only applies to this file, and not this project as a
8  * whole.
9  *
10  *  a) This library is free software; you can redistribute it and/or
11  *     modify it under the terms of the GNU General Public License as
12  *     published by the Free Software Foundation; either version 2 of the
13  *     License, or (at your option) any later version.
14  *
15  *     This library is distributed in the hope that it will be useful,
16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *     GNU General Public License for more details.
19  *
20  *     You should have received a copy of the GNU General Public License
21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
22  *
23  * Or, alternatively,
24  *
25  *  b) Permission is hereby granted, free of charge, to any person
26  *     obtaining a copy of this software and associated documentation
27  *     files (the "Software"), to deal in the Software without
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29  *     copy, modify, merge, publish, distribute, sublicense, and/or
30  *     sell copies of the Software, and to permit persons to whom the
31  *     Software is furnished to do so, subject to the following
32  *     conditions:
33  *
34  *     The above copyright notice and this permission notice shall be
35  *     included in all copies or substantial portions of the Software.
36  *
37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44  *     OTHER DEALINGS IN THE SOFTWARE.
45  */
46
47 #include <dt-bindings/clock/meson8b-clkc.h>
48 #include <dt-bindings/gpio/meson8b-gpio.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
51 #include "meson.dtsi"
52
53 / {
54         cpus {
55                 #address-cells = <1>;
56                 #size-cells = <0>;
57
58                 cpu0: cpu@200 {
59                         device_type = "cpu";
60                         compatible = "arm,cortex-a5";
61                         next-level-cache = <&L2>;
62                         reg = <0x200>;
63                         enable-method = "amlogic,meson8b-smp";
64                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
65                 };
66
67                 cpu1: cpu@201 {
68                         device_type = "cpu";
69                         compatible = "arm,cortex-a5";
70                         next-level-cache = <&L2>;
71                         reg = <0x201>;
72                         enable-method = "amlogic,meson8b-smp";
73                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
74                 };
75
76                 cpu2: cpu@202 {
77                         device_type = "cpu";
78                         compatible = "arm,cortex-a5";
79                         next-level-cache = <&L2>;
80                         reg = <0x202>;
81                         enable-method = "amlogic,meson8b-smp";
82                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
83                 };
84
85                 cpu3: cpu@203 {
86                         device_type = "cpu";
87                         compatible = "arm,cortex-a5";
88                         next-level-cache = <&L2>;
89                         reg = <0x203>;
90                         enable-method = "amlogic,meson8b-smp";
91                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
92                 };
93         };
94
95         pmu {
96                 compatible = "arm,cortex-a5-pmu";
97                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
98                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
99                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
100                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
101                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
102         };
103
104         reserved-memory {
105                 #address-cells = <1>;
106                 #size-cells = <1>;
107                 ranges;
108
109                 /* 2 MiB reserved for Hardware ROM Firmware? */
110                 hwrom@0 {
111                         reg = <0x0 0x200000>;
112                         no-map;
113                 };
114         };
115
116         scu@c4300000 {
117                 compatible = "arm,cortex-a5-scu";
118                 reg = <0xc4300000 0x100>;
119         };
120 }; /* end of / */
121
122 &aobus {
123         pmu: pmu@e0 {
124                 compatible = "amlogic,meson8b-pmu", "syscon";
125                 reg = <0xe0 0x18>;
126         };
127
128         pinctrl_aobus: pinctrl@84 {
129                 compatible = "amlogic,meson8b-aobus-pinctrl";
130                 reg = <0x84 0xc>;
131                 #address-cells = <1>;
132                 #size-cells = <1>;
133                 ranges;
134
135                 gpio_ao: ao-bank@14 {
136                         reg = <0x14 0x4>,
137                                 <0x2c 0x4>,
138                                 <0x24 0x8>;
139                         reg-names = "mux", "pull", "gpio";
140                         gpio-controller;
141                         #gpio-cells = <2>;
142                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
143                 };
144
145                 uart_ao_a_pins: uart_ao_a {
146                         mux {
147                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
148                                 function = "uart_ao";
149                                 bias-disable;
150                         };
151                 };
152
153                 ir_recv_pins: remote {
154                         mux {
155                                 groups = "remote_input";
156                                 function = "remote";
157                                 bias-disable;
158                         };
159                 };
160         };
161 };
162
163 &cbus {
164         clkc: clock-controller@4000 {
165                 #clock-cells = <1>;
166                 #reset-cells = <1>;
167                 compatible = "amlogic,meson8b-clkc";
168                 reg = <0x8000 0x4>, <0x4000 0x400>;
169         };
170
171         reset: reset-controller@4404 {
172                 compatible = "amlogic,meson8b-reset";
173                 reg = <0x4404 0x9c>;
174                 #reset-cells = <1>;
175         };
176
177         analog_top: analog-top@81a8 {
178                 compatible = "amlogic,meson8b-analog-top", "syscon";
179                 reg = <0x81a8 0x14>;
180         };
181
182         pwm_ef: pwm@86c0 {
183                 compatible = "amlogic,meson8b-pwm";
184                 reg = <0x86c0 0x10>;
185                 #pwm-cells = <3>;
186                 status = "disabled";
187         };
188
189         pinctrl_cbus: pinctrl@9880 {
190                 compatible = "amlogic,meson8b-cbus-pinctrl";
191                 reg = <0x9880 0x10>;
192                 #address-cells = <1>;
193                 #size-cells = <1>;
194                 ranges;
195
196                 gpio: banks@80b0 {
197                         reg = <0x80b0 0x28>,
198                                 <0x80e8 0x18>,
199                                 <0x8120 0x18>,
200                                 <0x8030 0x38>;
201                         reg-names = "mux", "pull", "pull-enable", "gpio";
202                         gpio-controller;
203                         #gpio-cells = <2>;
204                         gpio-ranges = <&pinctrl_cbus 0 0 83>;
205                 };
206
207                 eth_rgmii_pins: eth-rgmii {
208                         mux {
209                                 groups = "eth_tx_clk",
210                                          "eth_tx_en",
211                                          "eth_txd1_0",
212                                          "eth_txd1_1",
213                                          "eth_txd0_0",
214                                          "eth_txd0_1",
215                                          "eth_rx_clk",
216                                          "eth_rx_dv",
217                                          "eth_rxd1",
218                                          "eth_rxd0",
219                                          "eth_mdio_en",
220                                          "eth_mdc",
221                                          "eth_ref_clk",
222                                          "eth_txd2",
223                                          "eth_txd3";
224                                 function = "ethernet";
225                                 bias-disable;
226                         };
227                 };
228
229                 eth_rmii_pins: eth-rmii {
230                         mux {
231                                 groups = "eth_tx_en",
232                                          "eth_txd1_0",
233                                          "eth_txd0_0",
234                                          "eth_rx_clk",
235                                          "eth_rx_dv",
236                                          "eth_rxd1",
237                                          "eth_rxd0",
238                                          "eth_mdio_en",
239                                          "eth_mdc";
240                                 function = "ethernet";
241                                 bias-disable;
242                         };
243                 };
244
245                 i2c_a_pins: i2c-a {
246                         mux {
247                                 groups = "i2c_sda_a", "i2c_sck_a";
248                                 function = "i2c_a";
249                                 bias-disable;
250                         };
251                 };
252
253                 sd_b_pins: sd-b {
254                         mux {
255                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
256                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
257                                 function = "sd_b";
258                                 bias-disable;
259                         };
260                 };
261
262                 pwm_c1_pins: pwm-c1 {
263                         mux {
264                                 groups = "pwm_c1";
265                                 function = "pwm_c";
266                                 bias-disable;
267                         };
268                 };
269
270                 uart_b0_pins: uart-b0 {
271                         mux {
272                                 groups = "uart_tx_b0",
273                                        "uart_rx_b0";
274                                 function = "uart_b";
275                                 bias-disable;
276                         };
277                 };
278
279                 uart_b0_cts_rts_pins: uart-b0-cts-rts {
280                         mux {
281                                 groups = "uart_cts_b0",
282                                        "uart_rts_b0";
283                                 function = "uart_b";
284                                 bias-disable;
285                         };
286                 };
287         };
288 };
289
290 &ahb_sram {
291         smp-sram@1ff80 {
292                 compatible = "amlogic,meson8b-smp-sram";
293                 reg = <0x1ff80 0x8>;
294         };
295 };
296
297
298 &efuse {
299         compatible = "amlogic,meson8b-efuse";
300         clocks = <&clkc CLKID_EFUSE>;
301         clock-names = "core";
302 };
303
304 &ethmac {
305         compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
306
307         reg = <0xc9410000 0x10000
308                0xc1108140 0x4>;
309
310         clocks = <&clkc CLKID_ETH>,
311                  <&clkc CLKID_MPLL2>,
312                  <&clkc CLKID_MPLL2>;
313         clock-names = "stmmaceth", "clkin0", "clkin1";
314
315         resets = <&reset RESET_ETHERNET>;
316         reset-names = "stmmaceth";
317 };
318
319 &gpio_intc {
320         compatible = "amlogic,meson-gpio-intc",
321                      "amlogic,meson8b-gpio-intc";
322         status = "okay";
323 };
324
325 &hwrng {
326         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
327         clocks = <&clkc CLKID_RNG0>;
328         clock-names = "core";
329 };
330
331 &i2c_AO {
332         clocks = <&clkc CLKID_CLK81>;
333 };
334
335 &i2c_A {
336         clocks = <&clkc CLKID_I2C>;
337 };
338
339 &i2c_B {
340         clocks = <&clkc CLKID_I2C>;
341 };
342
343 &L2 {
344         arm,data-latency = <3 3 3>;
345         arm,tag-latency = <2 2 2>;
346         arm,filter-ranges = <0x100000 0xc0000000>;
347         prefetch-data = <1>;
348         prefetch-instr = <1>;
349         arm,shared-override;
350 };
351
352 &pwm_ab {
353         compatible = "amlogic,meson8b-pwm";
354 };
355
356 &pwm_cd {
357         compatible = "amlogic,meson8b-pwm";
358 };
359
360 &saradc {
361         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
362         clocks = <&clkc CLKID_XTAL>,
363                 <&clkc CLKID_SAR_ADC>;
364         clock-names = "clkin", "core";
365 };
366
367 &sdio {
368         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
369         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
370         clock-names = "core", "clkin";
371 };
372
373 &timer_abcde {
374         clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
375         clock-names = "xtal", "pclk";
376 };
377
378 &uart_AO {
379         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
380         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
381         clock-names = "baud", "xtal", "pclk";
382 };
383
384 &uart_A {
385         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
386         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
387         clock-names = "baud", "xtal", "pclk";
388 };
389
390 &uart_B {
391         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
392         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
393         clock-names = "baud", "xtal", "pclk";
394 };
395
396 &uart_C {
397         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
398         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
399         clock-names = "baud", "xtal", "pclk";
400 };
401
402 &usb0 {
403         compatible = "amlogic,meson8b-usb", "snps,dwc2";
404         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
405         clock-names = "otg";
406 };
407
408 &usb1 {
409         compatible = "amlogic,meson8b-usb", "snps,dwc2";
410         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
411         clock-names = "otg";
412 };
413
414 &usb0_phy {
415         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
416         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
417         clock-names = "usb_general", "usb";
418         resets = <&reset RESET_USB_OTG>;
419 };
420
421 &usb1_phy {
422         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
423         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
424         clock-names = "usb_general", "usb";
425         resets = <&reset RESET_USB_OTG>;
426 };
427
428 &wdt {
429         compatible = "amlogic,meson8b-wdt";
430 };