ARM: dts: mmp2: fix TWSI2
[muen/linux.git] / arch / arm / boot / dts / mmp2.dtsi
1 /*
2  *  Copyright (C) 2012 Marvell Technology Group Ltd.
3  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4  *
5  *  This program is free software; you can redistribute it and/or modify
6  *  it under the terms of the GNU General Public License version 2 as
7  *  publishhed by the Free Software Foundation.
8  */
9
10 #include "skeleton.dtsi"
11 #include <dt-bindings/clock/marvell,mmp2.h>
12
13 / {
14         aliases {
15                 serial0 = &uart1;
16                 serial1 = &uart2;
17                 serial2 = &uart3;
18                 serial3 = &uart4;
19                 i2c0 = &twsi1;
20                 i2c1 = &twsi2;
21         };
22
23         soc {
24                 #address-cells = <1>;
25                 #size-cells = <1>;
26                 compatible = "simple-bus";
27                 interrupt-parent = <&intc>;
28                 ranges;
29
30                 L2: l2-cache {
31                         compatible = "marvell,tauros2-cache";
32                         marvell,tauros2-cache-features = <0x3>;
33                 };
34
35                 axi@d4200000 {  /* AXI */
36                         compatible = "mrvl,axi-bus", "simple-bus";
37                         #address-cells = <1>;
38                         #size-cells = <1>;
39                         reg = <0xd4200000 0x00200000>;
40                         ranges;
41
42                         intc: interrupt-controller@d4282000 {
43                                 compatible = "mrvl,mmp2-intc";
44                                 interrupt-controller;
45                                 #interrupt-cells = <1>;
46                                 reg = <0xd4282000 0x1000>;
47                                 mrvl,intc-nr-irqs = <64>;
48                         };
49
50                         intcmux4: interrupt-controller@d4282150 {
51                                 compatible = "mrvl,mmp2-mux-intc";
52                                 interrupts = <4>;
53                                 interrupt-controller;
54                                 #interrupt-cells = <1>;
55                                 reg = <0x150 0x4>, <0x168 0x4>;
56                                 reg-names = "mux status", "mux mask";
57                                 mrvl,intc-nr-irqs = <2>;
58                         };
59
60                         intcmux5: interrupt-controller@d4282154 {
61                                 compatible = "mrvl,mmp2-mux-intc";
62                                 interrupts = <5>;
63                                 interrupt-controller;
64                                 #interrupt-cells = <1>;
65                                 reg = <0x154 0x4>, <0x16c 0x4>;
66                                 reg-names = "mux status", "mux mask";
67                                 mrvl,intc-nr-irqs = <2>;
68                                 mrvl,clr-mfp-irq = <1>;
69                         };
70
71                         intcmux9: interrupt-controller@d4282180 {
72                                 compatible = "mrvl,mmp2-mux-intc";
73                                 interrupts = <9>;
74                                 interrupt-controller;
75                                 #interrupt-cells = <1>;
76                                 reg = <0x180 0x4>, <0x17c 0x4>;
77                                 reg-names = "mux status", "mux mask";
78                                 mrvl,intc-nr-irqs = <3>;
79                         };
80
81                         intcmux17: interrupt-controller@d4282158 {
82                                 compatible = "mrvl,mmp2-mux-intc";
83                                 interrupts = <17>;
84                                 interrupt-controller;
85                                 #interrupt-cells = <1>;
86                                 reg = <0x158 0x4>, <0x170 0x4>;
87                                 reg-names = "mux status", "mux mask";
88                                 mrvl,intc-nr-irqs = <5>;
89                         };
90
91                         intcmux35: interrupt-controller@d428215c {
92                                 compatible = "mrvl,mmp2-mux-intc";
93                                 interrupts = <35>;
94                                 interrupt-controller;
95                                 #interrupt-cells = <1>;
96                                 reg = <0x15c 0x4>, <0x174 0x4>;
97                                 reg-names = "mux status", "mux mask";
98                                 mrvl,intc-nr-irqs = <15>;
99                         };
100
101                         intcmux51: interrupt-controller@d4282160 {
102                                 compatible = "mrvl,mmp2-mux-intc";
103                                 interrupts = <51>;
104                                 interrupt-controller;
105                                 #interrupt-cells = <1>;
106                                 reg = <0x160 0x4>, <0x178 0x4>;
107                                 reg-names = "mux status", "mux mask";
108                                 mrvl,intc-nr-irqs = <2>;
109                         };
110
111                         intcmux55: interrupt-controller@d4282188 {
112                                 compatible = "mrvl,mmp2-mux-intc";
113                                 interrupts = <55>;
114                                 interrupt-controller;
115                                 #interrupt-cells = <1>;
116                                 reg = <0x188 0x4>, <0x184 0x4>;
117                                 reg-names = "mux status", "mux mask";
118                                 mrvl,intc-nr-irqs = <2>;
119                         };
120
121                         mmc1: mmc@d4280000 {
122                                 compatible = "mrvl,pxav3-mmc";
123                                 reg = <0xd4280000 0x120>;
124                                 clocks = <&soc_clocks MMP2_CLK_SDH0>;
125                                 clock-names = "io";
126                                 interrupts = <39>;
127                                 status = "disabled";
128                         };
129
130                         mmc2: mmc@d4280800 {
131                                 compatible = "mrvl,pxav3-mmc";
132                                 reg = <0xd4280800 0x120>;
133                                 clocks = <&soc_clocks MMP2_CLK_SDH1>;
134                                 clock-names = "io";
135                                 interrupts = <52>;
136                                 status = "disabled";
137                         };
138
139                         mmc3: mmc@d4281000 {
140                                 compatible = "mrvl,pxav3-mmc";
141                                 reg = <0xd4281000 0x120>;
142                                 clocks = <&soc_clocks MMP2_CLK_SDH2>;
143                                 clock-names = "io";
144                                 interrupts = <53>;
145                                 status = "disabled";
146                         };
147
148                         mmc4: mmc@d4281800 {
149                                 compatible = "mrvl,pxav3-mmc";
150                                 reg = <0xd4281800 0x120>;
151                                 clocks = <&soc_clocks MMP2_CLK_SDH3>;
152                                 clock-names = "io";
153                                 interrupts = <54>;
154                                 status = "disabled";
155                         };
156                 };
157
158                 apb@d4000000 {  /* APB */
159                         compatible = "mrvl,apb-bus", "simple-bus";
160                         #address-cells = <1>;
161                         #size-cells = <1>;
162                         reg = <0xd4000000 0x00200000>;
163                         ranges;
164
165                         timer0: timer@d4014000 {
166                                 compatible = "mrvl,mmp-timer";
167                                 reg = <0xd4014000 0x100>;
168                                 interrupts = <13>;
169                                 clocks = <&soc_clocks MMP2_CLK_TIMER>;
170                         };
171
172                         uart1: uart@d4030000 {
173                                 compatible = "mrvl,mmp-uart";
174                                 reg = <0xd4030000 0x1000>;
175                                 interrupts = <27>;
176                                 clocks = <&soc_clocks MMP2_CLK_UART0>;
177                                 resets = <&soc_clocks MMP2_CLK_UART0>;
178                                 status = "disabled";
179                         };
180
181                         uart2: uart@d4017000 {
182                                 compatible = "mrvl,mmp-uart";
183                                 reg = <0xd4017000 0x1000>;
184                                 interrupts = <28>;
185                                 clocks = <&soc_clocks MMP2_CLK_UART1>;
186                                 resets = <&soc_clocks MMP2_CLK_UART1>;
187                                 status = "disabled";
188                         };
189
190                         uart3: uart@d4018000 {
191                                 compatible = "mrvl,mmp-uart";
192                                 reg = <0xd4018000 0x1000>;
193                                 interrupts = <24>;
194                                 clocks = <&soc_clocks MMP2_CLK_UART2>;
195                                 resets = <&soc_clocks MMP2_CLK_UART2>;
196                                 status = "disabled";
197                         };
198
199                         uart4: uart@d4016000 {
200                                 compatible = "mrvl,mmp-uart";
201                                 reg = <0xd4016000 0x1000>;
202                                 interrupts = <46>;
203                                 clocks = <&soc_clocks MMP2_CLK_UART3>;
204                                 resets = <&soc_clocks MMP2_CLK_UART3>;
205                                 status = "disabled";
206                         };
207
208                         gpio: gpio@d4019000 {
209                                 compatible = "marvell,mmp2-gpio";
210                                 #address-cells = <1>;
211                                 #size-cells = <1>;
212                                 reg = <0xd4019000 0x1000>;
213                                 gpio-controller;
214                                 #gpio-cells = <2>;
215                                 interrupts = <49>;
216                                 interrupt-names = "gpio_mux";
217                                 clocks = <&soc_clocks MMP2_CLK_GPIO>;
218                                 resets = <&soc_clocks MMP2_CLK_GPIO>;
219                                 interrupt-controller;
220                                 #interrupt-cells = <2>;
221                                 ranges;
222
223                                 gcb0: gpio@d4019000 {
224                                         reg = <0xd4019000 0x4>;
225                                 };
226
227                                 gcb1: gpio@d4019004 {
228                                         reg = <0xd4019004 0x4>;
229                                 };
230
231                                 gcb2: gpio@d4019008 {
232                                         reg = <0xd4019008 0x4>;
233                                 };
234
235                                 gcb3: gpio@d4019100 {
236                                         reg = <0xd4019100 0x4>;
237                                 };
238
239                                 gcb4: gpio@d4019104 {
240                                         reg = <0xd4019104 0x4>;
241                                 };
242
243                                 gcb5: gpio@d4019108 {
244                                         reg = <0xd4019108 0x4>;
245                                 };
246                         };
247
248                         twsi1: i2c@d4011000 {
249                                 compatible = "mrvl,mmp-twsi";
250                                 reg = <0xd4011000 0x1000>;
251                                 interrupts = <7>;
252                                 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
253                                 resets = <&soc_clocks MMP2_CLK_TWSI0>;
254                                 #address-cells = <1>;
255                                 #size-cells = <0>;
256                                 mrvl,i2c-fast-mode;
257                                 status = "disabled";
258                         };
259
260                         twsi2: i2c@d4031000 {
261                                 compatible = "mrvl,mmp-twsi";
262                                 reg = <0xd4031000 0x1000>;
263                                 interrupt-parent = <&intcmux17>;
264                                 interrupts = <0>;
265                                 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
266                                 resets = <&soc_clocks MMP2_CLK_TWSI1>;
267                                 #address-cells = <1>;
268                                 #size-cells = <0>;
269                                 status = "disabled";
270                         };
271
272                         rtc: rtc@d4010000 {
273                                 compatible = "mrvl,mmp-rtc";
274                                 reg = <0xd4010000 0x1000>;
275                                 interrupts = <1 0>;
276                                 interrupt-names = "rtc 1Hz", "rtc alarm";
277                                 interrupt-parent = <&intcmux5>;
278                                 clocks = <&soc_clocks MMP2_CLK_RTC>;
279                                 resets = <&soc_clocks MMP2_CLK_RTC>;
280                                 status = "disabled";
281                         };
282                 };
283
284                 soc_clocks: clocks{
285                         compatible = "marvell,mmp2-clock";
286                         reg = <0xd4050000 0x1000>,
287                               <0xd4282800 0x400>,
288                               <0xd4015000 0x1000>;
289                         reg-names = "mpmu", "apmu", "apbc";
290                         #clock-cells = <1>;
291                         #reset-cells = <1>;
292                 };
293         };
294 };