15547b1389772f60bb08c4257be9827ea005c4f3
[muen/linux.git] / arch / arm / boot / dts / rda8810pl.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * RDA8810PL SoC
4  *
5  * Copyright (c) 2017 Andreas Färber
6  * Copyright (c) 2018 Manivannan Sadhasivam
7  */
8
9 / {
10         compatible = "rda,8810pl";
11         interrupt-parent = <&intc>;
12         #address-cells = <1>;
13         #size-cells = <1>;
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a5";
22                         reg = <0x0>;
23                 };
24         };
25
26         sram@100000 {
27                 compatible = "mmio-sram";
28                 reg = <0x100000 0x10000>;
29                 #address-cells = <1>;
30                 #size-cells = <1>;
31                 ranges;
32         };
33
34         apb@20800000 {
35                 compatible = "simple-bus";
36                 #address-cells = <1>;
37                 #size-cells = <1>;
38                 ranges = <0x0 0x20800000 0x100000>;
39
40                 intc: interrupt-controller@0 {
41                         compatible = "rda,8810pl-intc";
42                         reg = <0x0 0x1000>;
43                         interrupt-controller;
44                         #interrupt-cells = <2>;
45                 };
46         };
47
48         apb@20900000 {
49                 compatible = "simple-bus";
50                 #address-cells = <1>;
51                 #size-cells = <1>;
52                 ranges = <0x0 0x20900000 0x100000>;
53         };
54
55         apb@20a00000 {
56                 compatible = "simple-bus";
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 ranges = <0x0 0x20a00000 0x100000>;
60
61                 uart1: serial@0 {
62                         compatible = "rda,8810pl-uart";
63                         reg = <0x0 0x1000>;
64                         status = "disabled";
65                 };
66
67                 uart2: serial@10000 {
68                         compatible = "rda,8810pl-uart";
69                         reg = <0x10000 0x1000>;
70                         status = "disabled";
71                 };
72
73                 uart3: serial@90000 {
74                         compatible = "rda,8810pl-uart";
75                         reg = <0x90000 0x1000>;
76                         status = "disabled";
77                 };
78         };
79
80         l2: cache-controller@21100000 {
81                 compatible = "arm,pl310-cache";
82                 reg = <0x21100000 0x1000>;
83                 cache-unified;
84                 cache-level = <2>;
85         };
86 };