arch/arm/boot/dts/rk3066a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3066a-cru.h>
  10 #include <dt-bindings/power/rk3066-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3066a";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1416000 1300000
  29                                 1200000 1175000
  30                                 1008000 1125000
  31                                 816000  1125000
  32                                 600000  1100000
  33                                 504000  1100000
  34                                 312000  1075000
  35                         >;
  36                         clock-latency = <40000>;
  37                         clocks = <&cru ARMCLK>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x1>;
  44                 };
  45         };
  46
  47         sram: sram@10080000 {
  48                 compatible = "mmio-sram";
  49                 reg = <0x10080000 0x10000>;
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges = <0 0x10080000 0x10000>;
  53
  54                 smp-sram@0 {
  55                         compatible = "rockchip,rk3066-smp-sram";
  56                         reg = <0x0 0x50>;
  57                 };
  58         };
  59
  60         i2s0: i2s@10118000 {
  61                 compatible = "rockchip,rk3066-i2s";
  62                 reg = <0x10118000 0x2000>;
  63                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 pinctrl-names = "default";
  67                 pinctrl-0 = <&i2s0_bus>;
  68                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
  69                 dma-names = "tx", "rx";
  70                 clock-names = "i2s_hclk", "i2s_clk";
  71                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
  72                 rockchip,playback-channels = <8>;
  73                 rockchip,capture-channels = <2>;
  74                 status = "disabled";
  75         };
  76
  77         i2s1: i2s@1011a000 {
  78                 compatible = "rockchip,rk3066-i2s";
  79                 reg = <0x1011a000 0x2000>;
  80                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&i2s1_bus>;
  85                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
  86                 dma-names = "tx", "rx";
  87                 clock-names = "i2s_hclk", "i2s_clk";
  88                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
  89                 rockchip,playback-channels = <2>;
  90                 rockchip,capture-channels = <2>;
  91                 status = "disabled";
  92         };
  93
  94         i2s2: i2s@1011c000 {
  95                 compatible = "rockchip,rk3066-i2s";
  96                 reg = <0x1011c000 0x2000>;
  97                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&i2s2_bus>;
 102                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 103                 dma-names = "tx", "rx";
 104                 clock-names = "i2s_hclk", "i2s_clk";
 105                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 106                 rockchip,playback-channels = <2>;
 107                 rockchip,capture-channels = <2>;
 108                 status = "disabled";
 109         };
 110
 111         cru: clock-controller@20000000 {
 112                 compatible = "rockchip,rk3066a-cru";
 113                 reg = <0x20000000 0x1000>;
 114                 rockchip,grf = <&grf>;
 115
 116                 #clock-cells = <1>;
 117                 #reset-cells = <1>;
 118                 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 119                                   <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 120                                   <&cru PCLK_CPU>, <&cru ACLK_PERI>,
 121                                   <&cru HCLK_PERI>, <&cru PCLK_PERI>;
 122                 assigned-clock-rates = <400000000>, <594000000>,
 123                                        <300000000>, <150000000>,
 124                                        <75000000>, <300000000>,
 125                                        <150000000>, <75000000>;
 126         };
 127
 128         timer@2000e000 {
 129                 compatible = "snps,dw-apb-timer-osc";
 130                 reg = <0x2000e000 0x100>;
 131                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 133                 clock-names = "timer", "pclk";
 134         };
 135
 136         efuse: efuse@20010000 {
 137                 compatible = "rockchip,rk3066a-efuse";
 138                 reg = <0x20010000 0x4000>;
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 clocks = <&cru PCLK_EFUSE>;
 142                 clock-names = "pclk_efuse";
 143
 144                 cpu_leakage: cpu_leakage@17 {
 145                         reg = <0x17 0x1>;
 146                 };
 147         };
 148
 149         timer@20038000 {
 150                 compatible = "snps,dw-apb-timer-osc";
 151                 reg = <0x20038000 0x100>;
 152                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 153                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 154                 clock-names = "timer", "pclk";
 155         };
 156
 157         timer@2003a000 {
 158                 compatible = "snps,dw-apb-timer-osc";
 159                 reg = <0x2003a000 0x100>;
 160                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 161                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 162                 clock-names = "timer", "pclk";
 163         };
 164
 165         tsadc: tsadc@20060000 {
 166                 compatible = "rockchip,rk3066-tsadc";
 167                 reg = <0x20060000 0x100>;
 168                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 169                 clock-names = "saradc", "apb_pclk";
 170                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 171                 #io-channel-cells = <1>;
 172                 resets = <&cru SRST_TSADC>;
 173                 reset-names = "saradc-apb";
 174                 status = "disabled";
 175         };
 176
 177         usbphy: phy {
 178                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 179                 rockchip,grf = <&grf>;
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 status = "disabled";
 183
 184                 usbphy0: usb-phy@17c {
 185                         #phy-cells = <0>;
 186                         reg = <0x17c>;
 187                         clocks = <&cru SCLK_OTGPHY0>;
 188                         clock-names = "phyclk";
 189                         #clock-cells = <0>;
 190                 };
 191
 192                 usbphy1: usb-phy@188 {
 193                         #phy-cells = <0>;
 194                         reg = <0x188>;
 195                         clocks = <&cru SCLK_OTGPHY1>;
 196                         clock-names = "phyclk";
 197                         #clock-cells = <0>;
 198                 };
 199         };
 200
 201         pinctrl: pinctrl {
 202                 compatible = "rockchip,rk3066a-pinctrl";
 203                 rockchip,grf = <&grf>;
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 gpio0: gpio0@20034000 {
 209                         compatible = "rockchip,gpio-bank";
 210                         reg = <0x20034000 0x100>;
 211                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&cru PCLK_GPIO0>;
 213
 214                         gpio-controller;
 215                         #gpio-cells = <2>;
 216
 217                         interrupt-controller;
 218                         #interrupt-cells = <2>;
 219                 };
 220
 221                 gpio1: gpio1@2003c000 {
 222                         compatible = "rockchip,gpio-bank";
 223                         reg = <0x2003c000 0x100>;
 224                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&cru PCLK_GPIO1>;
 226
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229
 230                         interrupt-controller;
 231                         #interrupt-cells = <2>;
 232                 };
 233
 234                 gpio2: gpio2@2003e000 {
 235                         compatible = "rockchip,gpio-bank";
 236                         reg = <0x2003e000 0x100>;
 237                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&cru PCLK_GPIO2>;
 239
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242
 243                         interrupt-controller;
 244                         #interrupt-cells = <2>;
 245                 };
 246
 247                 gpio3: gpio3@20080000 {
 248                         compatible = "rockchip,gpio-bank";
 249                         reg = <0x20080000 0x100>;
 250                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&cru PCLK_GPIO3>;
 252
 253                         gpio-controller;
 254                         #gpio-cells = <2>;
 255
 256                         interrupt-controller;
 257                         #interrupt-cells = <2>;
 258                 };
 259
 260                 gpio4: gpio4@20084000 {
 261                         compatible = "rockchip,gpio-bank";
 262                         reg = <0x20084000 0x100>;
 263                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&cru PCLK_GPIO4>;
 265
 266                         gpio-controller;
 267                         #gpio-cells = <2>;
 268
 269                         interrupt-controller;
 270                         #interrupt-cells = <2>;
 271                 };
 272
 273                 gpio6: gpio6@2000a000 {
 274                         compatible = "rockchip,gpio-bank";
 275                         reg = <0x2000a000 0x100>;
 276                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 277                         clocks = <&cru PCLK_GPIO6>;
 278
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                 };
 285
 286                 pcfg_pull_default: pcfg_pull_default {
 287                         bias-pull-pin-default;
 288                 };
 289
 290                 pcfg_pull_none: pcfg_pull_none {
 291                         bias-disable;
 292                 };
 293
 294                 emac {
 295                         emac_xfer: emac-xfer {
 296                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 297                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 298                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 299                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 300                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 301                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 302                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 303                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 304                         };
 305
 306                         emac_mdio: emac-mdio {
 307                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 308                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 309                         };
 310                 };
 311
 312                 emmc {
 313                         emmc_clk: emmc-clk {
 314                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 315                         };
 316
 317                         emmc_cmd: emmc-cmd {
 318                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 319                         };
 320
 321                         emmc_rst: emmc-rst {
 322                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 323                         };
 324
 325                         /*
 326                          * The data pins are shared between nandc and emmc and
 327                          * not accessible through pinctrl. Also they should've
 328                          * been already set correctly by firmware, as
 329                          * flash/emmc is the boot-device.
 330                          */
 331                 };
 332
 333                 i2c0 {
 334                         i2c0_xfer: i2c0-xfer {
 335                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 336                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 337                         };
 338                 };
 339
 340                 i2c1 {
 341                         i2c1_xfer: i2c1-xfer {
 342                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 343                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 344                         };
 345                 };
 346
 347                 i2c2 {
 348                         i2c2_xfer: i2c2-xfer {
 349                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 350                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 351                         };
 352                 };
 353
 354                 i2c3 {
 355                         i2c3_xfer: i2c3-xfer {
 356                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 357                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 358                         };
 359                 };
 360
 361                 i2c4 {
 362                         i2c4_xfer: i2c4-xfer {
 363                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 364                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 365                         };
 366                 };
 367
 368                 pwm0 {
 369                         pwm0_out: pwm0-out {
 370                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 371                         };
 372                 };
 373
 374                 pwm1 {
 375                         pwm1_out: pwm1-out {
 376                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 377                         };
 378                 };
 379
 380                 pwm2 {
 381                         pwm2_out: pwm2-out {
 382                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 383                         };
 384                 };
 385
 386                 pwm3 {
 387                         pwm3_out: pwm3-out {
 388                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 389                         };
 390                 };
 391
 392                 spi0 {
 393                         spi0_clk: spi0-clk {
 394                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 395                         };
 396                         spi0_cs0: spi0-cs0 {
 397                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 398                         };
 399                         spi0_tx: spi0-tx {
 400                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 401                         };
 402                         spi0_rx: spi0-rx {
 403                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 404                         };
 405                         spi0_cs1: spi0-cs1 {
 406                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 407                         };
 408                 };
 409
 410                 spi1 {
 411                         spi1_clk: spi1-clk {
 412                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 413                         };
 414                         spi1_cs0: spi1-cs0 {
 415                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 416                         };
 417                         spi1_rx: spi1-rx {
 418                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 419                         };
 420                         spi1_tx: spi1-tx {
 421                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 422                         };
 423                         spi1_cs1: spi1-cs1 {
 424                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 425                         };
 426                 };
 427
 428                 uart0 {
 429                         uart0_xfer: uart0-xfer {
 430                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 431                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 432                         };
 433
 434                         uart0_cts: uart0-cts {
 435                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 436                         };
 437
 438                         uart0_rts: uart0-rts {
 439                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 440                         };
 441                 };
 442
 443                 uart1 {
 444                         uart1_xfer: uart1-xfer {
 445                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 446                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 447                         };
 448
 449                         uart1_cts: uart1-cts {
 450                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 451                         };
 452
 453                         uart1_rts: uart1-rts {
 454                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 455                         };
 456                 };
 457
 458                 uart2 {
 459                         uart2_xfer: uart2-xfer {
 460                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 461                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 462                         };
 463                         /* no rts / cts for uart2 */
 464                 };
 465
 466                 uart3 {
 467                         uart3_xfer: uart3-xfer {
 468                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 469                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 470                         };
 471
 472                         uart3_cts: uart3-cts {
 473                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 474                         };
 475
 476                         uart3_rts: uart3-rts {
 477                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 478                         };
 479                 };
 480
 481                 sd0 {
 482                         sd0_clk: sd0-clk {
 483                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 484                         };
 485
 486                         sd0_cmd: sd0-cmd {
 487                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 488                         };
 489
 490                         sd0_cd: sd0-cd {
 491                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 492                         };
 493
 494                         sd0_wp: sd0-wp {
 495                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 496                         };
 497
 498                         sd0_bus1: sd0-bus-width1 {
 499                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 500                         };
 501
 502                         sd0_bus4: sd0-bus-width4 {
 503                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 504                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 505                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 506                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 507                         };
 508                 };
 509
 510                 sd1 {
 511                         sd1_clk: sd1-clk {
 512                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 513                         };
 514
 515                         sd1_cmd: sd1-cmd {
 516                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 517                         };
 518
 519                         sd1_cd: sd1-cd {
 520                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 521                         };
 522
 523                         sd1_wp: sd1-wp {
 524                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 525                         };
 526
 527                         sd1_bus1: sd1-bus-width1 {
 528                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 529                         };
 530
 531                         sd1_bus4: sd1-bus-width4 {
 532                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 533                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 534                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 535                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 536                         };
 537                 };
 538
 539                 i2s0 {
 540                         i2s0_bus: i2s0-bus {
 541                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 542                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 543                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 544                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 545                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 546                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 547                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 548                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 549                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 550                         };
 551                 };
 552
 553                 i2s1 {
 554                         i2s1_bus: i2s1-bus {
 555                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 556                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 557                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 558                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 559                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 560                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 561                         };
 562                 };
 563
 564                 i2s2 {
 565                         i2s2_bus: i2s2-bus {
 566                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 567                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 568                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 569                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 570                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 571                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 572                         };
 573                 };
 574         };
 575 };
 576
 577 &gpu {
 578         compatible = "rockchip,rk3066-mali", "arm,mali-400";
 579         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 580                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 581                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 582                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 583                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 584                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 585                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 586                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 587                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 588                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 589         interrupt-names = "gp",
 590                           "gpmmu",
 591                           "pp0",
 592                           "ppmmu0",
 593                           "pp1",
 594                           "ppmmu1",
 595                           "pp2",
 596                           "ppmmu2",
 597                           "pp3",
 598                           "ppmmu3";
 599         power-domains = <&power RK3066_PD_GPU>;
 600 };
 601
 602 &i2c0 {
 603         pinctrl-names = "default";
 604         pinctrl-0 = <&i2c0_xfer>;
 605 };
 606
 607 &i2c1 {
 608         pinctrl-names = "default";
 609         pinctrl-0 = <&i2c1_xfer>;
 610 };
 611
 612 &i2c2 {
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&i2c2_xfer>;
 615 };
 616
 617 &i2c3 {
 618         pinctrl-names = "default";
 619         pinctrl-0 = <&i2c3_xfer>;
 620 };
 621
 622 &i2c4 {
 623         pinctrl-names = "default";
 624         pinctrl-0 = <&i2c4_xfer>;
 625 };
 626
 627 &mmc0 {
 628         clock-frequency = <50000000>;
 629         dmas = <&dmac2 1>;
 630         dma-names = "rx-tx";
 631         max-frequency = <50000000>;
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 634 };
 635
 636 &mmc1 {
 637         dmas = <&dmac2 3>;
 638         dma-names = "rx-tx";
 639         pinctrl-names = "default";
 640         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 641 };
 642
 643 &emmc {
 644         dmas = <&dmac2 4>;
 645         dma-names = "rx-tx";
 646 };
 647
 648 &pmu {
 649         power: power-controller {
 650                 compatible = "rockchip,rk3066-power-controller";
 651                 #power-domain-cells = <1>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654
 655                 pd_vio@RK3066_PD_VIO {
 656                         reg = <RK3066_PD_VIO>;
 657                         clocks = <&cru ACLK_LCDC0>,
 658                                  <&cru ACLK_LCDC1>,
 659                                  <&cru DCLK_LCDC0>,
 660                                  <&cru DCLK_LCDC1>,
 661                                  <&cru HCLK_LCDC0>,
 662                                  <&cru HCLK_LCDC1>,
 663                                  <&cru SCLK_CIF1>,
 664                                  <&cru ACLK_CIF1>,
 665                                  <&cru HCLK_CIF1>,
 666                                  <&cru SCLK_CIF0>,
 667                                  <&cru ACLK_CIF0>,
 668                                  <&cru HCLK_CIF0>,
 669                                  <&cru ACLK_IPP>,
 670                                  <&cru HCLK_IPP>,
 671                                  <&cru ACLK_RGA>,
 672                                  <&cru HCLK_RGA>;
 673                         pm_qos = <&qos_lcdc0>,
 674                                  <&qos_lcdc1>,
 675                                  <&qos_cif0>,
 676                                  <&qos_cif1>,
 677                                  <&qos_ipp>,
 678                                  <&qos_rga>;
 679                 };
 680
 681                 pd_video@RK3066_PD_VIDEO {
 682                         reg = <RK3066_PD_VIDEO>;
 683                         clocks = <&cru ACLK_VDPU>,
 684                                  <&cru ACLK_VEPU>,
 685                                  <&cru HCLK_VDPU>,
 686                                  <&cru HCLK_VEPU>;
 687                         pm_qos = <&qos_vpu>;
 688                 };
 689
 690                 pd_gpu@RK3066_PD_GPU {
 691                         reg = <RK3066_PD_GPU>;
 692                         clocks = <&cru ACLK_GPU>;
 693                         pm_qos = <&qos_gpu>;
 694                 };
 695         };
 696 };
 697
 698 &pwm0 {
 699         pinctrl-names = "default";
 700         pinctrl-0 = <&pwm0_out>;
 701 };
 702
 703 &pwm1 {
 704         pinctrl-names = "default";
 705         pinctrl-0 = <&pwm1_out>;
 706 };
 707
 708 &pwm2 {
 709         pinctrl-names = "default";
 710         pinctrl-0 = <&pwm2_out>;
 711 };
 712
 713 &pwm3 {
 714         pinctrl-names = "default";
 715         pinctrl-0 = <&pwm3_out>;
 716 };
 717
 718 &spi0 {
 719         pinctrl-names = "default";
 720         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 721 };
 722
 723 &spi1 {
 724         pinctrl-names = "default";
 725         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 726 };
 727
 728 &uart0 {
 729         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 730         dmas = <&dmac1_s 0>, <&dmac1_s 1>;
 731         dma-names = "tx", "rx";
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&uart0_xfer>;
 734 };
 735
 736 &uart1 {
 737         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 738         dmas = <&dmac1_s 2>, <&dmac1_s 3>;
 739         dma-names = "tx", "rx";
 740         pinctrl-names = "default";
 741         pinctrl-0 = <&uart1_xfer>;
 742 };
 743
 744 &uart2 {
 745         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 746         dmas = <&dmac2 6>, <&dmac2 7>;
 747         dma-names = "tx", "rx";
 748         pinctrl-names = "default";
 749         pinctrl-0 = <&uart2_xfer>;
 750 };
 751
 752 &uart3 {
 753         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 754         dmas = <&dmac2 8>, <&dmac2 9>;
 755         dma-names = "tx", "rx";
 756         pinctrl-names = "default";
 757         pinctrl-0 = <&uart3_xfer>;
 758 };
 759
 760 &wdt {
 761         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 762 };
 763
 764 &emac {
 765         compatible = "rockchip,rk3066-emac";
 766 };