arch/arm/boot/dts/rk3188.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3188-cru.h>
  10 #include <dt-bindings/power/rk3188-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3188";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1608000 1350000
  29                                 1416000 1250000
  30                                 1200000 1150000
  31                                 1008000 1075000
  32                                  816000  975000
  33                                  600000  950000
  34                                  504000  925000
  35                                  312000  875000
  36                         >;
  37                         clock-latency = <40000>;
  38                         clocks = <&cru ARMCLK>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         next-level-cache = <&L2>;
  44                         reg = <0x1>;
  45                 };
  46                 cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         next-level-cache = <&L2>;
  50                         reg = <0x2>;
  51                 };
  52                 cpu@3 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         next-level-cache = <&L2>;
  56                         reg = <0x3>;
  57                 };
  58         };
  59
  60         display-subsystem {
  61                 compatible = "rockchip,display-subsystem";
  62                 ports = <&vop0_out>, <&vop1_out>;
  63         };
  64
  65         sram: sram@10080000 {
  66                 compatible = "mmio-sram";
  67                 reg = <0x10080000 0x8000>;
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges = <0 0x10080000 0x8000>;
  71
  72                 smp-sram@0 {
  73                         compatible = "rockchip,rk3066-smp-sram";
  74                         reg = <0x0 0x50>;
  75                 };
  76         };
  77
  78         vop0: vop@1010c000 {
  79                 compatible = "rockchip,rk3188-vop";
  80                 reg = <0x1010c000 0x1000>;
  81                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  82                 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
  83                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  84                 power-domains = <&power RK3188_PD_VIO>;
  85                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
  86                 reset-names = "axi", "ahb", "dclk";
  87                 status = "disabled";
  88
  89                 vop0_out: port {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                 };
  93         };
  94
  95         vop1: vop@1010e000 {
  96                 compatible = "rockchip,rk3188-vop";
  97                 reg = <0x1010e000 0x1000>;
  98                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  99                 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
 100                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 101                 power-domains = <&power RK3188_PD_VIO>;
 102                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 103                 reset-names = "axi", "ahb", "dclk";
 104                 status = "disabled";
 105
 106                 vop1_out: port {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                 };
 110         };
 111
 112         timer3: timer@2000e000 {
 113                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 114                 reg = <0x2000e000 0x20>;
 115                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 116                 clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
 117                 clock-names = "timer", "pclk";
 118         };
 119
 120         timer6: timer@200380a0 {
 121                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 122                 reg = <0x200380a0 0x20>;
 123                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 124                 clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
 125                 clock-names = "timer", "pclk";
 126         };
 127
 128         i2s0: i2s@1011a000 {
 129                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 130                 reg = <0x1011a000 0x2000>;
 131                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134                 pinctrl-names = "default";
 135                 pinctrl-0 = <&i2s0_bus>;
 136                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 137                 dma-names = "tx", "rx";
 138                 clock-names = "i2s_hclk", "i2s_clk";
 139                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 140                 rockchip,playback-channels = <2>;
 141                 rockchip,capture-channels = <2>;
 142                 status = "disabled";
 143         };
 144
 145         spdif: sound@1011e000 {
 146                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 147                 reg = <0x1011e000 0x2000>;
 148                 #sound-dai-cells = <0>;
 149                 clock-names = "hclk", "mclk";
 150                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
 151                 dmas = <&dmac1_s 8>;
 152                 dma-names = "tx";
 153                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 154                 pinctrl-names = "default";
 155                 pinctrl-0 = <&spdif_tx>;
 156                 status = "disabled";
 157         };
 158
 159         cru: clock-controller@20000000 {
 160                 compatible = "rockchip,rk3188-cru";
 161                 reg = <0x20000000 0x1000>;
 162                 rockchip,grf = <&grf>;
 163
 164                 #clock-cells = <1>;
 165                 #reset-cells = <1>;
 166         };
 167
 168         efuse: efuse@20010000 {
 169                 compatible = "rockchip,rk3188-efuse";
 170                 reg = <0x20010000 0x4000>;
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 clocks = <&cru PCLK_EFUSE>;
 174                 clock-names = "pclk_efuse";
 175
 176                 cpu_leakage: cpu_leakage@17 {
 177                         reg = <0x17 0x1>;
 178                 };
 179         };
 180
 181         usbphy: phy {
 182                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 183                 rockchip,grf = <&grf>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 status = "disabled";
 187
 188                 usbphy0: usb-phy@10c {
 189                         #phy-cells = <0>;
 190                         reg = <0x10c>;
 191                         clocks = <&cru SCLK_OTGPHY0>;
 192                         clock-names = "phyclk";
 193                         #clock-cells = <0>;
 194                 };
 195
 196                 usbphy1: usb-phy@11c {
 197                         #phy-cells = <0>;
 198                         reg = <0x11c>;
 199                         clocks = <&cru SCLK_OTGPHY1>;
 200                         clock-names = "phyclk";
 201                         #clock-cells = <0>;
 202                 };
 203         };
 204
 205         pinctrl: pinctrl {
 206                 compatible = "rockchip,rk3188-pinctrl";
 207                 rockchip,grf = <&grf>;
 208                 rockchip,pmu = <&pmu>;
 209
 210                 #address-cells = <1>;
 211                 #size-cells = <1>;
 212                 ranges;
 213
 214                 gpio0: gpio0@2000a000 {
 215                         compatible = "rockchip,rk3188-gpio-bank0";
 216                         reg = <0x2000a000 0x100>;
 217                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&cru PCLK_GPIO0>;
 219
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222
 223                         interrupt-controller;
 224                         #interrupt-cells = <2>;
 225                 };
 226
 227                 gpio1: gpio1@2003c000 {
 228                         compatible = "rockchip,gpio-bank";
 229                         reg = <0x2003c000 0x100>;
 230                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&cru PCLK_GPIO1>;
 232
 233                         gpio-controller;
 234                         #gpio-cells = <2>;
 235
 236                         interrupt-controller;
 237                         #interrupt-cells = <2>;
 238                 };
 239
 240                 gpio2: gpio2@2003e000 {
 241                         compatible = "rockchip,gpio-bank";
 242                         reg = <0x2003e000 0x100>;
 243                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 244                         clocks = <&cru PCLK_GPIO2>;
 245
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248
 249                         interrupt-controller;
 250                         #interrupt-cells = <2>;
 251                 };
 252
 253                 gpio3: gpio3@20080000 {
 254                         compatible = "rockchip,gpio-bank";
 255                         reg = <0x20080000 0x100>;
 256                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&cru PCLK_GPIO3>;
 258
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261
 262                         interrupt-controller;
 263                         #interrupt-cells = <2>;
 264                 };
 265
 266                 pcfg_pull_up: pcfg_pull_up {
 267                         bias-pull-up;
 268                 };
 269
 270                 pcfg_pull_down: pcfg_pull_down {
 271                         bias-pull-down;
 272                 };
 273
 274                 pcfg_pull_none: pcfg_pull_none {
 275                         bias-disable;
 276                 };
 277
 278                 emmc {
 279                         emmc_clk: emmc-clk {
 280                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 281                         };
 282
 283                         emmc_cmd: emmc-cmd {
 284                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 285                         };
 286
 287                         emmc_rst: emmc-rst {
 288                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 289                         };
 290
 291                         /*
 292                          * The data pins are shared between nandc and emmc and
 293                          * not accessible through pinctrl. Also they should've
 294                          * been already set correctly by firmware, as
 295                          * flash/emmc is the boot-device.
 296                          */
 297                 };
 298
 299                 emac {
 300                         emac_xfer: emac-xfer {
 301                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 302                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 303                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 304                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 305                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 306                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 307                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 308                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 309                         };
 310
 311                         emac_mdio: emac-mdio {
 312                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 313                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 314                         };
 315                 };
 316
 317                 i2c0 {
 318                         i2c0_xfer: i2c0-xfer {
 319                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 320                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 321                         };
 322                 };
 323
 324                 i2c1 {
 325                         i2c1_xfer: i2c1-xfer {
 326                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 327                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 328                         };
 329                 };
 330
 331                 i2c2 {
 332                         i2c2_xfer: i2c2-xfer {
 333                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 334                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 335                         };
 336                 };
 337
 338                 i2c3 {
 339                         i2c3_xfer: i2c3-xfer {
 340                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 341                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 342                         };
 343                 };
 344
 345                 i2c4 {
 346                         i2c4_xfer: i2c4-xfer {
 347                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 348                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 349                         };
 350                 };
 351
 352                 lcdc1 {
 353                         lcdc1_dclk: lcdc1-dclk {
 354                                 rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 355                         };
 356
 357                         lcdc1_den: lcdc1-den {
 358                                 rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 359                         };
 360
 361                         lcdc1_hsync: lcdc1-hsync {
 362                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
 363                         };
 364
 365                         lcdc1_vsync: lcdc1-vsync {
 366                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
 367                         };
 368
 369                         lcdc1_rgb24: ldcd1-rgb24 {
 370                                 rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
 371                                                 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
 372                                                 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
 373                                                 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
 374                                                 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
 375                                                 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
 376                                                 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
 377                                                 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
 378                                                 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
 379                                                 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
 380                                                 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
 381                                                 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
 382                                                 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
 383                                                 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
 384                                                 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
 385                                                 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
 386                                                 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
 387                                                 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
 388                                                 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
 389                                                 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
 390                                                 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
 391                                                 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
 392                                                 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
 393                                                 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
 394                         };
 395                 };
 396
 397                 pwm0 {
 398                         pwm0_out: pwm0-out {
 399                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 400                         };
 401                 };
 402
 403                 pwm1 {
 404                         pwm1_out: pwm1-out {
 405                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 406                         };
 407                 };
 408
 409                 pwm2 {
 410                         pwm2_out: pwm2-out {
 411                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 412                         };
 413                 };
 414
 415                 pwm3 {
 416                         pwm3_out: pwm3-out {
 417                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 418                         };
 419                 };
 420
 421                 spi0 {
 422                         spi0_clk: spi0-clk {
 423                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 424                         };
 425                         spi0_cs0: spi0-cs0 {
 426                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 427                         };
 428                         spi0_tx: spi0-tx {
 429                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 430                         };
 431                         spi0_rx: spi0-rx {
 432                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 433                         };
 434                         spi0_cs1: spi0-cs1 {
 435                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 436                         };
 437                 };
 438
 439                 spi1 {
 440                         spi1_clk: spi1-clk {
 441                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 442                         };
 443                         spi1_cs0: spi1-cs0 {
 444                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 445                         };
 446                         spi1_rx: spi1-rx {
 447                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 448                         };
 449                         spi1_tx: spi1-tx {
 450                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 451                         };
 452                         spi1_cs1: spi1-cs1 {
 453                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 454                         };
 455                 };
 456
 457                 uart0 {
 458                         uart0_xfer: uart0-xfer {
 459                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 460                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 461                         };
 462
 463                         uart0_cts: uart0-cts {
 464                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 465                         };
 466
 467                         uart0_rts: uart0-rts {
 468                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 469                         };
 470                 };
 471
 472                 uart1 {
 473                         uart1_xfer: uart1-xfer {
 474                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 475                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 476                         };
 477
 478                         uart1_cts: uart1-cts {
 479                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 480                         };
 481
 482                         uart1_rts: uart1-rts {
 483                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 484                         };
 485                 };
 486
 487                 uart2 {
 488                         uart2_xfer: uart2-xfer {
 489                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 490                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 491                         };
 492                         /* no rts / cts for uart2 */
 493                 };
 494
 495                 uart3 {
 496                         uart3_xfer: uart3-xfer {
 497                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 498                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 499                         };
 500
 501                         uart3_cts: uart3-cts {
 502                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 503                         };
 504
 505                         uart3_rts: uart3-rts {
 506                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 507                         };
 508                 };
 509
 510                 sd0 {
 511                         sd0_clk: sd0-clk {
 512                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 513                         };
 514
 515                         sd0_cmd: sd0-cmd {
 516                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 517                         };
 518
 519                         sd0_cd: sd0-cd {
 520                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 521                         };
 522
 523                         sd0_wp: sd0-wp {
 524                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 525                         };
 526
 527                         sd0_pwr: sd0-pwr {
 528                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 529                         };
 530
 531                         sd0_bus1: sd0-bus-width1 {
 532                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 533                         };
 534
 535                         sd0_bus4: sd0-bus-width4 {
 536                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 537                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 538                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 539                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 540                         };
 541                 };
 542
 543                 sd1 {
 544                         sd1_clk: sd1-clk {
 545                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 546                         };
 547
 548                         sd1_cmd: sd1-cmd {
 549                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 550                         };
 551
 552                         sd1_cd: sd1-cd {
 553                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 554                         };
 555
 556                         sd1_wp: sd1-wp {
 557                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 558                         };
 559
 560                         sd1_bus1: sd1-bus-width1 {
 561                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 562                         };
 563
 564                         sd1_bus4: sd1-bus-width4 {
 565                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 566                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 567                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 568                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 569                         };
 570                 };
 571
 572                 i2s0 {
 573                         i2s0_bus: i2s0-bus {
 574                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 575                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 576                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 577                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 578                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 579                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 580                         };
 581                 };
 582
 583                 spdif {
 584                         spdif_tx: spdif-tx {
 585                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 586                         };
 587                 };
 588         };
 589 };
 590
 591 &emac {
 592         compatible = "rockchip,rk3188-emac";
 593 };
 594
 595 &global_timer {
 596         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 597         status = "disabled";
 598 };
 599
 600 &local_timer {
 601         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 602 };
 603
 604 &gpu {
 605         compatible = "rockchip,rk3188-mali", "arm,mali-400";
 606         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 607                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 608                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 609                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 610                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 611                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 612                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 613                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 614                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 615                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 616         interrupt-names = "gp",
 617                           "gpmmu",
 618                           "pp0",
 619                           "ppmmu0",
 620                           "pp1",
 621                           "ppmmu1",
 622                           "pp2",
 623                           "ppmmu2",
 624                           "pp3",
 625                           "ppmmu3";
 626         power-domains = <&power RK3188_PD_GPU>;
 627 };
 628
 629 &i2c0 {
 630         compatible = "rockchip,rk3188-i2c";
 631         pinctrl-names = "default";
 632         pinctrl-0 = <&i2c0_xfer>;
 633 };
 634
 635 &i2c1 {
 636         compatible = "rockchip,rk3188-i2c";
 637         pinctrl-names = "default";
 638         pinctrl-0 = <&i2c1_xfer>;
 639 };
 640
 641 &i2c2 {
 642         compatible = "rockchip,rk3188-i2c";
 643         pinctrl-names = "default";
 644         pinctrl-0 = <&i2c2_xfer>;
 645 };
 646
 647 &i2c3 {
 648         compatible = "rockchip,rk3188-i2c";
 649         pinctrl-names = "default";
 650         pinctrl-0 = <&i2c3_xfer>;
 651 };
 652
 653 &i2c4 {
 654         compatible = "rockchip,rk3188-i2c";
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&i2c4_xfer>;
 657 };
 658
 659 &pmu {
 660         power: power-controller {
 661                 compatible = "rockchip,rk3188-power-controller";
 662                 #power-domain-cells = <1>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665
 666                 pd_vio@RK3188_PD_VIO {
 667                         reg = <RK3188_PD_VIO>;
 668                         clocks = <&cru ACLK_LCDC0>,
 669                                  <&cru ACLK_LCDC1>,
 670                                  <&cru DCLK_LCDC0>,
 671                                  <&cru DCLK_LCDC1>,
 672                                  <&cru HCLK_LCDC0>,
 673                                  <&cru HCLK_LCDC1>,
 674                                  <&cru SCLK_CIF0>,
 675                                  <&cru ACLK_CIF0>,
 676                                  <&cru HCLK_CIF0>,
 677                                  <&cru ACLK_IPP>,
 678                                  <&cru HCLK_IPP>,
 679                                  <&cru ACLK_RGA>,
 680                                  <&cru HCLK_RGA>;
 681                         pm_qos = <&qos_lcdc0>,
 682                                  <&qos_lcdc1>,
 683                                  <&qos_cif0>,
 684                                  <&qos_cif1>,
 685                                  <&qos_ipp>,
 686                                  <&qos_rga>;
 687                 };
 688
 689                 pd_video@RK3188_PD_VIDEO {
 690                         reg = <RK3188_PD_VIDEO>;
 691                         clocks = <&cru ACLK_VDPU>,
 692                                  <&cru ACLK_VEPU>,
 693                                  <&cru HCLK_VDPU>,
 694                                  <&cru HCLK_VEPU>;
 695                         pm_qos = <&qos_vpu>;
 696                 };
 697
 698                 pd_gpu@RK3188_PD_GPU {
 699                         reg = <RK3188_PD_GPU>;
 700                         clocks = <&cru ACLK_GPU>;
 701                         pm_qos = <&qos_gpu>;
 702                 };
 703         };
 704 };
 705
 706 &pwm0 {
 707         pinctrl-names = "default";
 708         pinctrl-0 = <&pwm0_out>;
 709 };
 710
 711 &pwm1 {
 712         pinctrl-names = "default";
 713         pinctrl-0 = <&pwm1_out>;
 714 };
 715
 716 &pwm2 {
 717         pinctrl-names = "default";
 718         pinctrl-0 = <&pwm2_out>;
 719 };
 720
 721 &pwm3 {
 722         pinctrl-names = "default";
 723         pinctrl-0 = <&pwm3_out>;
 724 };
 725
 726 &spi0 {
 727         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 728         pinctrl-names = "default";
 729         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 730 };
 731
 732 &spi1 {
 733         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 734         pinctrl-names = "default";
 735         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 736 };
 737
 738 &uart0 {
 739         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 740         pinctrl-names = "default";
 741         pinctrl-0 = <&uart0_xfer>;
 742 };
 743
 744 &uart1 {
 745         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 746         pinctrl-names = "default";
 747         pinctrl-0 = <&uart1_xfer>;
 748 };
 749
 750 &uart2 {
 751         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 752         pinctrl-names = "default";
 753         pinctrl-0 = <&uart2_xfer>;
 754 };
 755
 756 &uart3 {
 757         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 758         pinctrl-names = "default";
 759         pinctrl-0 = <&uart3_xfer>;
 760 };
 761
 762 &wdt {
 763         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 764 };