Merge tag 'for-linus-20190407' of git://git.kernel.dk/linux-block
[muen/linux.git] / arch / arm / boot / dts / rk3288.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/power/rk3288-power.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12
13 / {
14         #address-cells = <2>;
15         #size-cells = <2>;
16
17         compatible = "rockchip,rk3288";
18
19         interrupt-parent = <&gic>;
20
21         aliases {
22                 ethernet0 = &gmac;
23                 i2c0 = &i2c0;
24                 i2c1 = &i2c1;
25                 i2c2 = &i2c2;
26                 i2c3 = &i2c3;
27                 i2c4 = &i2c4;
28                 i2c5 = &i2c5;
29                 mshc0 = &emmc;
30                 mshc1 = &sdmmc;
31                 mshc2 = &sdio0;
32                 mshc3 = &sdio1;
33                 serial0 = &uart0;
34                 serial1 = &uart1;
35                 serial2 = &uart2;
36                 serial3 = &uart3;
37                 serial4 = &uart4;
38                 spi0 = &spi0;
39                 spi1 = &spi1;
40                 spi2 = &spi2;
41         };
42
43         arm-pmu {
44                 compatible = "arm,cortex-a12-pmu";
45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
50         };
51
52         cpus {
53                 #address-cells = <1>;
54                 #size-cells = <0>;
55                 enable-method = "rockchip,rk3066-smp";
56                 rockchip,pmu = <&pmu>;
57
58                 cpu0: cpu@500 {
59                         device_type = "cpu";
60                         compatible = "arm,cortex-a12";
61                         reg = <0x500>;
62                         resets = <&cru SRST_CORE0>;
63                         operating-points-v2 = <&cpu_opp_table>;
64                         #cooling-cells = <2>; /* min followed by max */
65                         clock-latency = <40000>;
66                         clocks = <&cru ARMCLK>;
67                 };
68                 cpu1: cpu@501 {
69                         device_type = "cpu";
70                         compatible = "arm,cortex-a12";
71                         reg = <0x501>;
72                         resets = <&cru SRST_CORE1>;
73                         operating-points = <&cpu_opp_table>;
74                         #cooling-cells = <2>; /* min followed by max */
75                         clock-latency = <40000>;
76                         clocks = <&cru ARMCLK>;
77                 };
78                 cpu2: cpu@502 {
79                         device_type = "cpu";
80                         compatible = "arm,cortex-a12";
81                         reg = <0x502>;
82                         resets = <&cru SRST_CORE2>;
83                         operating-points = <&cpu_opp_table>;
84                         #cooling-cells = <2>; /* min followed by max */
85                         clock-latency = <40000>;
86                         clocks = <&cru ARMCLK>;
87                 };
88                 cpu3: cpu@503 {
89                         device_type = "cpu";
90                         compatible = "arm,cortex-a12";
91                         reg = <0x503>;
92                         resets = <&cru SRST_CORE3>;
93                         operating-points = <&cpu_opp_table>;
94                         #cooling-cells = <2>; /* min followed by max */
95                         clock-latency = <40000>;
96                         clocks = <&cru ARMCLK>;
97                 };
98         };
99
100         cpu_opp_table: cpu-opp-table {
101                 compatible = "operating-points-v2";
102                 opp-shared;
103
104                 opp-126000000 {
105                         opp-hz = /bits/ 64 <126000000>;
106                         opp-microvolt = <900000>;
107                 };
108                 opp-216000000 {
109                         opp-hz = /bits/ 64 <216000000>;
110                         opp-microvolt = <900000>;
111                 };
112                 opp-312000000 {
113                         opp-hz = /bits/ 64 <312000000>;
114                         opp-microvolt = <900000>;
115                 };
116                 opp-408000000 {
117                         opp-hz = /bits/ 64 <408000000>;
118                         opp-microvolt = <900000>;
119                 };
120                 opp-600000000 {
121                         opp-hz = /bits/ 64 <600000000>;
122                         opp-microvolt = <900000>;
123                 };
124                 opp-696000000 {
125                         opp-hz = /bits/ 64 <696000000>;
126                         opp-microvolt = <950000>;
127                 };
128                 opp-816000000 {
129                         opp-hz = /bits/ 64 <816000000>;
130                         opp-microvolt = <1000000>;
131                 };
132                 opp-1008000000 {
133                         opp-hz = /bits/ 64 <1008000000>;
134                         opp-microvolt = <1050000>;
135                 };
136                 opp-1200000000 {
137                         opp-hz = /bits/ 64 <1200000000>;
138                         opp-microvolt = <1100000>;
139                 };
140                 opp-1416000000 {
141                         opp-hz = /bits/ 64 <1416000000>;
142                         opp-microvolt = <1200000>;
143                 };
144                 opp-1512000000 {
145                         opp-hz = /bits/ 64 <1512000000>;
146                         opp-microvolt = <1300000>;
147                 };
148                 opp-1608000000 {
149                         opp-hz = /bits/ 64 <1608000000>;
150                         opp-microvolt = <1350000>;
151                 };
152         };
153
154         amba {
155                 compatible = "simple-bus";
156                 #address-cells = <2>;
157                 #size-cells = <2>;
158                 ranges;
159
160                 dmac_peri: dma-controller@ff250000 {
161                         compatible = "arm,pl330", "arm,primecell";
162                         reg = <0x0 0xff250000 0x0 0x4000>;
163                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
164                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
165                         #dma-cells = <1>;
166                         arm,pl330-broken-no-flushp;
167                         clocks = <&cru ACLK_DMAC2>;
168                         clock-names = "apb_pclk";
169                 };
170
171                 dmac_bus_ns: dma-controller@ff600000 {
172                         compatible = "arm,pl330", "arm,primecell";
173                         reg = <0x0 0xff600000 0x0 0x4000>;
174                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
175                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
176                         #dma-cells = <1>;
177                         arm,pl330-broken-no-flushp;
178                         clocks = <&cru ACLK_DMAC1>;
179                         clock-names = "apb_pclk";
180                         status = "disabled";
181                 };
182
183                 dmac_bus_s: dma-controller@ffb20000 {
184                         compatible = "arm,pl330", "arm,primecell";
185                         reg = <0x0 0xffb20000 0x0 0x4000>;
186                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
187                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
188                         #dma-cells = <1>;
189                         arm,pl330-broken-no-flushp;
190                         clocks = <&cru ACLK_DMAC1>;
191                         clock-names = "apb_pclk";
192                 };
193         };
194
195         reserved-memory {
196                 #address-cells = <2>;
197                 #size-cells = <2>;
198                 ranges;
199
200                 /*
201                  * The rk3288 cannot use the memory area above 0xfe000000
202                  * for dma operations for some reason. While there is
203                  * probably a better solution available somewhere, we
204                  * haven't found it yet and while devices with 2GB of ram
205                  * are not affected, this issue prevents 4GB from booting.
206                  * So to make these devices at least bootable, block
207                  * this area for the time being until the real solution
208                  * is found.
209                  */
210                 dma-unusable@fe000000 {
211                         reg = <0x0 0xfe000000 0x0 0x1000000>;
212                 };
213         };
214
215         xin24m: oscillator {
216                 compatible = "fixed-clock";
217                 clock-frequency = <24000000>;
218                 clock-output-names = "xin24m";
219                 #clock-cells = <0>;
220         };
221
222         timer {
223                 compatible = "arm,armv7-timer";
224                 arm,cpu-registers-not-fw-configured;
225                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
226                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
227                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
228                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
229                 clock-frequency = <24000000>;
230         };
231
232         timer: timer@ff810000 {
233                 compatible = "rockchip,rk3288-timer";
234                 reg = <0x0 0xff810000 0x0 0x20>;
235                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
236                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
237                 clock-names = "timer", "pclk";
238         };
239
240         display-subsystem {
241                 compatible = "rockchip,display-subsystem";
242                 ports = <&vopl_out>, <&vopb_out>;
243         };
244
245         sdmmc: dwmmc@ff0c0000 {
246                 compatible = "rockchip,rk3288-dw-mshc";
247                 max-frequency = <150000000>;
248                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
249                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
250                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251                 fifo-depth = <0x100>;
252                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
253                 reg = <0x0 0xff0c0000 0x0 0x4000>;
254                 resets = <&cru SRST_MMC0>;
255                 reset-names = "reset";
256                 status = "disabled";
257         };
258
259         sdio0: dwmmc@ff0d0000 {
260                 compatible = "rockchip,rk3288-dw-mshc";
261                 max-frequency = <150000000>;
262                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
263                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
264                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265                 fifo-depth = <0x100>;
266                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
267                 reg = <0x0 0xff0d0000 0x0 0x4000>;
268                 resets = <&cru SRST_SDIO0>;
269                 reset-names = "reset";
270                 status = "disabled";
271         };
272
273         sdio1: dwmmc@ff0e0000 {
274                 compatible = "rockchip,rk3288-dw-mshc";
275                 max-frequency = <150000000>;
276                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
277                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
278                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279                 fifo-depth = <0x100>;
280                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
281                 reg = <0x0 0xff0e0000 0x0 0x4000>;
282                 resets = <&cru SRST_SDIO1>;
283                 reset-names = "reset";
284                 status = "disabled";
285         };
286
287         emmc: dwmmc@ff0f0000 {
288                 compatible = "rockchip,rk3288-dw-mshc";
289                 max-frequency = <150000000>;
290                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
291                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
292                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
293                 fifo-depth = <0x100>;
294                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
295                 reg = <0x0 0xff0f0000 0x0 0x4000>;
296                 resets = <&cru SRST_EMMC>;
297                 reset-names = "reset";
298                 status = "disabled";
299         };
300
301         saradc: saradc@ff100000 {
302                 compatible = "rockchip,saradc";
303                 reg = <0x0 0xff100000 0x0 0x100>;
304                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
305                 #io-channel-cells = <1>;
306                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
307                 clock-names = "saradc", "apb_pclk";
308                 resets = <&cru SRST_SARADC>;
309                 reset-names = "saradc-apb";
310                 status = "disabled";
311         };
312
313         spi0: spi@ff110000 {
314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
315                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
316                 clock-names = "spiclk", "apb_pclk";
317                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
318                 dma-names = "tx", "rx";
319                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
320                 pinctrl-names = "default";
321                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
322                 reg = <0x0 0xff110000 0x0 0x1000>;
323                 #address-cells = <1>;
324                 #size-cells = <0>;
325                 status = "disabled";
326         };
327
328         spi1: spi@ff120000 {
329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
330                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
331                 clock-names = "spiclk", "apb_pclk";
332                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
333                 dma-names = "tx", "rx";
334                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
335                 pinctrl-names = "default";
336                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
337                 reg = <0x0 0xff120000 0x0 0x1000>;
338                 #address-cells = <1>;
339                 #size-cells = <0>;
340                 status = "disabled";
341         };
342
343         spi2: spi@ff130000 {
344                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
345                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
346                 clock-names = "spiclk", "apb_pclk";
347                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
348                 dma-names = "tx", "rx";
349                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
350                 pinctrl-names = "default";
351                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
352                 reg = <0x0 0xff130000 0x0 0x1000>;
353                 #address-cells = <1>;
354                 #size-cells = <0>;
355                 status = "disabled";
356         };
357
358         i2c1: i2c@ff140000 {
359                 compatible = "rockchip,rk3288-i2c";
360                 reg = <0x0 0xff140000 0x0 0x1000>;
361                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
362                 #address-cells = <1>;
363                 #size-cells = <0>;
364                 clock-names = "i2c";
365                 clocks = <&cru PCLK_I2C1>;
366                 pinctrl-names = "default";
367                 pinctrl-0 = <&i2c1_xfer>;
368                 status = "disabled";
369         };
370
371         i2c3: i2c@ff150000 {
372                 compatible = "rockchip,rk3288-i2c";
373                 reg = <0x0 0xff150000 0x0 0x1000>;
374                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
375                 #address-cells = <1>;
376                 #size-cells = <0>;
377                 clock-names = "i2c";
378                 clocks = <&cru PCLK_I2C3>;
379                 pinctrl-names = "default";
380                 pinctrl-0 = <&i2c3_xfer>;
381                 status = "disabled";
382         };
383
384         i2c4: i2c@ff160000 {
385                 compatible = "rockchip,rk3288-i2c";
386                 reg = <0x0 0xff160000 0x0 0x1000>;
387                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
388                 #address-cells = <1>;
389                 #size-cells = <0>;
390                 clock-names = "i2c";
391                 clocks = <&cru PCLK_I2C4>;
392                 pinctrl-names = "default";
393                 pinctrl-0 = <&i2c4_xfer>;
394                 status = "disabled";
395         };
396
397         i2c5: i2c@ff170000 {
398                 compatible = "rockchip,rk3288-i2c";
399                 reg = <0x0 0xff170000 0x0 0x1000>;
400                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
401                 #address-cells = <1>;
402                 #size-cells = <0>;
403                 clock-names = "i2c";
404                 clocks = <&cru PCLK_I2C5>;
405                 pinctrl-names = "default";
406                 pinctrl-0 = <&i2c5_xfer>;
407                 status = "disabled";
408         };
409
410         uart0: serial@ff180000 {
411                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
412                 reg = <0x0 0xff180000 0x0 0x100>;
413                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
414                 reg-shift = <2>;
415                 reg-io-width = <4>;
416                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
417                 clock-names = "baudclk", "apb_pclk";
418                 pinctrl-names = "default";
419                 pinctrl-0 = <&uart0_xfer>;
420                 status = "disabled";
421         };
422
423         uart1: serial@ff190000 {
424                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
425                 reg = <0x0 0xff190000 0x0 0x100>;
426                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
427                 reg-shift = <2>;
428                 reg-io-width = <4>;
429                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
430                 clock-names = "baudclk", "apb_pclk";
431                 pinctrl-names = "default";
432                 pinctrl-0 = <&uart1_xfer>;
433                 status = "disabled";
434         };
435
436         uart2: serial@ff690000 {
437                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
438                 reg = <0x0 0xff690000 0x0 0x100>;
439                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
440                 reg-shift = <2>;
441                 reg-io-width = <4>;
442                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
443                 clock-names = "baudclk", "apb_pclk";
444                 pinctrl-names = "default";
445                 pinctrl-0 = <&uart2_xfer>;
446                 status = "disabled";
447         };
448
449         uart3: serial@ff1b0000 {
450                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
451                 reg = <0x0 0xff1b0000 0x0 0x100>;
452                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
453                 reg-shift = <2>;
454                 reg-io-width = <4>;
455                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
456                 clock-names = "baudclk", "apb_pclk";
457                 pinctrl-names = "default";
458                 pinctrl-0 = <&uart3_xfer>;
459                 status = "disabled";
460         };
461
462         uart4: serial@ff1c0000 {
463                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
464                 reg = <0x0 0xff1c0000 0x0 0x100>;
465                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
466                 reg-shift = <2>;
467                 reg-io-width = <4>;
468                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
469                 clock-names = "baudclk", "apb_pclk";
470                 pinctrl-names = "default";
471                 pinctrl-0 = <&uart4_xfer>;
472                 status = "disabled";
473         };
474
475         thermal-zones {
476                 reserve_thermal: reserve_thermal {
477                         polling-delay-passive = <1000>; /* milliseconds */
478                         polling-delay = <5000>; /* milliseconds */
479
480                         thermal-sensors = <&tsadc 0>;
481                 };
482
483                 cpu_thermal: cpu_thermal {
484                         polling-delay-passive = <100>; /* milliseconds */
485                         polling-delay = <5000>; /* milliseconds */
486
487                         thermal-sensors = <&tsadc 1>;
488
489                         trips {
490                                 cpu_alert0: cpu_alert0 {
491                                         temperature = <70000>; /* millicelsius */
492                                         hysteresis = <2000>; /* millicelsius */
493                                         type = "passive";
494                                 };
495                                 cpu_alert1: cpu_alert1 {
496                                         temperature = <75000>; /* millicelsius */
497                                         hysteresis = <2000>; /* millicelsius */
498                                         type = "passive";
499                                 };
500                                 cpu_crit: cpu_crit {
501                                         temperature = <90000>; /* millicelsius */
502                                         hysteresis = <2000>; /* millicelsius */
503                                         type = "critical";
504                                 };
505                         };
506
507                         cooling-maps {
508                                 map0 {
509                                         trip = <&cpu_alert0>;
510                                         cooling-device =
511                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
512                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
513                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
514                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
515                                 };
516                                 map1 {
517                                         trip = <&cpu_alert1>;
518                                         cooling-device =
519                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
520                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
521                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
522                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
523                                 };
524                         };
525                 };
526
527                 gpu_thermal: gpu_thermal {
528                         polling-delay-passive = <100>; /* milliseconds */
529                         polling-delay = <5000>; /* milliseconds */
530
531                         thermal-sensors = <&tsadc 2>;
532
533                         trips {
534                                 gpu_alert0: gpu_alert0 {
535                                         temperature = <70000>; /* millicelsius */
536                                         hysteresis = <2000>; /* millicelsius */
537                                         type = "passive";
538                                 };
539                                 gpu_crit: gpu_crit {
540                                         temperature = <90000>; /* millicelsius */
541                                         hysteresis = <2000>; /* millicelsius */
542                                         type = "critical";
543                                 };
544                         };
545
546                         cooling-maps {
547                                 map0 {
548                                         trip = <&gpu_alert0>;
549                                         cooling-device =
550                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
551                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
552                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
553                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
554                                 };
555                         };
556                 };
557         };
558
559         tsadc: tsadc@ff280000 {
560                 compatible = "rockchip,rk3288-tsadc";
561                 reg = <0x0 0xff280000 0x0 0x100>;
562                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
563                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
564                 clock-names = "tsadc", "apb_pclk";
565                 resets = <&cru SRST_TSADC>;
566                 reset-names = "tsadc-apb";
567                 pinctrl-names = "init", "default", "sleep";
568                 pinctrl-0 = <&otp_gpio>;
569                 pinctrl-1 = <&otp_out>;
570                 pinctrl-2 = <&otp_gpio>;
571                 #thermal-sensor-cells = <1>;
572                 rockchip,hw-tshut-temp = <95000>;
573                 status = "disabled";
574         };
575
576         gmac: ethernet@ff290000 {
577                 compatible = "rockchip,rk3288-gmac";
578                 reg = <0x0 0xff290000 0x0 0x10000>;
579                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
580                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
581                 interrupt-names = "macirq", "eth_wake_irq";
582                 rockchip,grf = <&grf>;
583                 clocks = <&cru SCLK_MAC>,
584                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
585                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
586                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
587                 clock-names = "stmmaceth",
588                         "mac_clk_rx", "mac_clk_tx",
589                         "clk_mac_ref", "clk_mac_refout",
590                         "aclk_mac", "pclk_mac";
591                 resets = <&cru SRST_MAC>;
592                 reset-names = "stmmaceth";
593                 status = "disabled";
594         };
595
596         usb_host0_ehci: usb@ff500000 {
597                 compatible = "generic-ehci";
598                 reg = <0x0 0xff500000 0x0 0x100>;
599                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
600                 clocks = <&cru HCLK_USBHOST0>;
601                 clock-names = "usbhost";
602                 phys = <&usbphy1>;
603                 phy-names = "usb";
604                 status = "disabled";
605         };
606
607         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
608
609         usb_host1: usb@ff540000 {
610                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
611                                 "snps,dwc2";
612                 reg = <0x0 0xff540000 0x0 0x40000>;
613                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
614                 clocks = <&cru HCLK_USBHOST1>;
615                 clock-names = "otg";
616                 dr_mode = "host";
617                 phys = <&usbphy2>;
618                 phy-names = "usb2-phy";
619                 status = "disabled";
620         };
621
622         usb_otg: usb@ff580000 {
623                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
624                                 "snps,dwc2";
625                 reg = <0x0 0xff580000 0x0 0x40000>;
626                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
627                 clocks = <&cru HCLK_OTG0>;
628                 clock-names = "otg";
629                 dr_mode = "otg";
630                 g-np-tx-fifo-size = <16>;
631                 g-rx-fifo-size = <275>;
632                 g-tx-fifo-size = <256 128 128 64 64 32>;
633                 phys = <&usbphy0>;
634                 phy-names = "usb2-phy";
635                 status = "disabled";
636         };
637
638         usb_hsic: usb@ff5c0000 {
639                 compatible = "generic-ehci";
640                 reg = <0x0 0xff5c0000 0x0 0x100>;
641                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
642                 clocks = <&cru HCLK_HSIC>;
643                 clock-names = "usbhost";
644                 status = "disabled";
645         };
646
647         i2c0: i2c@ff650000 {
648                 compatible = "rockchip,rk3288-i2c";
649                 reg = <0x0 0xff650000 0x0 0x1000>;
650                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
651                 #address-cells = <1>;
652                 #size-cells = <0>;
653                 clock-names = "i2c";
654                 clocks = <&cru PCLK_I2C0>;
655                 pinctrl-names = "default";
656                 pinctrl-0 = <&i2c0_xfer>;
657                 status = "disabled";
658         };
659
660         i2c2: i2c@ff660000 {
661                 compatible = "rockchip,rk3288-i2c";
662                 reg = <0x0 0xff660000 0x0 0x1000>;
663                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
664                 #address-cells = <1>;
665                 #size-cells = <0>;
666                 clock-names = "i2c";
667                 clocks = <&cru PCLK_I2C2>;
668                 pinctrl-names = "default";
669                 pinctrl-0 = <&i2c2_xfer>;
670                 status = "disabled";
671         };
672
673         pwm0: pwm@ff680000 {
674                 compatible = "rockchip,rk3288-pwm";
675                 reg = <0x0 0xff680000 0x0 0x10>;
676                 #pwm-cells = <3>;
677                 pinctrl-names = "default";
678                 pinctrl-0 = <&pwm0_pin>;
679                 clocks = <&cru PCLK_PWM>;
680                 clock-names = "pwm";
681                 status = "disabled";
682         };
683
684         pwm1: pwm@ff680010 {
685                 compatible = "rockchip,rk3288-pwm";
686                 reg = <0x0 0xff680010 0x0 0x10>;
687                 #pwm-cells = <3>;
688                 pinctrl-names = "default";
689                 pinctrl-0 = <&pwm1_pin>;
690                 clocks = <&cru PCLK_PWM>;
691                 clock-names = "pwm";
692                 status = "disabled";
693         };
694
695         pwm2: pwm@ff680020 {
696                 compatible = "rockchip,rk3288-pwm";
697                 reg = <0x0 0xff680020 0x0 0x10>;
698                 #pwm-cells = <3>;
699                 pinctrl-names = "default";
700                 pinctrl-0 = <&pwm2_pin>;
701                 clocks = <&cru PCLK_PWM>;
702                 clock-names = "pwm";
703                 status = "disabled";
704         };
705
706         pwm3: pwm@ff680030 {
707                 compatible = "rockchip,rk3288-pwm";
708                 reg = <0x0 0xff680030 0x0 0x10>;
709                 #pwm-cells = <2>;
710                 pinctrl-names = "default";
711                 pinctrl-0 = <&pwm3_pin>;
712                 clocks = <&cru PCLK_PWM>;
713                 clock-names = "pwm";
714                 status = "disabled";
715         };
716
717         bus_intmem@ff700000 {
718                 compatible = "mmio-sram";
719                 reg = <0x0 0xff700000 0x0 0x18000>;
720                 #address-cells = <1>;
721                 #size-cells = <1>;
722                 ranges = <0 0x0 0xff700000 0x18000>;
723                 smp-sram@0 {
724                         compatible = "rockchip,rk3066-smp-sram";
725                         reg = <0x00 0x10>;
726                 };
727         };
728
729         sram@ff720000 {
730                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
731                 reg = <0x0 0xff720000 0x0 0x1000>;
732         };
733
734         pmu: power-management@ff730000 {
735                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
736                 reg = <0x0 0xff730000 0x0 0x100>;
737
738                 power: power-controller {
739                         compatible = "rockchip,rk3288-power-controller";
740                         #power-domain-cells = <1>;
741                         #address-cells = <1>;
742                         #size-cells = <0>;
743
744                         assigned-clocks = <&cru SCLK_EDP_24M>;
745                         assigned-clock-parents = <&xin24m>;
746
747                         /*
748                          * Note: Although SCLK_* are the working clocks
749                          * of device without including on the NOC, needed for
750                          * synchronous reset.
751                          *
752                          * The clocks on the which NOC:
753                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
754                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
755                          * ACLK_RGA is on ACLK_RGA_NIU.
756                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
757                          *
758                          * Which clock are device clocks:
759                          *      clocks          devices
760                          *      *_IEP           IEP:Image Enhancement Processor
761                          *      *_ISP           ISP:Image Signal Processing
762                          *      *_VIP           VIP:Video Input Processor
763                          *      *_VOP*          VOP:Visual Output Processor
764                          *      *_RGA           RGA
765                          *      *_EDP*          EDP
766                          *      *_LVDS_*        LVDS
767                          *      *_HDMI          HDMI
768                          *      *_MIPI_*        MIPI
769                          */
770                         pd_vio@RK3288_PD_VIO {
771                                 reg = <RK3288_PD_VIO>;
772                                 clocks = <&cru ACLK_IEP>,
773                                          <&cru ACLK_ISP>,
774                                          <&cru ACLK_RGA>,
775                                          <&cru ACLK_VIP>,
776                                          <&cru ACLK_VOP0>,
777                                          <&cru ACLK_VOP1>,
778                                          <&cru DCLK_VOP0>,
779                                          <&cru DCLK_VOP1>,
780                                          <&cru HCLK_IEP>,
781                                          <&cru HCLK_ISP>,
782                                          <&cru HCLK_RGA>,
783                                          <&cru HCLK_VIP>,
784                                          <&cru HCLK_VOP0>,
785                                          <&cru HCLK_VOP1>,
786                                          <&cru PCLK_EDP_CTRL>,
787                                          <&cru PCLK_HDMI_CTRL>,
788                                          <&cru PCLK_LVDS_PHY>,
789                                          <&cru PCLK_MIPI_CSI>,
790                                          <&cru PCLK_MIPI_DSI0>,
791                                          <&cru PCLK_MIPI_DSI1>,
792                                          <&cru SCLK_EDP_24M>,
793                                          <&cru SCLK_EDP>,
794                                          <&cru SCLK_ISP_JPE>,
795                                          <&cru SCLK_ISP>,
796                                          <&cru SCLK_RGA>;
797                                 pm_qos = <&qos_vio0_iep>,
798                                          <&qos_vio1_vop>,
799                                          <&qos_vio1_isp_w0>,
800                                          <&qos_vio1_isp_w1>,
801                                          <&qos_vio0_vop>,
802                                          <&qos_vio0_vip>,
803                                          <&qos_vio2_rga_r>,
804                                          <&qos_vio2_rga_w>,
805                                          <&qos_vio1_isp_r>;
806                         };
807
808                         /*
809                          * Note: The following 3 are HEVC(H.265) clocks,
810                          * and on the ACLK_HEVC_NIU (NOC).
811                          */
812                         pd_hevc@RK3288_PD_HEVC {
813                                 reg = <RK3288_PD_HEVC>;
814                                 clocks = <&cru ACLK_HEVC>,
815                                          <&cru SCLK_HEVC_CABAC>,
816                                          <&cru SCLK_HEVC_CORE>;
817                                 pm_qos = <&qos_hevc_r>,
818                                          <&qos_hevc_w>;
819                         };
820
821                         /*
822                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
823                          * (video endecoder & decoder) clocks that on the
824                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
825                          */
826                         pd_video@RK3288_PD_VIDEO {
827                                 reg = <RK3288_PD_VIDEO>;
828                                 clocks = <&cru ACLK_VCODEC>,
829                                          <&cru HCLK_VCODEC>;
830                                 pm_qos = <&qos_video>;
831                         };
832
833                         /*
834                          * Note: ACLK_GPU is the GPU clock,
835                          * and on the ACLK_GPU_NIU (NOC).
836                          */
837                         pd_gpu@RK3288_PD_GPU {
838                                 reg = <RK3288_PD_GPU>;
839                                 clocks = <&cru ACLK_GPU>;
840                                 pm_qos = <&qos_gpu_r>,
841                                          <&qos_gpu_w>;
842                         };
843                 };
844
845                 reboot-mode {
846                         compatible = "syscon-reboot-mode";
847                         offset = <0x94>;
848                         mode-normal = <BOOT_NORMAL>;
849                         mode-recovery = <BOOT_RECOVERY>;
850                         mode-bootloader = <BOOT_FASTBOOT>;
851                         mode-loader = <BOOT_BL_DOWNLOAD>;
852                 };
853         };
854
855         sgrf: syscon@ff740000 {
856                 compatible = "rockchip,rk3288-sgrf", "syscon";
857                 reg = <0x0 0xff740000 0x0 0x1000>;
858         };
859
860         cru: clock-controller@ff760000 {
861                 compatible = "rockchip,rk3288-cru";
862                 reg = <0x0 0xff760000 0x0 0x1000>;
863                 rockchip,grf = <&grf>;
864                 #clock-cells = <1>;
865                 #reset-cells = <1>;
866                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
867                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
868                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
869                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
870                                   <&cru PCLK_PERI>;
871                 assigned-clock-rates = <594000000>, <400000000>,
872                                        <500000000>, <300000000>,
873                                        <150000000>, <75000000>,
874                                        <300000000>, <150000000>,
875                                        <75000000>;
876         };
877
878         grf: syscon@ff770000 {
879                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
880                 reg = <0x0 0xff770000 0x0 0x1000>;
881
882                 edp_phy: edp-phy {
883                         compatible = "rockchip,rk3288-dp-phy";
884                         clocks = <&cru SCLK_EDP_24M>;
885                         clock-names = "24m";
886                         #phy-cells = <0>;
887                         status = "disabled";
888                 };
889
890                 io_domains: io-domains {
891                         compatible = "rockchip,rk3288-io-voltage-domain";
892                         status = "disabled";
893                 };
894
895                 usbphy: usbphy {
896                         compatible = "rockchip,rk3288-usb-phy";
897                         #address-cells = <1>;
898                         #size-cells = <0>;
899                         status = "disabled";
900
901                         usbphy0: usb-phy@320 {
902                                 #phy-cells = <0>;
903                                 reg = <0x320>;
904                                 clocks = <&cru SCLK_OTGPHY0>;
905                                 clock-names = "phyclk";
906                                 #clock-cells = <0>;
907                         };
908
909                         usbphy1: usb-phy@334 {
910                                 #phy-cells = <0>;
911                                 reg = <0x334>;
912                                 clocks = <&cru SCLK_OTGPHY1>;
913                                 clock-names = "phyclk";
914                                 #clock-cells = <0>;
915                         };
916
917                         usbphy2: usb-phy@348 {
918                                 #phy-cells = <0>;
919                                 reg = <0x348>;
920                                 clocks = <&cru SCLK_OTGPHY2>;
921                                 clock-names = "phyclk";
922                                 #clock-cells = <0>;
923                         };
924                 };
925         };
926
927         wdt: watchdog@ff800000 {
928                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
929                 reg = <0x0 0xff800000 0x0 0x100>;
930                 clocks = <&cru PCLK_WDT>;
931                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
932                 status = "disabled";
933         };
934
935         spdif: sound@ff88b0000 {
936                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
937                 reg = <0x0 0xff8b0000 0x0 0x10000>;
938                 #sound-dai-cells = <0>;
939                 clock-names = "hclk", "mclk";
940                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
941                 dmas = <&dmac_bus_s 3>;
942                 dma-names = "tx";
943                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
944                 pinctrl-names = "default";
945                 pinctrl-0 = <&spdif_tx>;
946                 rockchip,grf = <&grf>;
947                 status = "disabled";
948         };
949
950         i2s: i2s@ff890000 {
951                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
952                 reg = <0x0 0xff890000 0x0 0x10000>;
953                 #sound-dai-cells = <0>;
954                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
955                 #address-cells = <1>;
956                 #size-cells = <0>;
957                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
958                 dma-names = "tx", "rx";
959                 clock-names = "i2s_hclk", "i2s_clk";
960                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
961                 pinctrl-names = "default";
962                 pinctrl-0 = <&i2s0_bus>;
963                 rockchip,playback-channels = <8>;
964                 rockchip,capture-channels = <2>;
965                 status = "disabled";
966         };
967
968         crypto: cypto-controller@ff8a0000 {
969                 compatible = "rockchip,rk3288-crypto";
970                 reg = <0x0 0xff8a0000 0x0 0x4000>;
971                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
972                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
973                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
974                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
975                 resets = <&cru SRST_CRYPTO>;
976                 reset-names = "crypto-rst";
977                 status = "okay";
978         };
979
980         iep_mmu: iommu@ff900800 {
981                 compatible = "rockchip,iommu";
982                 reg = <0x0 0xff900800 0x0 0x40>;
983                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
984                 interrupt-names = "iep_mmu";
985                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
986                 clock-names = "aclk", "iface";
987                 #iommu-cells = <0>;
988                 status = "disabled";
989         };
990
991         isp_mmu: iommu@ff914000 {
992                 compatible = "rockchip,iommu";
993                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
994                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
995                 interrupt-names = "isp_mmu";
996                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
997                 clock-names = "aclk", "iface";
998                 #iommu-cells = <0>;
999                 rockchip,disable-mmu-reset;
1000                 status = "disabled";
1001         };
1002
1003         rga: rga@ff920000 {
1004                 compatible = "rockchip,rk3288-rga";
1005                 reg = <0x0 0xff920000 0x0 0x180>;
1006                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1007                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1008                 clock-names = "aclk", "hclk", "sclk";
1009                 power-domains = <&power RK3288_PD_VIO>;
1010                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1011                 reset-names = "core", "axi", "ahb";
1012         };
1013
1014         vopb: vop@ff930000 {
1015                 compatible = "rockchip,rk3288-vop";
1016                 reg = <0x0 0xff930000 0x0 0x19c>;
1017                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1019                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1020                 power-domains = <&power RK3288_PD_VIO>;
1021                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1022                 reset-names = "axi", "ahb", "dclk";
1023                 iommus = <&vopb_mmu>;
1024                 status = "disabled";
1025
1026                 vopb_out: port {
1027                         #address-cells = <1>;
1028                         #size-cells = <0>;
1029
1030                         vopb_out_hdmi: endpoint@0 {
1031                                 reg = <0>;
1032                                 remote-endpoint = <&hdmi_in_vopb>;
1033                         };
1034
1035                         vopb_out_edp: endpoint@1 {
1036                                 reg = <1>;
1037                                 remote-endpoint = <&edp_in_vopb>;
1038                         };
1039
1040                         vopb_out_mipi: endpoint@2 {
1041                                 reg = <2>;
1042                                 remote-endpoint = <&mipi_in_vopb>;
1043                         };
1044
1045                         vopb_out_lvds: endpoint@3 {
1046                                 reg = <3>;
1047                                 remote-endpoint = <&lvds_in_vopb>;
1048                         };
1049                 };
1050         };
1051
1052         vopb_mmu: iommu@ff930300 {
1053                 compatible = "rockchip,iommu";
1054                 reg = <0x0 0xff930300 0x0 0x100>;
1055                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "vopb_mmu";
1057                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1058                 clock-names = "aclk", "iface";
1059                 power-domains = <&power RK3288_PD_VIO>;
1060                 #iommu-cells = <0>;
1061                 status = "disabled";
1062         };
1063
1064         vopl: vop@ff940000 {
1065                 compatible = "rockchip,rk3288-vop";
1066                 reg = <0x0 0xff940000 0x0 0x19c>;
1067                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1068                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1069                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1070                 power-domains = <&power RK3288_PD_VIO>;
1071                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1072                 reset-names = "axi", "ahb", "dclk";
1073                 iommus = <&vopl_mmu>;
1074                 status = "disabled";
1075
1076                 vopl_out: port {
1077                         #address-cells = <1>;
1078                         #size-cells = <0>;
1079
1080                         vopl_out_hdmi: endpoint@0 {
1081                                 reg = <0>;
1082                                 remote-endpoint = <&hdmi_in_vopl>;
1083                         };
1084
1085                         vopl_out_edp: endpoint@1 {
1086                                 reg = <1>;
1087                                 remote-endpoint = <&edp_in_vopl>;
1088                         };
1089
1090                         vopl_out_mipi: endpoint@2 {
1091                                 reg = <2>;
1092                                 remote-endpoint = <&mipi_in_vopl>;
1093                         };
1094
1095                         vopl_out_lvds: endpoint@3 {
1096                                 reg = <3>;
1097                                 remote-endpoint = <&lvds_in_vopl>;
1098                         };
1099                 };
1100         };
1101
1102         vopl_mmu: iommu@ff940300 {
1103                 compatible = "rockchip,iommu";
1104                 reg = <0x0 0xff940300 0x0 0x100>;
1105                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1106                 interrupt-names = "vopl_mmu";
1107                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1108                 clock-names = "aclk", "iface";
1109                 power-domains = <&power RK3288_PD_VIO>;
1110                 #iommu-cells = <0>;
1111                 status = "disabled";
1112         };
1113
1114         mipi_dsi: mipi@ff960000 {
1115                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1116                 reg = <0x0 0xff960000 0x0 0x4000>;
1117                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1118                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1119                 clock-names = "ref", "pclk";
1120                 power-domains = <&power RK3288_PD_VIO>;
1121                 rockchip,grf = <&grf>;
1122                 #address-cells = <1>;
1123                 #size-cells = <0>;
1124                 status = "disabled";
1125
1126                 ports {
1127                         mipi_in: port {
1128                                 #address-cells = <1>;
1129                                 #size-cells = <0>;
1130                                 mipi_in_vopb: endpoint@0 {
1131                                         reg = <0>;
1132                                         remote-endpoint = <&vopb_out_mipi>;
1133                                 };
1134                                 mipi_in_vopl: endpoint@1 {
1135                                         reg = <1>;
1136                                         remote-endpoint = <&vopl_out_mipi>;
1137                                 };
1138                         };
1139                 };
1140         };
1141
1142         lvds: lvds@ff96c000 {
1143                 compatible = "rockchip,rk3288-lvds";
1144                 reg = <0x0 0xff96c000 0x0 0x4000>;
1145                 clocks = <&cru PCLK_LVDS_PHY>;
1146                 clock-names = "pclk_lvds";
1147                 pinctrl-names = "lcdc";
1148                 pinctrl-0 = <&lcdc_ctl>;
1149                 power-domains = <&power RK3288_PD_VIO>;
1150                 rockchip,grf = <&grf>;
1151                 status = "disabled";
1152
1153                 ports {
1154                         #address-cells = <1>;
1155                         #size-cells = <0>;
1156
1157                         lvds_in: port@0 {
1158                                 reg = <0>;
1159
1160                                 #address-cells = <1>;
1161                                 #size-cells = <0>;
1162
1163                                 lvds_in_vopb: endpoint@0 {
1164                                         reg = <0>;
1165                                         remote-endpoint = <&vopb_out_lvds>;
1166                                 };
1167                                 lvds_in_vopl: endpoint@1 {
1168                                         reg = <1>;
1169                                         remote-endpoint = <&vopl_out_lvds>;
1170                                 };
1171                         };
1172                 };
1173         };
1174
1175         edp: dp@ff970000 {
1176                 compatible = "rockchip,rk3288-dp";
1177                 reg = <0x0 0xff970000 0x0 0x4000>;
1178                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1179                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1180                 clock-names = "dp", "pclk";
1181                 phys = <&edp_phy>;
1182                 phy-names = "dp";
1183                 resets = <&cru SRST_EDP>;
1184                 reset-names = "dp";
1185                 rockchip,grf = <&grf>;
1186                 status = "disabled";
1187
1188                 ports {
1189                         #address-cells = <1>;
1190                         #size-cells = <0>;
1191                         edp_in: port@0 {
1192                                 reg = <0>;
1193                                 #address-cells = <1>;
1194                                 #size-cells = <0>;
1195                                 edp_in_vopb: endpoint@0 {
1196                                         reg = <0>;
1197                                         remote-endpoint = <&vopb_out_edp>;
1198                                 };
1199                                 edp_in_vopl: endpoint@1 {
1200                                         reg = <1>;
1201                                         remote-endpoint = <&vopl_out_edp>;
1202                                 };
1203                         };
1204                 };
1205         };
1206
1207         hdmi: hdmi@ff980000 {
1208                 compatible = "rockchip,rk3288-dw-hdmi";
1209                 reg = <0x0 0xff980000 0x0 0x20000>;
1210                 reg-io-width = <4>;
1211                 #sound-dai-cells = <0>;
1212                 rockchip,grf = <&grf>;
1213                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1214                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1215                 clock-names = "iahb", "isfr", "cec";
1216                 power-domains = <&power RK3288_PD_VIO>;
1217                 status = "disabled";
1218
1219                 ports {
1220                         hdmi_in: port {
1221                                 #address-cells = <1>;
1222                                 #size-cells = <0>;
1223                                 hdmi_in_vopb: endpoint@0 {
1224                                         reg = <0>;
1225                                         remote-endpoint = <&vopb_out_hdmi>;
1226                                 };
1227                                 hdmi_in_vopl: endpoint@1 {
1228                                         reg = <1>;
1229                                         remote-endpoint = <&vopl_out_hdmi>;
1230                                 };
1231                         };
1232                 };
1233         };
1234
1235         vpu: video-codec@ff9a0000 {
1236                 compatible = "rockchip,rk3288-vpu";
1237                 reg = <0x0 0xff9a0000 0x0 0x800>;
1238                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1239                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1240                 interrupt-names = "vepu", "vdpu";
1241                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1242                 clock-names = "aclk", "hclk";
1243                 iommus = <&vpu_mmu>;
1244                 power-domains = <&power RK3288_PD_VIDEO>;
1245         };
1246
1247         vpu_mmu: iommu@ff9a0800 {
1248                 compatible = "rockchip,iommu";
1249                 reg = <0x0 0xff9a0800 0x0 0x100>;
1250                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1251                 interrupt-names = "vpu_mmu";
1252                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1253                 clock-names = "aclk", "iface";
1254                 #iommu-cells = <0>;
1255                 power-domains = <&power RK3288_PD_VIDEO>;
1256         };
1257
1258         hevc_mmu: iommu@ff9c0440 {
1259                 compatible = "rockchip,iommu";
1260                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1261                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1262                 interrupt-names = "hevc_mmu";
1263                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1264                 clock-names = "aclk", "iface";
1265                 #iommu-cells = <0>;
1266                 status = "disabled";
1267         };
1268
1269         gpu: gpu@ffa30000 {
1270                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1271                 reg = <0x0 0xffa30000 0x0 0x10000>;
1272                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1273                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1274                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1275                 interrupt-names = "job", "mmu", "gpu";
1276                 clocks = <&cru ACLK_GPU>;
1277                 operating-points-v2 = <&gpu_opp_table>;
1278                 power-domains = <&power RK3288_PD_GPU>;
1279                 status = "disabled";
1280         };
1281
1282         gpu_opp_table: gpu-opp-table {
1283                 compatible = "operating-points-v2";
1284
1285                 opp@100000000 {
1286                         opp-hz = /bits/ 64 <100000000>;
1287                         opp-microvolt = <950000>;
1288                 };
1289                 opp@200000000 {
1290                         opp-hz = /bits/ 64 <200000000>;
1291                         opp-microvolt = <950000>;
1292                 };
1293                 opp@300000000 {
1294                         opp-hz = /bits/ 64 <300000000>;
1295                         opp-microvolt = <1000000>;
1296                 };
1297                 opp@400000000 {
1298                         opp-hz = /bits/ 64 <400000000>;
1299                         opp-microvolt = <1100000>;
1300                 };
1301                 opp@500000000 {
1302                         opp-hz = /bits/ 64 <500000000>;
1303                         opp-microvolt = <1200000>;
1304                 };
1305                 opp@600000000 {
1306                         opp-hz = /bits/ 64 <600000000>;
1307                         opp-microvolt = <1250000>;
1308                 };
1309         };
1310
1311         qos_gpu_r: qos@ffaa0000 {
1312                 compatible = "syscon";
1313                 reg = <0x0 0xffaa0000 0x0 0x20>;
1314         };
1315
1316         qos_gpu_w: qos@ffaa0080 {
1317                 compatible = "syscon";
1318                 reg = <0x0 0xffaa0080 0x0 0x20>;
1319         };
1320
1321         qos_vio1_vop: qos@ffad0000 {
1322                 compatible = "syscon";
1323                 reg = <0x0 0xffad0000 0x0 0x20>;
1324         };
1325
1326         qos_vio1_isp_w0: qos@ffad0100 {
1327                 compatible = "syscon";
1328                 reg = <0x0 0xffad0100 0x0 0x20>;
1329         };
1330
1331         qos_vio1_isp_w1: qos@ffad0180 {
1332                 compatible = "syscon";
1333                 reg = <0x0 0xffad0180 0x0 0x20>;
1334         };
1335
1336         qos_vio0_vop: qos@ffad0400 {
1337                 compatible = "syscon";
1338                 reg = <0x0 0xffad0400 0x0 0x20>;
1339         };
1340
1341         qos_vio0_vip: qos@ffad0480 {
1342                 compatible = "syscon";
1343                 reg = <0x0 0xffad0480 0x0 0x20>;
1344         };
1345
1346         qos_vio0_iep: qos@ffad0500 {
1347                 compatible = "syscon";
1348                 reg = <0x0 0xffad0500 0x0 0x20>;
1349         };
1350
1351         qos_vio2_rga_r: qos@ffad0800 {
1352                 compatible = "syscon";
1353                 reg = <0x0 0xffad0800 0x0 0x20>;
1354         };
1355
1356         qos_vio2_rga_w: qos@ffad0880 {
1357                 compatible = "syscon";
1358                 reg = <0x0 0xffad0880 0x0 0x20>;
1359         };
1360
1361         qos_vio1_isp_r: qos@ffad0900 {
1362                 compatible = "syscon";
1363                 reg = <0x0 0xffad0900 0x0 0x20>;
1364         };
1365
1366         qos_video: qos@ffae0000 {
1367                 compatible = "syscon";
1368                 reg = <0x0 0xffae0000 0x0 0x20>;
1369         };
1370
1371         qos_hevc_r: qos@ffaf0000 {
1372                 compatible = "syscon";
1373                 reg = <0x0 0xffaf0000 0x0 0x20>;
1374         };
1375
1376         qos_hevc_w: qos@ffaf0080 {
1377                 compatible = "syscon";
1378                 reg = <0x0 0xffaf0080 0x0 0x20>;
1379         };
1380
1381         gic: interrupt-controller@ffc01000 {
1382                 compatible = "arm,gic-400";
1383                 interrupt-controller;
1384                 #interrupt-cells = <3>;
1385                 #address-cells = <0>;
1386
1387                 reg = <0x0 0xffc01000 0x0 0x1000>,
1388                       <0x0 0xffc02000 0x0 0x2000>,
1389                       <0x0 0xffc04000 0x0 0x2000>,
1390                       <0x0 0xffc06000 0x0 0x2000>;
1391                 interrupts = <GIC_PPI 9 0xf04>;
1392         };
1393
1394         efuse: efuse@ffb40000 {
1395                 compatible = "rockchip,rk3288-efuse";
1396                 reg = <0x0 0xffb40000 0x0 0x20>;
1397                 #address-cells = <1>;
1398                 #size-cells = <1>;
1399                 clocks = <&cru PCLK_EFUSE256>;
1400                 clock-names = "pclk_efuse";
1401
1402                 cpu_leakage: cpu_leakage@17 {
1403                         reg = <0x17 0x1>;
1404                 };
1405         };
1406
1407         pinctrl: pinctrl {
1408                 compatible = "rockchip,rk3288-pinctrl";
1409                 rockchip,grf = <&grf>;
1410                 rockchip,pmu = <&pmu>;
1411                 #address-cells = <2>;
1412                 #size-cells = <2>;
1413                 ranges;
1414
1415                 gpio0: gpio0@ff750000 {
1416                         compatible = "rockchip,gpio-bank";
1417                         reg = <0x0 0xff750000 0x0 0x100>;
1418                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1419                         clocks = <&cru PCLK_GPIO0>;
1420
1421                         gpio-controller;
1422                         #gpio-cells = <2>;
1423
1424                         interrupt-controller;
1425                         #interrupt-cells = <2>;
1426                 };
1427
1428                 gpio1: gpio1@ff780000 {
1429                         compatible = "rockchip,gpio-bank";
1430                         reg = <0x0 0xff780000 0x0 0x100>;
1431                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1432                         clocks = <&cru PCLK_GPIO1>;
1433
1434                         gpio-controller;
1435                         #gpio-cells = <2>;
1436
1437                         interrupt-controller;
1438                         #interrupt-cells = <2>;
1439                 };
1440
1441                 gpio2: gpio2@ff790000 {
1442                         compatible = "rockchip,gpio-bank";
1443                         reg = <0x0 0xff790000 0x0 0x100>;
1444                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1445                         clocks = <&cru PCLK_GPIO2>;
1446
1447                         gpio-controller;
1448                         #gpio-cells = <2>;
1449
1450                         interrupt-controller;
1451                         #interrupt-cells = <2>;
1452                 };
1453
1454                 gpio3: gpio3@ff7a0000 {
1455                         compatible = "rockchip,gpio-bank";
1456                         reg = <0x0 0xff7a0000 0x0 0x100>;
1457                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1458                         clocks = <&cru PCLK_GPIO3>;
1459
1460                         gpio-controller;
1461                         #gpio-cells = <2>;
1462
1463                         interrupt-controller;
1464                         #interrupt-cells = <2>;
1465                 };
1466
1467                 gpio4: gpio4@ff7b0000 {
1468                         compatible = "rockchip,gpio-bank";
1469                         reg = <0x0 0xff7b0000 0x0 0x100>;
1470                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1471                         clocks = <&cru PCLK_GPIO4>;
1472
1473                         gpio-controller;
1474                         #gpio-cells = <2>;
1475
1476                         interrupt-controller;
1477                         #interrupt-cells = <2>;
1478                 };
1479
1480                 gpio5: gpio5@ff7c0000 {
1481                         compatible = "rockchip,gpio-bank";
1482                         reg = <0x0 0xff7c0000 0x0 0x100>;
1483                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1484                         clocks = <&cru PCLK_GPIO5>;
1485
1486                         gpio-controller;
1487                         #gpio-cells = <2>;
1488
1489                         interrupt-controller;
1490                         #interrupt-cells = <2>;
1491                 };
1492
1493                 gpio6: gpio6@ff7d0000 {
1494                         compatible = "rockchip,gpio-bank";
1495                         reg = <0x0 0xff7d0000 0x0 0x100>;
1496                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1497                         clocks = <&cru PCLK_GPIO6>;
1498
1499                         gpio-controller;
1500                         #gpio-cells = <2>;
1501
1502                         interrupt-controller;
1503                         #interrupt-cells = <2>;
1504                 };
1505
1506                 gpio7: gpio7@ff7e0000 {
1507                         compatible = "rockchip,gpio-bank";
1508                         reg = <0x0 0xff7e0000 0x0 0x100>;
1509                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1510                         clocks = <&cru PCLK_GPIO7>;
1511
1512                         gpio-controller;
1513                         #gpio-cells = <2>;
1514
1515                         interrupt-controller;
1516                         #interrupt-cells = <2>;
1517                 };
1518
1519                 gpio8: gpio8@ff7f0000 {
1520                         compatible = "rockchip,gpio-bank";
1521                         reg = <0x0 0xff7f0000 0x0 0x100>;
1522                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1523                         clocks = <&cru PCLK_GPIO8>;
1524
1525                         gpio-controller;
1526                         #gpio-cells = <2>;
1527
1528                         interrupt-controller;
1529                         #interrupt-cells = <2>;
1530                 };
1531
1532                 hdmi {
1533                         hdmi_cec_c0: hdmi-cec-c0 {
1534                                 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1535                         };
1536
1537                         hdmi_cec_c7: hdmi-cec-c7 {
1538                                 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
1539                         };
1540
1541                         hdmi_ddc: hdmi-ddc {
1542                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1543                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1544                         };
1545                 };
1546
1547                 pcfg_pull_up: pcfg-pull-up {
1548                         bias-pull-up;
1549                 };
1550
1551                 pcfg_pull_down: pcfg-pull-down {
1552                         bias-pull-down;
1553                 };
1554
1555                 pcfg_pull_none: pcfg-pull-none {
1556                         bias-disable;
1557                 };
1558
1559                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1560                         bias-disable;
1561                         drive-strength = <12>;
1562                 };
1563
1564                 sleep {
1565                         global_pwroff: global-pwroff {
1566                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1567                         };
1568
1569                         ddrio_pwroff: ddrio-pwroff {
1570                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1571                         };
1572
1573                         ddr0_retention: ddr0-retention {
1574                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1575                         };
1576
1577                         ddr1_retention: ddr1-retention {
1578                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1579                         };
1580                 };
1581
1582                 edp {
1583                         edp_hpd: edp-hpd {
1584                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1585                         };
1586                 };
1587
1588                 i2c0 {
1589                         i2c0_xfer: i2c0-xfer {
1590                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1591                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1592                         };
1593                 };
1594
1595                 i2c1 {
1596                         i2c1_xfer: i2c1-xfer {
1597                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1598                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1599                         };
1600                 };
1601
1602                 i2c2 {
1603                         i2c2_xfer: i2c2-xfer {
1604                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1605                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1606                         };
1607                 };
1608
1609                 i2c3 {
1610                         i2c3_xfer: i2c3-xfer {
1611                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1612                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1613                         };
1614                 };
1615
1616                 i2c4 {
1617                         i2c4_xfer: i2c4-xfer {
1618                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1619                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1620                         };
1621                 };
1622
1623                 i2c5 {
1624                         i2c5_xfer: i2c5-xfer {
1625                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1626                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1627                         };
1628                 };
1629
1630                 i2s0 {
1631                         i2s0_bus: i2s0-bus {
1632                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1633                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1634                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1635                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1636                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1637                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1638                         };
1639                 };
1640
1641                 lcdc {
1642                         lcdc_ctl: lcdc-ctl {
1643                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1644                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1645                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1646                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 sdmmc {
1651                         sdmmc_clk: sdmmc-clk {
1652                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1653                         };
1654
1655                         sdmmc_cmd: sdmmc-cmd {
1656                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1657                         };
1658
1659                         sdmmc_cd: sdmmc-cd {
1660                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1661                         };
1662
1663                         sdmmc_bus1: sdmmc-bus1 {
1664                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1665                         };
1666
1667                         sdmmc_bus4: sdmmc-bus4 {
1668                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1669                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1670                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1671                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1672                         };
1673                 };
1674
1675                 sdio0 {
1676                         sdio0_bus1: sdio0-bus1 {
1677                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1678                         };
1679
1680                         sdio0_bus4: sdio0-bus4 {
1681                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1682                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1683                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1684                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1685                         };
1686
1687                         sdio0_cmd: sdio0-cmd {
1688                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1689                         };
1690
1691                         sdio0_clk: sdio0-clk {
1692                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1693                         };
1694
1695                         sdio0_cd: sdio0-cd {
1696                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1697                         };
1698
1699                         sdio0_wp: sdio0-wp {
1700                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1701                         };
1702
1703                         sdio0_pwr: sdio0-pwr {
1704                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1705                         };
1706
1707                         sdio0_bkpwr: sdio0-bkpwr {
1708                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1709                         };
1710
1711                         sdio0_int: sdio0-int {
1712                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1713                         };
1714                 };
1715
1716                 sdio1 {
1717                         sdio1_bus1: sdio1-bus1 {
1718                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1719                         };
1720
1721                         sdio1_bus4: sdio1-bus4 {
1722                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1723                                                 <3 25 4 &pcfg_pull_up>,
1724                                                 <3 26 4 &pcfg_pull_up>,
1725                                                 <3 27 4 &pcfg_pull_up>;
1726                         };
1727
1728                         sdio1_cd: sdio1-cd {
1729                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1730                         };
1731
1732                         sdio1_wp: sdio1-wp {
1733                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1734                         };
1735
1736                         sdio1_bkpwr: sdio1-bkpwr {
1737                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1738                         };
1739
1740                         sdio1_int: sdio1-int {
1741                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1742                         };
1743
1744                         sdio1_cmd: sdio1-cmd {
1745                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1746                         };
1747
1748                         sdio1_clk: sdio1-clk {
1749                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1750                         };
1751
1752                         sdio1_pwr: sdio1-pwr {
1753                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1754                         };
1755                 };
1756
1757                 emmc {
1758                         emmc_clk: emmc-clk {
1759                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1760                         };
1761
1762                         emmc_cmd: emmc-cmd {
1763                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1764                         };
1765
1766                         emmc_pwr: emmc-pwr {
1767                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1768                         };
1769
1770                         emmc_bus1: emmc-bus1 {
1771                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1772                         };
1773
1774                         emmc_bus4: emmc-bus4 {
1775                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1776                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1777                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1778                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1779                         };
1780
1781                         emmc_bus8: emmc-bus8 {
1782                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1783                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1784                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1785                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1786                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1787                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1788                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1789                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1790                         };
1791                 };
1792
1793                 spi0 {
1794                         spi0_clk: spi0-clk {
1795                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797                         spi0_cs0: spi0-cs0 {
1798                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1799                         };
1800                         spi0_tx: spi0-tx {
1801                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1802                         };
1803                         spi0_rx: spi0-rx {
1804                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806                         spi0_cs1: spi0-cs1 {
1807                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1808                         };
1809                 };
1810                 spi1 {
1811                         spi1_clk: spi1-clk {
1812                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1813                         };
1814                         spi1_cs0: spi1-cs0 {
1815                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1816                         };
1817                         spi1_rx: spi1-rx {
1818                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1819                         };
1820                         spi1_tx: spi1-tx {
1821                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1822                         };
1823                 };
1824
1825                 spi2 {
1826                         spi2_cs1: spi2-cs1 {
1827                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1828                         };
1829                         spi2_clk: spi2-clk {
1830                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1831                         };
1832                         spi2_cs0: spi2-cs0 {
1833                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1834                         };
1835                         spi2_rx: spi2-rx {
1836                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1837                         };
1838                         spi2_tx: spi2-tx {
1839                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1840                         };
1841                 };
1842
1843                 uart0 {
1844                         uart0_xfer: uart0-xfer {
1845                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1846                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1847                         };
1848
1849                         uart0_cts: uart0-cts {
1850                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852
1853                         uart0_rts: uart0-rts {
1854                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1855                         };
1856                 };
1857
1858                 uart1 {
1859                         uart1_xfer: uart1-xfer {
1860                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1861                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1862                         };
1863
1864                         uart1_cts: uart1-cts {
1865                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1866                         };
1867
1868                         uart1_rts: uart1-rts {
1869                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1870                         };
1871                 };
1872
1873                 uart2 {
1874                         uart2_xfer: uart2-xfer {
1875                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1876                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1877                         };
1878                         /* no rts / cts for uart2 */
1879                 };
1880
1881                 uart3 {
1882                         uart3_xfer: uart3-xfer {
1883                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1884                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1885                         };
1886
1887                         uart3_cts: uart3-cts {
1888                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1889                         };
1890
1891                         uart3_rts: uart3-rts {
1892                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1893                         };
1894                 };
1895
1896                 uart4 {
1897                         uart4_xfer: uart4-xfer {
1898                                 rockchip,pins = <5 15 3 &pcfg_pull_up>,
1899                                                 <5 14 3 &pcfg_pull_none>;
1900                         };
1901
1902                         uart4_cts: uart4-cts {
1903                                 rockchip,pins = <5 12 3 &pcfg_pull_up>;
1904                         };
1905
1906                         uart4_rts: uart4-rts {
1907                                 rockchip,pins = <5 13 3 &pcfg_pull_none>;
1908                         };
1909                 };
1910
1911                 tsadc {
1912                         otp_gpio: otp-gpio {
1913                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1914                         };
1915
1916                         otp_out: otp-out {
1917                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1918                         };
1919                 };
1920
1921                 pwm0 {
1922                         pwm0_pin: pwm0-pin {
1923                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1924                         };
1925                 };
1926
1927                 pwm1 {
1928                         pwm1_pin: pwm1-pin {
1929                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1930                         };
1931                 };
1932
1933                 pwm2 {
1934                         pwm2_pin: pwm2-pin {
1935                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1936                         };
1937                 };
1938
1939                 pwm3 {
1940                         pwm3_pin: pwm3-pin {
1941                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1942                         };
1943                 };
1944
1945                 gmac {
1946                         rgmii_pins: rgmii-pins {
1947                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1948                                                 <3 31 3 &pcfg_pull_none>,
1949                                                 <3 26 3 &pcfg_pull_none>,
1950                                                 <3 27 3 &pcfg_pull_none>,
1951                                                 <3 28 3 &pcfg_pull_none_12ma>,
1952                                                 <3 29 3 &pcfg_pull_none_12ma>,
1953                                                 <3 24 3 &pcfg_pull_none_12ma>,
1954                                                 <3 25 3 &pcfg_pull_none_12ma>,
1955                                                 <4 0 3 &pcfg_pull_none>,
1956                                                 <4 5 3 &pcfg_pull_none>,
1957                                                 <4 6 3 &pcfg_pull_none>,
1958                                                 <4 9 3 &pcfg_pull_none_12ma>,
1959                                                 <4 4 3 &pcfg_pull_none_12ma>,
1960                                                 <4 1 3 &pcfg_pull_none>,
1961                                                 <4 3 3 &pcfg_pull_none>;
1962                         };
1963
1964                         rmii_pins: rmii-pins {
1965                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1966                                                 <3 31 3 &pcfg_pull_none>,
1967                                                 <3 28 3 &pcfg_pull_none>,
1968                                                 <3 29 3 &pcfg_pull_none>,
1969                                                 <4 0 3 &pcfg_pull_none>,
1970                                                 <4 5 3 &pcfg_pull_none>,
1971                                                 <4 4 3 &pcfg_pull_none>,
1972                                                 <4 1 3 &pcfg_pull_none>,
1973                                                 <4 2 3 &pcfg_pull_none>,
1974                                                 <4 3 3 &pcfg_pull_none>;
1975                         };
1976                 };
1977
1978                 spdif {
1979                         spdif_tx: spdif-tx {
1980                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1981                         };
1982                 };
1983         };
1984 };