Merge tag 'v4.21-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[muen/linux.git] / arch / arm / boot / dts / rv1108.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
9 / {
10         #address-cells = <1>;
11         #size-cells = <1>;
12
13         compatible = "rockchip,rv1108";
14
15         interrupt-parent = <&gic>;
16
17         aliases {
18                 i2c0 = &i2c0;
19                 i2c1 = &i2c1;
20                 i2c2 = &i2c2;
21                 i2c3 = &i2c3;
22                 serial0 = &uart0;
23                 serial1 = &uart1;
24                 serial2 = &uart2;
25         };
26
27         cpus {
28                 #address-cells = <1>;
29                 #size-cells = <0>;
30
31                 cpu0: cpu@f00 {
32                         device_type = "cpu";
33                         compatible = "arm,cortex-a7";
34                         reg = <0xf00>;
35                         clock-latency = <40000>;
36                         clocks = <&cru ARMCLK>;
37                         #cooling-cells = <2>; /* min followed by max */
38                         dynamic-power-coefficient = <75>;
39                         operating-points-v2 = <&cpu_opp_table>;
40                 };
41         };
42
43         cpu_opp_table: opp_table {
44                 compatible = "operating-points-v2";
45
46                 opp-408000000 {
47                         opp-hz = /bits/ 64 <408000000>;
48                         opp-microvolt = <975000>;
49                         clock-latency-ns = <40000>;
50                 };
51                 opp-600000000 {
52                         opp-hz = /bits/ 64 <600000000>;
53                         opp-microvolt = <975000>;
54                         clock-latency-ns = <40000>;
55                 };
56                 opp-816000000 {
57                         opp-hz = /bits/ 64 <816000000>;
58                         opp-microvolt = <1025000>;
59                         clock-latency-ns = <40000>;
60                 };
61                 opp-1008000000 {
62                         opp-hz = /bits/ 64 <1008000000>;
63                         opp-microvolt = <1150000>;
64                         clock-latency-ns = <40000>;
65                 };
66         };
67
68         arm-pmu {
69                 compatible = "arm,cortex-a7-pmu";
70                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
71         };
72
73         timer {
74                 compatible = "arm,armv7-timer";
75                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77                 arm,cpu-registers-not-fw-configured;
78                 clock-frequency = <24000000>;
79         };
80
81         xin24m: oscillator {
82                 compatible = "fixed-clock";
83                 clock-frequency = <24000000>;
84                 clock-output-names = "xin24m";
85                 #clock-cells = <0>;
86         };
87
88         amba {
89                 compatible = "simple-bus";
90                 #address-cells = <1>;
91                 #size-cells = <1>;
92                 ranges;
93
94                 pdma: pdma@102a0000 {
95                         compatible = "arm,pl330", "arm,primecell";
96                         reg = <0x102a0000 0x4000>;
97                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
98                         #dma-cells = <1>;
99                         arm,pl330-broken-no-flushp;
100                         clocks = <&cru ACLK_DMAC>;
101                         clock-names = "apb_pclk";
102                 };
103         };
104
105         bus_intmem@10080000 {
106                 compatible = "mmio-sram";
107                 reg = <0x10080000 0x2000>;
108                 #address-cells = <1>;
109                 #size-cells = <1>;
110                 ranges = <0 0x10080000 0x2000>;
111         };
112
113         uart2: serial@10210000 {
114                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
115                 reg = <0x10210000 0x100>;
116                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
117                 reg-shift = <2>;
118                 reg-io-width = <4>;
119                 clock-frequency = <24000000>;
120                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
121                 clock-names = "baudclk", "apb_pclk";
122                 dmas = <&pdma 6>, <&pdma 7>;
123                 #dma-cells = <2>;
124                 pinctrl-names = "default";
125                 pinctrl-0 = <&uart2m0_xfer>;
126                 status = "disabled";
127         };
128
129         uart1: serial@10220000 {
130                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
131                 reg = <0x10220000 0x100>;
132                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
133                 reg-shift = <2>;
134                 reg-io-width = <4>;
135                 clock-frequency = <24000000>;
136                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137                 clock-names = "baudclk", "apb_pclk";
138                 dmas = <&pdma 4>, <&pdma 5>;
139                 #dma-cells = <2>;
140                 pinctrl-names = "default";
141                 pinctrl-0 = <&uart1_xfer>;
142                 status = "disabled";
143         };
144
145         uart0: serial@10230000 {
146                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
147                 reg = <0x10230000 0x100>;
148                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
149                 reg-shift = <2>;
150                 reg-io-width = <4>;
151                 clock-frequency = <24000000>;
152                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
153                 clock-names = "baudclk", "apb_pclk";
154                 dmas = <&pdma 2>, <&pdma 3>;
155                 #dma-cells = <2>;
156                 pinctrl-names = "default";
157                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
158                 status = "disabled";
159         };
160
161         i2c1: i2c@10240000 {
162                 compatible = "rockchip,rv1108-i2c";
163                 reg = <0x10240000 0x1000>;
164                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
165                 #address-cells = <1>;
166                 #size-cells = <0>;
167                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
168                 clock-names = "i2c", "pclk";
169                 pinctrl-names = "default";
170                 pinctrl-0 = <&i2c1_xfer>;
171                 rockchip,grf = <&grf>;
172                 status = "disabled";
173         };
174
175         i2c2: i2c@10250000 {
176                 compatible = "rockchip,rv1108-i2c";
177                 reg = <0x10250000 0x1000>;
178                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
179                 #address-cells = <1>;
180                 #size-cells = <0>;
181                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
182                 clock-names = "i2c", "pclk";
183                 pinctrl-names = "default";
184                 pinctrl-0 = <&i2c2m1_xfer>;
185                 rockchip,grf = <&grf>;
186                 status = "disabled";
187         };
188
189         i2c3: i2c@10260000 {
190                 compatible = "rockchip,rv1108-i2c";
191                 reg = <0x10260000 0x1000>;
192                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
193                 #address-cells = <1>;
194                 #size-cells = <0>;
195                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
196                 clock-names = "i2c", "pclk";
197                 pinctrl-names = "default";
198                 pinctrl-0 = <&i2c3_xfer>;
199                 rockchip,grf = <&grf>;
200                 status = "disabled";
201         };
202
203         spi: spi@10270000 {
204                 compatible = "rockchip,rv1108-spi";
205                 reg = <0x10270000 0x1000>;
206                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
207                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
208                 clock-names = "spiclk", "apb_pclk";
209                 dmas = <&pdma 8>, <&pdma 9>;
210                 #dma-cells = <2>;
211                 #address-cells = <1>;
212                 #size-cells = <0>;
213                 status = "disabled";
214         };
215
216         pwm4: pwm@10280000 {
217                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
218                 reg = <0x10280000 0x10>;
219                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
220                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
221                 clock-names = "pwm", "pclk";
222                 pinctrl-names = "default";
223                 pinctrl-0 = <&pwm4_pin>;
224                 #pwm-cells = <3>;
225                 status = "disabled";
226         };
227
228         pwm5: pwm@10280010 {
229                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
230                 reg = <0x10280010 0x10>;
231                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
232                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
233                 clock-names = "pwm", "pclk";
234                 pinctrl-names = "default";
235                 pinctrl-0 = <&pwm5_pin>;
236                 #pwm-cells = <3>;
237                 status = "disabled";
238         };
239
240         pwm6: pwm@10280020 {
241                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
242                 reg = <0x10280020 0x10>;
243                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
244                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
245                 clock-names = "pwm", "pclk";
246                 pinctrl-names = "default";
247                 pinctrl-0 = <&pwm6_pin>;
248                 #pwm-cells = <3>;
249                 status = "disabled";
250         };
251
252         pwm7: pwm@10280030 {
253                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
254                 reg = <0x10280030 0x10>;
255                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
256                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
257                 clock-names = "pwm", "pclk";
258                 pinctrl-names = "default";
259                 pinctrl-0 = <&pwm7_pin>;
260                 #pwm-cells = <3>;
261                 status = "disabled";
262         };
263
264         grf: syscon@10300000 {
265                 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
266                 reg = <0x10300000 0x1000>;
267                 #address-cells = <1>;
268                 #size-cells = <1>;
269
270                 u2phy: usb2-phy@100 {
271                         compatible = "rockchip,rv1108-usb2phy";
272                         reg = <0x100 0x0c>;
273                         clocks = <&cru SCLK_USBPHY>;
274                         clock-names = "phyclk";
275                         #clock-cells = <0>;
276                         clock-output-names = "usbphy";
277                         rockchip,usbgrf = <&usbgrf>;
278                         status = "disabled";
279
280                         u2phy_otg: otg-port {
281                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
282                                 interrupt-names = "otg-mux";
283                                 #phy-cells = <0>;
284                                 status = "disabled";
285                         };
286
287                         u2phy_host: host-port {
288                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
289                                 interrupt-names = "linestate";
290                                 #phy-cells = <0>;
291                                 status = "disabled";
292                         };
293                 };
294         };
295
296         timer: timer@10350000 {
297                 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
298                 reg = <0x10350000 0x20>;
299                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
300                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
301                 clock-names = "timer", "pclk";
302         };
303
304         watchdog: wdt@10360000 {
305                 compatible = "snps,dw-wdt";
306                 reg = <0x10360000 0x100>;
307                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
308                 clocks = <&cru PCLK_WDT>;
309                 clock-names = "pclk_wdt";
310                 status = "disabled";
311         };
312
313         thermal-zones {
314                 soc_thermal: soc-thermal {
315                         polling-delay-passive = <20>;
316                         polling-delay = <1000>;
317                         sustainable-power = <50>;
318                         thermal-sensors = <&tsadc 0>;
319
320                         trips {
321                                 threshold: trip-point0 {
322                                         temperature = <70000>;
323                                         hysteresis = <2000>;
324                                         type = "passive";
325                                 };
326                                 target: trip-point1 {
327                                         temperature = <85000>;
328                                         hysteresis = <2000>;
329                                         type = "passive";
330                                 };
331                                 soc_crit: soc-crit {
332                                         temperature = <95000>;
333                                         hysteresis = <2000>;
334                                         type = "critical";
335                                 };
336                         };
337
338                         cooling-maps {
339                                 map0 {
340                                         trip = <&target>;
341                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
342                                         contribution = <4096>;
343                                 };
344                         };
345                 };
346         };
347
348         tsadc: tsadc@10370000 {
349                 compatible = "rockchip,rv1108-tsadc";
350                 reg = <0x10370000 0x100>;
351                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
352                 assigned-clocks = <&cru SCLK_TSADC>;
353                 assigned-clock-rates = <750000>;
354                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
355                 clock-names = "tsadc", "apb_pclk";
356                 pinctrl-names = "init", "default", "sleep";
357                 pinctrl-0 = <&otp_gpio>;
358                 pinctrl-1 = <&otp_out>;
359                 pinctrl-2 = <&otp_gpio>;
360                 resets = <&cru SRST_TSADC>;
361                 reset-names = "tsadc-apb";
362                 rockchip,hw-tshut-temp = <120000>;
363                 #thermal-sensor-cells = <1>;
364                 status = "disabled";
365         };
366
367         adc: adc@1038c000 {
368                 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
369                 reg = <0x1038c000 0x100>;
370                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
371                 #io-channel-cells = <1>;
372                 clock-frequency = <1000000>;
373                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
374                 clock-names = "saradc", "apb_pclk";
375                 status = "disabled";
376         };
377
378         i2c0: i2c@20000000 {
379                 compatible = "rockchip,rv1108-i2c";
380                 reg = <0x20000000 0x1000>;
381                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
382                 #address-cells = <1>;
383                 #size-cells = <0>;
384                 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
385                 clock-names = "i2c", "pclk";
386                 pinctrl-names = "default";
387                 pinctrl-0 = <&i2c0_xfer>;
388                 rockchip,grf = <&grf>;
389                 status = "disabled";
390         };
391
392         pwm0: pwm@20040000 {
393                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
394                 reg = <0x20040000 0x10>;
395                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
396                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
397                 clock-names = "pwm", "pclk";
398                 pinctrl-names = "default";
399                 pinctrl-0 = <&pwm0_pin>;
400                 #pwm-cells = <3>;
401                 status = "disabled";
402         };
403
404         pwm1: pwm@20040010 {
405                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
406                 reg = <0x20040010 0x10>;
407                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
408                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
409                 clock-names = "pwm", "pclk";
410                 pinctrl-names = "default";
411                 pinctrl-0 = <&pwm1_pin>;
412                 #pwm-cells = <3>;
413                 status = "disabled";
414         };
415
416         pwm2: pwm@20040020 {
417                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
418                 reg = <0x20040020 0x10>;
419                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
420                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
421                 clock-names = "pwm", "pclk";
422                 pinctrl-names = "default";
423                 pinctrl-0 = <&pwm2_pin>;
424                 #pwm-cells = <3>;
425                 status = "disabled";
426         };
427
428         pwm3: pwm@20040030 {
429                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
430                 reg = <0x20040030 0x10>;
431                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
432                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
433                 clock-names = "pwm", "pclk";
434                 pinctrl-names = "default";
435                 pinctrl-0 = <&pwm3_pin>;
436                 #pwm-cells = <3>;
437                 status = "disabled";
438         };
439
440         pmugrf: syscon@20060000 {
441                 compatible = "rockchip,rv1108-pmugrf", "syscon";
442                 reg = <0x20060000 0x1000>;
443         };
444
445         usbgrf: syscon@202a0000 {
446                 compatible = "rockchip,rv1108-usbgrf", "syscon";
447                 reg = <0x202a0000 0x1000>;
448         };
449
450         cru: clock-controller@20200000 {
451                 compatible = "rockchip,rv1108-cru";
452                 reg = <0x20200000 0x1000>;
453                 rockchip,grf = <&grf>;
454                 #clock-cells = <1>;
455                 #reset-cells = <1>;
456         };
457
458         emmc: dwmmc@30110000 {
459                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
460                 reg = <0x30110000 0x4000>;
461                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
462                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
463                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
464                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
465                 fifo-depth = <0x100>;
466                 max-frequency = <150000000>;
467                 status = "disabled";
468         };
469
470         sdio: dwmmc@30120000 {
471                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
472                 reg = <0x30120000 0x4000>;
473                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
474                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
475                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
476                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
477                 fifo-depth = <0x100>;
478                 max-frequency = <150000000>;
479                 status = "disabled";
480         };
481
482         sdmmc: dwmmc@30130000 {
483                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
484                 reg = <0x30130000 0x4000>;
485                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
486                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
487                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
488                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
489                 fifo-depth = <0x100>;
490                 max-frequency = <100000000>;
491                 pinctrl-names = "default";
492                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
493                 status = "disabled";
494         };
495
496         usb_host_ehci: usb@30140000 {
497                 compatible = "generic-ehci";
498                 reg = <0x30140000 0x20000>;
499                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
500                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
501                 clock-names = "usbhost", "utmi";
502                 phys = <&u2phy_host>;
503                 phy-names = "usb";
504                 status = "disabled";
505         };
506
507         usb_host_ohci: usb@30160000 {
508                 compatible = "generic-ohci";
509                 reg = <0x30160000 0x20000>;
510                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
511                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
512                 clock-names = "usbhost", "utmi";
513                 phys = <&u2phy_host>;
514                 phy-names = "usb";
515                 status = "disabled";
516         };
517
518         usb_otg: usb@30180000 {
519                 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
520                              "snps,dwc2";
521                 reg = <0x30180000 0x40000>;
522                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
523                 clocks = <&cru HCLK_OTG>;
524                 clock-names = "otg";
525                 dr_mode = "otg";
526                 g-np-tx-fifo-size = <16>;
527                 g-rx-fifo-size = <280>;
528                 g-tx-fifo-size = <256 128 128 64 32 16>;
529                 g-use-dma;
530                 phys = <&u2phy_otg>;
531                 phy-names = "usb2-phy";
532                 status = "disabled";
533         };
534
535         gmac: eth@30200000 {
536                 compatible = "rockchip,rv1108-gmac";
537                 reg = <0x30200000 0x10000>;
538                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
539                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
540                 interrupt-names = "macirq", "eth_wake_irq";
541                 clocks = <&cru SCLK_MAC>,
542                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
543                         <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
544                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
545                 clock-names = "stmmaceth",
546                         "mac_clk_rx", "mac_clk_tx",
547                         "clk_mac_ref", "clk_mac_refout",
548                         "aclk_mac", "pclk_mac";
549                 /* rv1108 only supports an rmii interface */
550                 phy-mode = "rmii";
551                 pinctrl-names = "default";
552                 pinctrl-0 = <&rmii_pins>;
553                 rockchip,grf = <&grf>;
554                 status = "disabled";
555         };
556
557         gic: interrupt-controller@32010000 {
558                 compatible = "arm,gic-400";
559                 interrupt-controller;
560                 #interrupt-cells = <3>;
561                 #address-cells = <0>;
562
563                 reg = <0x32011000 0x1000>,
564                       <0x32012000 0x2000>,
565                       <0x32014000 0x2000>,
566                       <0x32016000 0x2000>;
567                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
568         };
569
570         pinctrl: pinctrl {
571                 compatible = "rockchip,rv1108-pinctrl";
572                 rockchip,grf = <&grf>;
573                 rockchip,pmu = <&pmugrf>;
574                 #address-cells = <1>;
575                 #size-cells = <1>;
576                 ranges;
577
578                 gpio0: gpio0@20030000 {
579                         compatible = "rockchip,gpio-bank";
580                         reg = <0x20030000 0x100>;
581                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
582                         clocks = <&cru PCLK_GPIO0_PMU>;
583
584                         gpio-controller;
585                         #gpio-cells = <2>;
586
587                         interrupt-controller;
588                         #interrupt-cells = <2>;
589                 };
590
591                 gpio1: gpio1@10310000 {
592                         compatible = "rockchip,gpio-bank";
593                         reg = <0x10310000 0x100>;
594                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
595                         clocks = <&cru PCLK_GPIO1>;
596
597                         gpio-controller;
598                         #gpio-cells = <2>;
599
600                         interrupt-controller;
601                         #interrupt-cells = <2>;
602                 };
603
604                 gpio2: gpio2@10320000 {
605                         compatible = "rockchip,gpio-bank";
606                         reg = <0x10320000 0x100>;
607                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
608                         clocks = <&cru PCLK_GPIO2>;
609
610                         gpio-controller;
611                         #gpio-cells = <2>;
612
613                         interrupt-controller;
614                         #interrupt-cells = <2>;
615                 };
616
617                 gpio3: gpio3@10330000 {
618                         compatible = "rockchip,gpio-bank";
619                         reg = <0x10330000 0x100>;
620                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
621                         clocks = <&cru PCLK_GPIO3>;
622
623                         gpio-controller;
624                         #gpio-cells = <2>;
625
626                         interrupt-controller;
627                         #interrupt-cells = <2>;
628                 };
629
630                 pcfg_pull_up: pcfg-pull-up {
631                         bias-pull-up;
632                 };
633
634                 pcfg_pull_down: pcfg-pull-down {
635                         bias-pull-down;
636                 };
637
638                 pcfg_pull_none: pcfg-pull-none {
639                         bias-disable;
640                 };
641
642                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
643                         drive-strength = <8>;
644                 };
645
646                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
647                         drive-strength = <12>;
648                 };
649
650                 pcfg_pull_none_smt: pcfg-pull-none-smt {
651                         bias-disable;
652                         input-schmitt-enable;
653                 };
654
655                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
656                         bias-pull-up;
657                         drive-strength = <8>;
658                 };
659
660                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
661                         drive-strength = <4>;
662                 };
663
664                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
665                         bias-pull-up;
666                         drive-strength = <4>;
667                 };
668
669                 pcfg_output_high: pcfg-output-high {
670                         output-high;
671                 };
672
673                 pcfg_output_low: pcfg-output-low {
674                         output-low;
675                 };
676
677                 pcfg_input_high: pcfg-input-high {
678                         bias-pull-up;
679                         input-enable;
680                 };
681
682                 emmc {
683                         emmc_bus8: emmc-bus8 {
684                                 rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
685                                                 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
686                                                 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
687                                                 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
688                                                 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
689                                                 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
690                                                 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
691                                                 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
692                         };
693
694                         emmc_clk: emmc-clk {
695                                 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
696                         };
697
698                         emmc_cmd: emmc-cmd {
699                                 rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
700                         };
701                 };
702
703                 gmac {
704                         rmii_pins: rmii-pins {
705                                 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
706                                                 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
707                                                 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
708                                                 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
709                                                 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
710                                                 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
711                                                 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
712                                                 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
713                                                 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
714                                                 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
715                         };
716                 };
717
718                 i2c0 {
719                         i2c0_xfer: i2c0-xfer {
720                                 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
721                                                 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
722                         };
723                 };
724
725                 i2c1 {
726                         i2c1_xfer: i2c1-xfer {
727                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
728                                                 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
729                         };
730                 };
731
732                 i2c2m1 {
733                         i2c2m1_xfer: i2c2m1-xfer {
734                                 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
735                                                 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
736                         };
737
738                         i2c2m1_gpio: i2c2m1-gpio {
739                                 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
740                                                 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
741                         };
742                 };
743
744                 i2c2m05v {
745                         i2c2m05v_xfer: i2c2m05v-xfer {
746                                 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
747                                                 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
748                         };
749
750                         i2c2m05v_gpio: i2c2m05v-gpio {
751                                 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
752                                                 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
753                         };
754                 };
755
756                 i2c3 {
757                         i2c3_xfer: i2c3-xfer {
758                                 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
759                                                 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
760                         };
761                 };
762
763                 pwm0 {
764                         pwm0_pin: pwm0-pin {
765                                 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
766                         };
767                 };
768
769                 pwm1 {
770                         pwm1_pin: pwm1-pin {
771                                 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
772                         };
773                 };
774
775                 pwm2 {
776                         pwm2_pin: pwm2-pin {
777                                 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
778                         };
779                 };
780
781                 pwm3 {
782                         pwm3_pin: pwm3-pin {
783                                 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
784                         };
785                 };
786
787                 pwm4 {
788                         pwm4_pin: pwm4-pin {
789                                 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
790                         };
791                 };
792
793                 pwm5 {
794                         pwm5_pin: pwm5-pin {
795                                 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
796                         };
797                 };
798
799                 pwm6 {
800                         pwm6_pin: pwm6-pin {
801                                 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
802                         };
803                 };
804
805                 pwm7 {
806                         pwm7_pin: pwm7-pin {
807                                 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
808                         };
809                 };
810
811                 sdmmc {
812                         sdmmc_clk: sdmmc-clk {
813                                 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
814                         };
815
816                         sdmmc_cmd: sdmmc-cmd {
817                                 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
818                         };
819
820                         sdmmc_cd: sdmmc-cd {
821                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
822                         };
823
824                         sdmmc_bus1: sdmmc-bus1 {
825                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
826                         };
827
828                         sdmmc_bus4: sdmmc-bus4 {
829                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
830                                                 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
831                                                 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
832                                                 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
833                         };
834                 };
835
836                 tsadc {
837                         otp_out: otp-out {
838                                 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
839                         };
840
841                         otp_gpio: otp-gpio {
842                                 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
843                         };
844                 };
845
846                 uart0 {
847                         uart0_xfer: uart0-xfer {
848                                 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
849                                                 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
850                         };
851
852                         uart0_cts: uart0-cts {
853                                 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
854                         };
855
856                         uart0_rts: uart0-rts {
857                                 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
858                         };
859
860                         uart0_rts_gpio: uart0-rts-gpio {
861                                 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
862                         };
863                 };
864
865                 uart1 {
866                         uart1_xfer: uart1-xfer {
867                                 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
868                                                 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
869                         };
870
871                         uart1_cts: uart1-cts {
872                                 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
873                         };
874
875                         uart1_rts: uart1-rts {
876                                 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
877                         };
878                 };
879
880                 uart2m0 {
881                         uart2m0_xfer: uart2m0-xfer {
882                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
883                                                 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
884                         };
885                 };
886
887                 uart2m1 {
888                         uart2m1_xfer: uart2m1-xfer {
889                                 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
890                                                 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
891                         };
892                 };
893
894                 uart2_5v {
895                         uart2_5v_cts: uart2_5v-cts {
896                                 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
897                         };
898
899                         uart2_5v_rts: uart2_5v-rts {
900                                 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
901                         };
902                 };
903         };
904 };