arm: dts: socfpga: remove dma-mask property
[muen/linux.git] / arch / arm / boot / dts / socfpga_arria10.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright Altera Corporation (C) 2014. All rights reserved.
4  */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
8
9 / {
10         #address-cells = <1>;
11         #size-cells = <1>;
12
13         cpus {
14                 #address-cells = <1>;
15                 #size-cells = <0>;
16                 enable-method = "altr,socfpga-a10-smp";
17
18                 cpu@0 {
19                         compatible = "arm,cortex-a9";
20                         device_type = "cpu";
21                         reg = <0>;
22                         next-level-cache = <&L2>;
23                 };
24                 cpu@1 {
25                         compatible = "arm,cortex-a9";
26                         device_type = "cpu";
27                         reg = <1>;
28                         next-level-cache = <&L2>;
29                 };
30         };
31
32         intc: intc@ffffd000 {
33                 compatible = "arm,cortex-a9-gic";
34                 #interrupt-cells = <3>;
35                 interrupt-controller;
36                 reg = <0xffffd000 0x1000>,
37                       <0xffffc100 0x100>;
38         };
39
40         soc {
41                 #address-cells = <1>;
42                 #size-cells = <1>;
43                 compatible = "simple-bus";
44                 device_type = "soc";
45                 interrupt-parent = <&intc>;
46                 ranges;
47
48                 amba {
49                         compatible = "simple-bus";
50                         #address-cells = <1>;
51                         #size-cells = <1>;
52                         ranges;
53
54                         pdma: pdma@ffda1000 {
55                                 compatible = "arm,pl330", "arm,primecell";
56                                 reg = <0xffda1000 0x1000>;
57                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
58                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
59                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
60                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
61                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
62                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
63                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
64                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
65                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
66                                 #dma-cells = <1>;
67                                 #dma-channels = <8>;
68                                 #dma-requests = <32>;
69                                 clocks = <&l4_main_clk>;
70                                 clock-names = "apb_pclk";
71                         };
72                 };
73
74                 base_fpga_region {
75                         #address-cells = <0x1>;
76                         #size-cells = <0x1>;
77
78                         compatible = "fpga-region";
79                         fpga-mgr = <&fpga_mgr>;
80                 };
81
82                 clkmgr@ffd04000 {
83                                 compatible = "altr,clk-mgr";
84                                 reg = <0xffd04000 0x1000>;
85
86                                 clocks {
87                                         #address-cells = <1>;
88                                         #size-cells = <0>;
89
90                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
91                                                 #clock-cells = <0>;
92                                                 compatible = "fixed-clock";
93                                         };
94
95                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
96                                                 #clock-cells = <0>;
97                                                 compatible = "fixed-clock";
98                                         };
99
100                                         f2s_free_clk: f2s_free_clk {
101                                                 #clock-cells = <0>;
102                                                 compatible = "fixed-clock";
103                                         };
104
105                                         osc1: osc1 {
106                                                 #clock-cells = <0>;
107                                                 compatible = "fixed-clock";
108                                         };
109
110                                         main_pll: main_pll@40 {
111                                                 #address-cells = <1>;
112                                                 #size-cells = <0>;
113                                                 #clock-cells = <0>;
114                                                 compatible = "altr,socfpga-a10-pll-clock";
115                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
116                                                          <&f2s_free_clk>;
117                                                 reg = <0x40>;
118
119                                                 main_mpu_base_clk: main_mpu_base_clk {
120                                                         #clock-cells = <0>;
121                                                         compatible = "altr,socfpga-a10-perip-clk";
122                                                         clocks = <&main_pll>;
123                                                         div-reg = <0x140 0 11>;
124                                                 };
125
126                                                 main_noc_base_clk: main_noc_base_clk {
127                                                         #clock-cells = <0>;
128                                                         compatible = "altr,socfpga-a10-perip-clk";
129                                                         clocks = <&main_pll>;
130                                                         div-reg = <0x144 0 11>;
131                                                 };
132
133                                                 main_emaca_clk: main_emaca_clk@68 {
134                                                         #clock-cells = <0>;
135                                                         compatible = "altr,socfpga-a10-perip-clk";
136                                                         clocks = <&main_pll>;
137                                                         reg = <0x68>;
138                                                 };
139
140                                                 main_emacb_clk: main_emacb_clk@6c {
141                                                         #clock-cells = <0>;
142                                                         compatible = "altr,socfpga-a10-perip-clk";
143                                                         clocks = <&main_pll>;
144                                                         reg = <0x6C>;
145                                                 };
146
147                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
148                                                         #clock-cells = <0>;
149                                                         compatible = "altr,socfpga-a10-perip-clk";
150                                                         clocks = <&main_pll>;
151                                                         reg = <0x70>;
152                                                 };
153
154                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
155                                                         #clock-cells = <0>;
156                                                         compatible = "altr,socfpga-a10-perip-clk";
157                                                         clocks = <&main_pll>;
158                                                         reg = <0x74>;
159                                                 };
160
161                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
162                                                         #clock-cells = <0>;
163                                                         compatible = "altr,socfpga-a10-perip-clk"
164 ;
165                                                         clocks = <&main_pll>;
166                                                         reg = <0x78>;
167                                                 };
168
169                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
170                                                         #clock-cells = <0>;
171                                                         compatible = "altr,socfpga-a10-perip-clk";
172                                                         clocks = <&main_pll>;
173                                                         reg = <0x7C>;
174                                                 };
175
176                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
177                                                         #clock-cells = <0>;
178                                                         compatible = "altr,socfpga-a10-perip-clk";
179                                                         clocks = <&main_pll>;
180                                                         reg = <0x80>;
181                                                 };
182
183                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
184                                                         #clock-cells = <0>;
185                                                         compatible = "altr,socfpga-a10-perip-clk";
186                                                         clocks = <&main_pll>;
187                                                         reg = <0x84>;
188                                                 };
189
190                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
191                                                         #clock-cells = <0>;
192                                                         compatible = "altr,socfpga-a10-perip-clk";
193                                                         clocks = <&main_pll>;
194                                                         reg = <0x9C>;
195                                                 };
196                                         };
197
198                                         periph_pll: periph_pll@c0 {
199                                                 #address-cells = <1>;
200                                                 #size-cells = <0>;
201                                                 #clock-cells = <0>;
202                                                 compatible = "altr,socfpga-a10-pll-clock";
203                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
204                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
205                                                 reg = <0xC0>;
206
207                                                 peri_mpu_base_clk: peri_mpu_base_clk {
208                                                         #clock-cells = <0>;
209                                                         compatible = "altr,socfpga-a10-perip-clk";
210                                                         clocks = <&periph_pll>;
211                                                         div-reg = <0x140 16 11>;
212                                                 };
213
214                                                 peri_noc_base_clk: peri_noc_base_clk {
215                                                         #clock-cells = <0>;
216                                                         compatible = "altr,socfpga-a10-perip-clk";
217                                                         clocks = <&periph_pll>;
218                                                         div-reg = <0x144 16 11>;
219                                                 };
220
221                                                 peri_emaca_clk: peri_emaca_clk@e8 {
222                                                         #clock-cells = <0>;
223                                                         compatible = "altr,socfpga-a10-perip-clk";
224                                                         clocks = <&periph_pll>;
225                                                         reg = <0xE8>;
226                                                 };
227
228                                                 peri_emacb_clk: peri_emacb_clk@ec {
229                                                         #clock-cells = <0>;
230                                                         compatible = "altr,socfpga-a10-perip-clk";
231                                                         clocks = <&periph_pll>;
232                                                         reg = <0xEC>;
233                                                 };
234
235                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
236                                                         #clock-cells = <0>;
237                                                         compatible = "altr,socfpga-a10-perip-clk";
238                                                         clocks = <&periph_pll>;
239                                                         reg = <0xF0>;
240                                                 };
241
242                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
243                                                         #clock-cells = <0>;
244                                                         compatible = "altr,socfpga-a10-perip-clk";
245                                                         clocks = <&periph_pll>;
246                                                         reg = <0xF4>;
247                                                 };
248
249                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
250                                                         #clock-cells = <0>;
251                                                         compatible = "altr,socfpga-a10-perip-clk";
252                                                         clocks = <&periph_pll>;
253                                                         reg = <0xF8>;
254                                                 };
255
256                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
257                                                         #clock-cells = <0>;
258                                                         compatible = "altr,socfpga-a10-perip-clk";
259                                                         clocks = <&periph_pll>;
260                                                         reg = <0xFC>;
261                                                 };
262
263                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
264                                                         #clock-cells = <0>;
265                                                         compatible = "altr,socfpga-a10-perip-clk";
266                                                         clocks = <&periph_pll>;
267                                                         reg = <0x100>;
268                                                 };
269
270                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
271                                                         #clock-cells = <0>;
272                                                         compatible = "altr,socfpga-a10-perip-clk";
273                                                         clocks = <&periph_pll>;
274                                                         reg = <0x104>;
275                                                 };
276                                         };
277
278                                         mpu_free_clk: mpu_free_clk@60 {
279                                                 #clock-cells = <0>;
280                                                 compatible = "altr,socfpga-a10-perip-clk";
281                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
282                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
283                                                          <&f2s_free_clk>;
284                                                 reg = <0x60>;
285                                         };
286
287                                         noc_free_clk: noc_free_clk@64 {
288                                                 #clock-cells = <0>;
289                                                 compatible = "altr,socfpga-a10-perip-clk";
290                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
291                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
292                                                          <&f2s_free_clk>;
293                                                 reg = <0x64>;
294                                         };
295
296                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
297                                                 #clock-cells = <0>;
298                                                 compatible = "altr,socfpga-a10-perip-clk";
299                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
300                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
301                                                          <&f2s_free_clk>;
302                                                 reg = <0x104>;
303                                         };
304
305                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
306                                                 #clock-cells = <0>;
307                                                 compatible = "altr,socfpga-a10-perip-clk";
308                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
309                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
310                                                          <&f2s_free_clk>;
311                                                 fixed-divider = <4>;
312                                                 reg = <0xF8>;
313                                         };
314
315                                         l4_sys_free_clk: l4_sys_free_clk {
316                                                 #clock-cells = <0>;
317                                                 compatible = "altr,socfpga-a10-perip-clk";
318                                                 clocks = <&noc_free_clk>;
319                                                 fixed-divider = <4>;
320                                         };
321
322                                         l4_main_clk: l4_main_clk {
323                                                 #clock-cells = <0>;
324                                                 compatible = "altr,socfpga-a10-gate-clk";
325                                                 clocks = <&noc_free_clk>;
326                                                 div-reg = <0xA8 0 2>;
327                                                 clk-gate = <0x48 1>;
328                                         };
329
330                                         l4_mp_clk: l4_mp_clk {
331                                                 #clock-cells = <0>;
332                                                 compatible = "altr,socfpga-a10-gate-clk";
333                                                 clocks = <&noc_free_clk>;
334                                                 div-reg = <0xA8 8 2>;
335                                                 clk-gate = <0x48 2>;
336                                         };
337
338                                         l4_sp_clk: l4_sp_clk {
339                                                 #clock-cells = <0>;
340                                                 compatible = "altr,socfpga-a10-gate-clk";
341                                                 clocks = <&noc_free_clk>;
342                                                 div-reg = <0xA8 16 2>;
343                                                 clk-gate = <0x48 3>;
344                                         };
345
346                                         mpu_periph_clk: mpu_periph_clk {
347                                                 #clock-cells = <0>;
348                                                 compatible = "altr,socfpga-a10-gate-clk";
349                                                 clocks = <&mpu_free_clk>;
350                                                 fixed-divider = <4>;
351                                                 clk-gate = <0x48 0>;
352                                         };
353
354                                         sdmmc_clk: sdmmc_clk {
355                                                 #clock-cells = <0>;
356                                                 compatible = "altr,socfpga-a10-gate-clk";
357                                                 clocks = <&sdmmc_free_clk>;
358                                                 clk-gate = <0xC8 5>;
359                                                 clk-phase = <0 135>;
360                                         };
361
362                                         qspi_clk: qspi_clk {
363                                                 #clock-cells = <0>;
364                                                 compatible = "altr,socfpga-a10-gate-clk";
365                                                 clocks = <&l4_main_clk>;
366                                                 clk-gate = <0xC8 11>;
367                                         };
368
369                                         nand_x_clk: nand_x_clk {
370                                                 #clock-cells = <0>;
371                                                 compatible = "altr,socfpga-a10-gate-clk";
372                                                 clocks = <&l4_mp_clk>;
373                                                 clk-gate = <0xC8 10>;
374                                         };
375
376                                         nand_ecc_clk: nand_ecc_clk {
377                                                 #clock-cells = <0>;
378                                                 compatible = "altr,socfpga-a10-gate-clk";
379                                                 clocks = <&nand_x_clk>;
380                                                 clk-gate = <0xC8 10>;
381                                         };
382
383                                         nand_clk: nand_clk {
384                                                 #clock-cells = <0>;
385                                                 compatible = "altr,socfpga-a10-gate-clk";
386                                                 clocks = <&nand_x_clk>;
387                                                 fixed-divider = <4>;
388                                                 clk-gate = <0xC8 10>;
389                                         };
390
391                                         spi_m_clk: spi_m_clk {
392                                                 #clock-cells = <0>;
393                                                 compatible = "altr,socfpga-a10-gate-clk";
394                                                 clocks = <&l4_main_clk>;
395                                                 clk-gate = <0xC8 9>;
396                                         };
397
398                                         usb_clk: usb_clk {
399                                                 #clock-cells = <0>;
400                                                 compatible = "altr,socfpga-a10-gate-clk";
401                                                 clocks = <&l4_mp_clk>;
402                                                 clk-gate = <0xC8 8>;
403                                         };
404
405                                         s2f_usr1_clk: s2f_usr1_clk {
406                                                 #clock-cells = <0>;
407                                                 compatible = "altr,socfpga-a10-gate-clk";
408                                                 clocks = <&peri_s2f_usr1_clk>;
409                                                 clk-gate = <0xC8 6>;
410                                         };
411                                 };
412                 };
413
414                 socfpga_axi_setup: stmmac-axi-config {
415                         snps,wr_osr_lmt = <0xf>;
416                         snps,rd_osr_lmt = <0xf>;
417                         snps,blen = <0 0 0 0 16 0 0>;
418                 };
419
420                 gmac0: ethernet@ff800000 {
421                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
422                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
423                         reg = <0xff800000 0x2000>;
424                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
425                         interrupt-names = "macirq";
426                         /* Filled in by bootloader */
427                         mac-address = [00 00 00 00 00 00];
428                         snps,multicast-filter-bins = <256>;
429                         snps,perfect-filter-entries = <128>;
430                         tx-fifo-depth = <4096>;
431                         rx-fifo-depth = <16384>;
432                         clocks = <&l4_mp_clk>;
433                         clock-names = "stmmaceth";
434                         resets = <&rst EMAC0_RESET>;
435                         reset-names = "stmmaceth";
436                         snps,axi-config = <&socfpga_axi_setup>;
437                         status = "disabled";
438                 };
439
440                 gmac1: ethernet@ff802000 {
441                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
442                         altr,sysmgr-syscon = <&sysmgr 0x48 0>;
443                         reg = <0xff802000 0x2000>;
444                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
445                         interrupt-names = "macirq";
446                         /* Filled in by bootloader */
447                         mac-address = [00 00 00 00 00 00];
448                         snps,multicast-filter-bins = <256>;
449                         snps,perfect-filter-entries = <128>;
450                         tx-fifo-depth = <4096>;
451                         rx-fifo-depth = <16384>;
452                         clocks = <&l4_mp_clk>;
453                         clock-names = "stmmaceth";
454                         resets = <&rst EMAC1_RESET>;
455                         reset-names = "stmmaceth";
456                         snps,axi-config = <&socfpga_axi_setup>;
457                         status = "disabled";
458                 };
459
460                 gmac2: ethernet@ff804000 {
461                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
462                         altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
463                         reg = <0xff804000 0x2000>;
464                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
465                         interrupt-names = "macirq";
466                         /* Filled in by bootloader */
467                         mac-address = [00 00 00 00 00 00];
468                         snps,multicast-filter-bins = <256>;
469                         snps,perfect-filter-entries = <128>;
470                         tx-fifo-depth = <4096>;
471                         rx-fifo-depth = <16384>;
472                         clocks = <&l4_mp_clk>;
473                         clock-names = "stmmaceth";
474                         snps,axi-config = <&socfpga_axi_setup>;
475                         status = "disabled";
476                 };
477
478                 gpio0: gpio@ffc02900 {
479                         #address-cells = <1>;
480                         #size-cells = <0>;
481                         compatible = "snps,dw-apb-gpio";
482                         reg = <0xffc02900 0x100>;
483                         status = "disabled";
484
485                         porta: gpio-controller@0 {
486                                 compatible = "snps,dw-apb-gpio-port";
487                                 gpio-controller;
488                                 #gpio-cells = <2>;
489                                 snps,nr-gpios = <29>;
490                                 reg = <0>;
491                                 interrupt-controller;
492                                 #interrupt-cells = <2>;
493                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
494                         };
495                 };
496
497                 gpio1: gpio@ffc02a00 {
498                         #address-cells = <1>;
499                         #size-cells = <0>;
500                         compatible = "snps,dw-apb-gpio";
501                         reg = <0xffc02a00 0x100>;
502                         status = "disabled";
503
504                         portb: gpio-controller@0 {
505                                 compatible = "snps,dw-apb-gpio-port";
506                                 gpio-controller;
507                                 #gpio-cells = <2>;
508                                 snps,nr-gpios = <29>;
509                                 reg = <0>;
510                                 interrupt-controller;
511                                 #interrupt-cells = <2>;
512                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
513                         };
514                 };
515
516                 gpio2: gpio@ffc02b00 {
517                         #address-cells = <1>;
518                         #size-cells = <0>;
519                         compatible = "snps,dw-apb-gpio";
520                         reg = <0xffc02b00 0x100>;
521                         status = "disabled";
522
523                         portc: gpio-controller@0 {
524                                 compatible = "snps,dw-apb-gpio-port";
525                                 gpio-controller;
526                                 #gpio-cells = <2>;
527                                 snps,nr-gpios = <27>;
528                                 reg = <0>;
529                                 interrupt-controller;
530                                 #interrupt-cells = <2>;
531                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
532                         };
533                 };
534
535                 fpga_mgr: fpga-mgr@ffd03000 {
536                         compatible = "altr,socfpga-a10-fpga-mgr";
537                         reg = <0xffd03000 0x100
538                                0xffcfe400 0x20>;
539                         clocks = <&l4_mp_clk>;
540                         resets = <&rst FPGAMGR_RESET>;
541                         reset-names = "fpgamgr";
542                 };
543
544                 i2c0: i2c@ffc02200 {
545                         #address-cells = <1>;
546                         #size-cells = <0>;
547                         compatible = "snps,designware-i2c";
548                         reg = <0xffc02200 0x100>;
549                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
550                         clocks = <&l4_sp_clk>;
551                         status = "disabled";
552                 };
553
554                 i2c1: i2c@ffc02300 {
555                         #address-cells = <1>;
556                         #size-cells = <0>;
557                         compatible = "snps,designware-i2c";
558                         reg = <0xffc02300 0x100>;
559                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
560                         clocks = <&l4_sp_clk>;
561                         status = "disabled";
562                 };
563
564                 i2c2: i2c@ffc02400 {
565                         #address-cells = <1>;
566                         #size-cells = <0>;
567                         compatible = "snps,designware-i2c";
568                         reg = <0xffc02400 0x100>;
569                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
570                         clocks = <&l4_sp_clk>;
571                         status = "disabled";
572                 };
573
574                 i2c3: i2c@ffc02500 {
575                         #address-cells = <1>;
576                         #size-cells = <0>;
577                         compatible = "snps,designware-i2c";
578                         reg = <0xffc02500 0x100>;
579                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
580                         clocks = <&l4_sp_clk>;
581                         status = "disabled";
582                 };
583
584                 i2c4: i2c@ffc02600 {
585                         #address-cells = <1>;
586                         #size-cells = <0>;
587                         compatible = "snps,designware-i2c";
588                         reg = <0xffc02600 0x100>;
589                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
590                         clocks = <&l4_sp_clk>;
591                         status = "disabled";
592                 };
593
594                 spi0: spi@ffda4000 {
595                         compatible = "snps,dw-apb-ssi";
596                         #address-cells = <1>;
597                         #size-cells = <0>;
598                         reg = <0xffda4000 0x100>;
599                         interrupts = <0 101 4>;
600                         num-cs = <4>;
601                         /*32bit_access;*/
602                         clocks = <&spi_m_clk>;
603                         status = "disabled";
604                 };
605
606                 spi1: spi@ffda5000 {
607                         compatible = "snps,dw-apb-ssi";
608                         #address-cells = <1>;
609                         #size-cells = <0>;
610                         reg = <0xffda5000 0x100>;
611                         interrupts = <0 102 4>;
612                         num-cs = <4>;
613                         /*32bit_access;*/
614                         tx-dma-channel = <&pdma 16>;
615                         rx-dma-channel = <&pdma 17>;
616                         clocks = <&spi_m_clk>;
617                         status = "disabled";
618                 };
619
620                 sdr: sdr@ffcfb100 {
621                         compatible = "altr,sdr-ctl", "syscon";
622                         reg = <0xffcfb100 0x80>;
623                 };
624
625                 L2: l2-cache@fffff000 {
626                         compatible = "arm,pl310-cache";
627                         reg = <0xfffff000 0x1000>;
628                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
629                         cache-unified;
630                         cache-level = <2>;
631                         prefetch-data = <1>;
632                         prefetch-instr = <1>;
633                         arm,shared-override;
634                 };
635
636                 mmc: dwmmc0@ff808000 {
637                         #address-cells = <1>;
638                         #size-cells = <0>;
639                         compatible = "altr,socfpga-dw-mshc";
640                         reg = <0xff808000 0x1000>;
641                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
642                         fifo-depth = <0x400>;
643                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
644                         clock-names = "biu", "ciu";
645                         status = "disabled";
646                 };
647
648                 nand: nand@ffb90000 {
649                         #address-cells = <1>;
650                         #size-cells = <1>;
651                         compatible = "altr,socfpga-denali-nand";
652                         reg = <0xffb90000 0x72000>,
653                               <0xffb80000 0x10000>;
654                         reg-names = "nand_data", "denali_reg";
655                         interrupts = <0 99 4>;
656                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
657                         clock-names = "nand", "nand_x", "ecc";
658                         status = "disabled";
659                 };
660
661                 ocram: sram@ffe00000 {
662                         compatible = "mmio-sram";
663                         reg = <0xffe00000 0x40000>;
664                 };
665
666                 eccmgr: eccmgr {
667                         compatible = "altr,socfpga-a10-ecc-manager";
668                         altr,sysmgr-syscon = <&sysmgr>;
669                         #address-cells = <1>;
670                         #size-cells = <1>;
671                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
672                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
673                         interrupt-controller;
674                         #interrupt-cells = <2>;
675                         ranges;
676
677                         sdramedac {
678                                 compatible = "altr,sdram-edac-a10";
679                                 altr,sdr-syscon = <&sdr>;
680                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
681                                              <49 IRQ_TYPE_LEVEL_HIGH>;
682                         };
683
684                         l2-ecc@ffd06010 {
685                                 compatible = "altr,socfpga-a10-l2-ecc";
686                                 reg = <0xffd06010 0x4>;
687                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
688                                              <32 IRQ_TYPE_LEVEL_HIGH>;
689                         };
690
691                         ocram-ecc@ff8c3000 {
692                                 compatible = "altr,socfpga-a10-ocram-ecc";
693                                 reg = <0xff8c3000 0x400>;
694                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
695                                              <33 IRQ_TYPE_LEVEL_HIGH>;
696                         };
697
698                         emac0-rx-ecc@ff8c0800 {
699                                 compatible = "altr,socfpga-eth-mac-ecc";
700                                 reg = <0xff8c0800 0x400>;
701                                 altr,ecc-parent = <&gmac0>;
702                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
703                                              <36 IRQ_TYPE_LEVEL_HIGH>;
704                         };
705
706                         emac0-tx-ecc@ff8c0c00 {
707                                 compatible = "altr,socfpga-eth-mac-ecc";
708                                 reg = <0xff8c0c00 0x400>;
709                                 altr,ecc-parent = <&gmac0>;
710                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
711                                              <37 IRQ_TYPE_LEVEL_HIGH>;
712                         };
713
714                         dma-ecc@ff8c8000 {
715                                 compatible = "altr,socfpga-dma-ecc";
716                                 reg = <0xff8c8000 0x400>;
717                                 altr,ecc-parent = <&pdma>;
718                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
719                                              <42 IRQ_TYPE_LEVEL_HIGH>;
720                         };
721
722                         usb0-ecc@ff8c8800 {
723                                 compatible = "altr,socfpga-usb-ecc";
724                                 reg = <0xff8c8800 0x400>;
725                                 altr,ecc-parent = <&usb0>;
726                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
727                                              <34 IRQ_TYPE_LEVEL_HIGH>;
728                         };
729                 };
730
731                 qspi: spi@ff809000 {
732                         compatible = "cdns,qspi-nor";
733                         #address-cells = <1>;
734                         #size-cells = <0>;
735                         reg = <0xff809000 0x100>,
736                               <0xffa00000 0x100000>;
737                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
738                         cdns,fifo-depth = <128>;
739                         cdns,fifo-width = <4>;
740                         cdns,trigger-address = <0x00000000>;
741                         clocks = <&qspi_clk>;
742                         status = "disabled";
743                 };
744
745                 rst: rstmgr@ffd05000 {
746                         #reset-cells = <1>;
747                         compatible = "altr,rst-mgr";
748                         reg = <0xffd05000 0x100>;
749                         altr,modrst-offset = <0x20>;
750                 };
751
752                 scu: snoop-control-unit@ffffc000 {
753                         compatible = "arm,cortex-a9-scu";
754                         reg = <0xffffc000 0x100>;
755                 };
756
757                 sysmgr: sysmgr@ffd06000 {
758                         compatible = "altr,sys-mgr", "syscon";
759                         reg = <0xffd06000 0x300>;
760                         cpu1-start-addr = <0xffd06230>;
761                 };
762
763                 /* Local timer */
764                 timer@ffffc600 {
765                         compatible = "arm,cortex-a9-twd-timer";
766                         reg = <0xffffc600 0x100>;
767                         interrupts = <1 13 0xf01>;
768                         clocks = <&mpu_periph_clk>;
769                 };
770
771                 timer0: timer0@ffc02700 {
772                         compatible = "snps,dw-apb-timer";
773                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
774                         reg = <0xffc02700 0x100>;
775                         clocks = <&l4_sp_clk>;
776                         clock-names = "timer";
777                         resets = <&rst SPTIMER0_RESET>;
778                         reset-names = "timer";
779                 };
780
781                 timer1: timer1@ffc02800 {
782                         compatible = "snps,dw-apb-timer";
783                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
784                         reg = <0xffc02800 0x100>;
785                         clocks = <&l4_sp_clk>;
786                         clock-names = "timer";
787                         resets = <&rst SPTIMER1_RESET>;
788                         reset-names = "timer";
789                 };
790
791                 timer2: timer2@ffd00000 {
792                         compatible = "snps,dw-apb-timer";
793                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
794                         reg = <0xffd00000 0x100>;
795                         clocks = <&l4_sys_free_clk>;
796                         clock-names = "timer";
797                         resets = <&rst L4SYSTIMER0_RESET>;
798                         reset-names = "timer";
799                 };
800
801                 timer3: timer3@ffd00100 {
802                         compatible = "snps,dw-apb-timer";
803                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
804                         reg = <0xffd01000 0x100>;
805                         clocks = <&l4_sys_free_clk>;
806                         clock-names = "timer";
807                         resets = <&rst L4SYSTIMER1_RESET>;
808                         reset-names = "timer";
809                 };
810
811                 uart0: serial0@ffc02000 {
812                         compatible = "snps,dw-apb-uart";
813                         reg = <0xffc02000 0x100>;
814                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
815                         reg-shift = <2>;
816                         reg-io-width = <4>;
817                         clocks = <&l4_sp_clk>;
818                         status = "disabled";
819                 };
820
821                 uart1: serial1@ffc02100 {
822                         compatible = "snps,dw-apb-uart";
823                         reg = <0xffc02100 0x100>;
824                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
825                         reg-shift = <2>;
826                         reg-io-width = <4>;
827                         clocks = <&l4_sp_clk>;
828                         status = "disabled";
829                 };
830
831                 usbphy0: usbphy {
832                         #phy-cells = <0>;
833                         compatible = "usb-nop-xceiv";
834                         status = "okay";
835                 };
836
837                 usb0: usb@ffb00000 {
838                         compatible = "snps,dwc2";
839                         reg = <0xffb00000 0xffff>;
840                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
841                         clocks = <&usb_clk>;
842                         clock-names = "otg";
843                         resets = <&rst USB0_RESET>;
844                         reset-names = "dwc2";
845                         phys = <&usbphy0>;
846                         phy-names = "usb2-phy";
847                         status = "disabled";
848                 };
849
850                 usb1: usb@ffb40000 {
851                         compatible = "snps,dwc2";
852                         reg = <0xffb40000 0xffff>;
853                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
854                         clocks = <&usb_clk>;
855                         clock-names = "otg";
856                         resets = <&rst USB1_RESET>;
857                         reset-names = "dwc2";
858                         phys = <&usbphy0>;
859                         phy-names = "usb2-phy";
860                         status = "disabled";
861                 };
862
863                 watchdog0: watchdog@ffd00200 {
864                         compatible = "snps,dw-wdt";
865                         reg = <0xffd00200 0x100>;
866                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
867                         clocks = <&l4_sys_free_clk>;
868                         status = "disabled";
869                 };
870
871                 watchdog1: watchdog@ffd00300 {
872                         compatible = "snps,dw-wdt";
873                         reg = <0xffd00300 0x100>;
874                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
875                         clocks = <&l4_sys_free_clk>;
876                         status = "disabled";
877                 };
878         };
879 };