Merge tag 'stm32-dt-for-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[muen/linux.git] / arch / arm / boot / dts / stm32f429.dtsi
1 /*
2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  *     You should have received a copy of the GNU General Public
20  *     License along with this file; if not, write to the Free
21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22  *     MA 02110-1301 USA
23  *
24  * Or, alternatively,
25  *
26  *  b) Permission is hereby granted, free of charge, to any person
27  *     obtaining a copy of this software and associated documentation
28  *     files (the "Software"), to deal in the Software without
29  *     restriction, including without limitation the rights to use,
30  *     copy, modify, merge, publish, distribute, sublicense, and/or
31  *     sell copies of the Software, and to permit persons to whom the
32  *     Software is furnished to do so, subject to the following
33  *     conditions:
34  *
35  *     The above copyright notice and this permission notice shall be
36  *     included in all copies or substantial portions of the Software.
37  *
38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45  *     OTHER DEALINGS IN THE SOFTWARE.
46  */
47
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
51
52 / {
53         #address-cells = <1>;
54         #size-cells = <1>;
55
56         clocks {
57                 clk_hse: clk-hse {
58                         #clock-cells = <0>;
59                         compatible = "fixed-clock";
60                         clock-frequency = <0>;
61                 };
62
63                 clk_lse: clk-lse {
64                         #clock-cells = <0>;
65                         compatible = "fixed-clock";
66                         clock-frequency = <32768>;
67                 };
68
69                 clk_lsi: clk-lsi {
70                         #clock-cells = <0>;
71                         compatible = "fixed-clock";
72                         clock-frequency = <32000>;
73                 };
74
75                 clk_i2s_ckin: i2s-ckin {
76                         #clock-cells = <0>;
77                         compatible = "fixed-clock";
78                         clock-frequency = <0>;
79                 };
80         };
81
82         soc {
83                 timer2: timer@40000000 {
84                         compatible = "st,stm32-timer";
85                         reg = <0x40000000 0x400>;
86                         interrupts = <28>;
87                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
88                         status = "disabled";
89                 };
90
91                 timers2: timers@40000000 {
92                         #address-cells = <1>;
93                         #size-cells = <0>;
94                         compatible = "st,stm32-timers";
95                         reg = <0x40000000 0x400>;
96                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
97                         clock-names = "int";
98                         status = "disabled";
99
100                         pwm {
101                                 compatible = "st,stm32-pwm";
102                                 status = "disabled";
103                         };
104
105                         timer@1 {
106                                 compatible = "st,stm32-timer-trigger";
107                                 reg = <1>;
108                                 status = "disabled";
109                         };
110                 };
111
112                 timer3: timer@40000400 {
113                         compatible = "st,stm32-timer";
114                         reg = <0x40000400 0x400>;
115                         interrupts = <29>;
116                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
117                         status = "disabled";
118                 };
119
120                 timers3: timers@40000400 {
121                         #address-cells = <1>;
122                         #size-cells = <0>;
123                         compatible = "st,stm32-timers";
124                         reg = <0x40000400 0x400>;
125                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
126                         clock-names = "int";
127                         status = "disabled";
128
129                         pwm {
130                                 compatible = "st,stm32-pwm";
131                                 status = "disabled";
132                         };
133
134                         timer@2 {
135                                 compatible = "st,stm32-timer-trigger";
136                                 reg = <2>;
137                                 status = "disabled";
138                         };
139                 };
140
141                 timer4: timer@40000800 {
142                         compatible = "st,stm32-timer";
143                         reg = <0x40000800 0x400>;
144                         interrupts = <30>;
145                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
146                         status = "disabled";
147                 };
148
149                 timers4: timers@40000800 {
150                         #address-cells = <1>;
151                         #size-cells = <0>;
152                         compatible = "st,stm32-timers";
153                         reg = <0x40000800 0x400>;
154                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
155                         clock-names = "int";
156                         status = "disabled";
157
158                         pwm {
159                                 compatible = "st,stm32-pwm";
160                                 status = "disabled";
161                         };
162
163                         timer@3 {
164                                 compatible = "st,stm32-timer-trigger";
165                                 reg = <3>;
166                                 status = "disabled";
167                         };
168                 };
169
170                 timer5: timer@40000c00 {
171                         compatible = "st,stm32-timer";
172                         reg = <0x40000c00 0x400>;
173                         interrupts = <50>;
174                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
175                 };
176
177                 timers5: timers@40000c00 {
178                         #address-cells = <1>;
179                         #size-cells = <0>;
180                         compatible = "st,stm32-timers";
181                         reg = <0x40000C00 0x400>;
182                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
183                         clock-names = "int";
184                         status = "disabled";
185
186                         pwm {
187                                 compatible = "st,stm32-pwm";
188                                 status = "disabled";
189                         };
190
191                         timer@4 {
192                                 compatible = "st,stm32-timer-trigger";
193                                 reg = <4>;
194                                 status = "disabled";
195                         };
196                 };
197
198                 timer6: timer@40001000 {
199                         compatible = "st,stm32-timer";
200                         reg = <0x40001000 0x400>;
201                         interrupts = <54>;
202                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
203                         status = "disabled";
204                 };
205
206                 timers6: timers@40001000 {
207                         #address-cells = <1>;
208                         #size-cells = <0>;
209                         compatible = "st,stm32-timers";
210                         reg = <0x40001000 0x400>;
211                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
212                         clock-names = "int";
213                         status = "disabled";
214
215                         timer@5 {
216                                 compatible = "st,stm32-timer-trigger";
217                                 reg = <5>;
218                                 status = "disabled";
219                         };
220                 };
221
222                 timer7: timer@40001400 {
223                         compatible = "st,stm32-timer";
224                         reg = <0x40001400 0x400>;
225                         interrupts = <55>;
226                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
227                         status = "disabled";
228                 };
229
230                 timers7: timers@40001400 {
231                         #address-cells = <1>;
232                         #size-cells = <0>;
233                         compatible = "st,stm32-timers";
234                         reg = <0x40001400 0x400>;
235                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
236                         clock-names = "int";
237                         status = "disabled";
238
239                         timer@6 {
240                                 compatible = "st,stm32-timer-trigger";
241                                 reg = <6>;
242                                 status = "disabled";
243                         };
244                 };
245
246                 timers12: timers@40001800 {
247                         #address-cells = <1>;
248                         #size-cells = <0>;
249                         compatible = "st,stm32-timers";
250                         reg = <0x40001800 0x400>;
251                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
252                         clock-names = "int";
253                         status = "disabled";
254
255                         pwm {
256                                 compatible = "st,stm32-pwm";
257                                 status = "disabled";
258                         };
259
260                         timer@11 {
261                                 compatible = "st,stm32-timer-trigger";
262                                 reg = <11>;
263                                 status = "disabled";
264                         };
265                 };
266
267                 timers13: timers@40001c00 {
268                         #address-cells = <1>;
269                         #size-cells = <0>;
270                         compatible = "st,stm32-timers";
271                         reg = <0x40001C00 0x400>;
272                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
273                         clock-names = "int";
274                         status = "disabled";
275
276                         pwm {
277                                 compatible = "st,stm32-pwm";
278                                 status = "disabled";
279                         };
280                 };
281
282                 timers14: timers@40002000 {
283                         #address-cells = <1>;
284                         #size-cells = <0>;
285                         compatible = "st,stm32-timers";
286                         reg = <0x40002000 0x400>;
287                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
288                         clock-names = "int";
289                         status = "disabled";
290
291                         pwm {
292                                 compatible = "st,stm32-pwm";
293                                 status = "disabled";
294                         };
295                 };
296
297                 rtc: rtc@40002800 {
298                         compatible = "st,stm32-rtc";
299                         reg = <0x40002800 0x400>;
300                         clocks = <&rcc 1 CLK_RTC>;
301                         clock-names = "ck_rtc";
302                         assigned-clocks = <&rcc 1 CLK_RTC>;
303                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
304                         interrupt-parent = <&exti>;
305                         interrupts = <17 1>;
306                         interrupt-names = "alarm";
307                         st,syscfg = <&pwrcfg 0x00 0x100>;
308                         status = "disabled";
309                 };
310
311                 iwdg: watchdog@40003000 {
312                         compatible = "st,stm32-iwdg";
313                         reg = <0x40003000 0x400>;
314                         clocks = <&clk_lsi>;
315                         clock-names = "lsi";
316                         status = "disabled";
317                 };
318
319                 spi2: spi@40003800 {
320                         #address-cells = <1>;
321                         #size-cells = <0>;
322                         compatible = "st,stm32f4-spi";
323                         reg = <0x40003800 0x400>;
324                         interrupts = <36>;
325                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
326                         status = "disabled";
327                 };
328
329                 spi3: spi@40003c00 {
330                         #address-cells = <1>;
331                         #size-cells = <0>;
332                         compatible = "st,stm32f4-spi";
333                         reg = <0x40003c00 0x400>;
334                         interrupts = <51>;
335                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
336                         status = "disabled";
337                 };
338
339                 usart2: serial@40004400 {
340                         compatible = "st,stm32-uart";
341                         reg = <0x40004400 0x400>;
342                         interrupts = <38>;
343                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
344                         status = "disabled";
345                 };
346
347                 usart3: serial@40004800 {
348                         compatible = "st,stm32-uart";
349                         reg = <0x40004800 0x400>;
350                         interrupts = <39>;
351                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
352                         status = "disabled";
353                         dmas = <&dma1 1 4 0x400 0x0>,
354                                <&dma1 3 4 0x400 0x0>;
355                         dma-names = "rx", "tx";
356                 };
357
358                 usart4: serial@40004c00 {
359                         compatible = "st,stm32-uart";
360                         reg = <0x40004c00 0x400>;
361                         interrupts = <52>;
362                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
363                         status = "disabled";
364                 };
365
366                 usart5: serial@40005000 {
367                         compatible = "st,stm32-uart";
368                         reg = <0x40005000 0x400>;
369                         interrupts = <53>;
370                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
371                         status = "disabled";
372                 };
373
374                 i2c1: i2c@40005400 {
375                         compatible = "st,stm32f4-i2c";
376                         reg = <0x40005400 0x400>;
377                         interrupts = <31>,
378                                      <32>;
379                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
380                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
381                         #address-cells = <1>;
382                         #size-cells = <0>;
383                         status = "disabled";
384                 };
385
386                 dac: dac@40007400 {
387                         compatible = "st,stm32f4-dac-core";
388                         reg = <0x40007400 0x400>;
389                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
390                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
391                         clock-names = "pclk";
392                         #address-cells = <1>;
393                         #size-cells = <0>;
394                         status = "disabled";
395
396                         dac1: dac@1 {
397                                 compatible = "st,stm32-dac";
398                                 #io-channels-cells = <1>;
399                                 reg = <1>;
400                                 status = "disabled";
401                         };
402
403                         dac2: dac@2 {
404                                 compatible = "st,stm32-dac";
405                                 #io-channels-cells = <1>;
406                                 reg = <2>;
407                                 status = "disabled";
408                         };
409                 };
410
411                 usart7: serial@40007800 {
412                         compatible = "st,stm32-uart";
413                         reg = <0x40007800 0x400>;
414                         interrupts = <82>;
415                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
416                         status = "disabled";
417                 };
418
419                 usart8: serial@40007c00 {
420                         compatible = "st,stm32-uart";
421                         reg = <0x40007c00 0x400>;
422                         interrupts = <83>;
423                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
424                         status = "disabled";
425                 };
426
427                 timers1: timers@40010000 {
428                         #address-cells = <1>;
429                         #size-cells = <0>;
430                         compatible = "st,stm32-timers";
431                         reg = <0x40010000 0x400>;
432                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
433                         clock-names = "int";
434                         status = "disabled";
435
436                         pwm {
437                                 compatible = "st,stm32-pwm";
438                                 status = "disabled";
439                         };
440
441                         timer@0 {
442                                 compatible = "st,stm32-timer-trigger";
443                                 reg = <0>;
444                                 status = "disabled";
445                         };
446                 };
447
448                 timers8: timers@40010400 {
449                         #address-cells = <1>;
450                         #size-cells = <0>;
451                         compatible = "st,stm32-timers";
452                         reg = <0x40010400 0x400>;
453                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
454                         clock-names = "int";
455                         status = "disabled";
456
457                         pwm {
458                                 compatible = "st,stm32-pwm";
459                                 status = "disabled";
460                         };
461
462                         timer@7 {
463                                 compatible = "st,stm32-timer-trigger";
464                                 reg = <7>;
465                                 status = "disabled";
466                         };
467                 };
468
469                 usart1: serial@40011000 {
470                         compatible = "st,stm32-uart";
471                         reg = <0x40011000 0x400>;
472                         interrupts = <37>;
473                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
474                         status = "disabled";
475                         dmas = <&dma2 2 4 0x400 0x0>,
476                                <&dma2 7 4 0x400 0x0>;
477                         dma-names = "rx", "tx";
478                 };
479
480                 usart6: serial@40011400 {
481                         compatible = "st,stm32-uart";
482                         reg = <0x40011400 0x400>;
483                         interrupts = <71>;
484                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
485                         status = "disabled";
486                 };
487
488                 adc: adc@40012000 {
489                         compatible = "st,stm32f4-adc-core";
490                         reg = <0x40012000 0x400>;
491                         interrupts = <18>;
492                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
493                         clock-names = "adc";
494                         interrupt-controller;
495                         #interrupt-cells = <1>;
496                         #address-cells = <1>;
497                         #size-cells = <0>;
498                         status = "disabled";
499
500                         adc1: adc@0 {
501                                 compatible = "st,stm32f4-adc";
502                                 #io-channel-cells = <1>;
503                                 reg = <0x0>;
504                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
505                                 interrupt-parent = <&adc>;
506                                 interrupts = <0>;
507                                 dmas = <&dma2 0 0 0x400 0x0>;
508                                 dma-names = "rx";
509                                 status = "disabled";
510                         };
511
512                         adc2: adc@100 {
513                                 compatible = "st,stm32f4-adc";
514                                 #io-channel-cells = <1>;
515                                 reg = <0x100>;
516                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
517                                 interrupt-parent = <&adc>;
518                                 interrupts = <1>;
519                                 dmas = <&dma2 3 1 0x400 0x0>;
520                                 dma-names = "rx";
521                                 status = "disabled";
522                         };
523
524                         adc3: adc@200 {
525                                 compatible = "st,stm32f4-adc";
526                                 #io-channel-cells = <1>;
527                                 reg = <0x200>;
528                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
529                                 interrupt-parent = <&adc>;
530                                 interrupts = <2>;
531                                 dmas = <&dma2 1 2 0x400 0x0>;
532                                 dma-names = "rx";
533                                 status = "disabled";
534                         };
535                 };
536
537                 sdio: sdio@40012c00 {
538                         compatible = "arm,pl180", "arm,primecell";
539                         arm,primecell-periphid = <0x00880180>;
540                         reg = <0x40012c00 0x400>;
541                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
542                         clock-names = "apb_pclk";
543                         interrupts = <49>;
544                         max-frequency = <48000000>;
545                         status = "disabled";
546                 };
547
548                 spi1: spi@40013000 {
549                         #address-cells = <1>;
550                         #size-cells = <0>;
551                         compatible = "st,stm32f4-spi";
552                         reg = <0x40013000 0x400>;
553                         interrupts = <35>;
554                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
555                         status = "disabled";
556                 };
557
558                 spi4: spi@40013400 {
559                         #address-cells = <1>;
560                         #size-cells = <0>;
561                         compatible = "st,stm32f4-spi";
562                         reg = <0x40013400 0x400>;
563                         interrupts = <84>;
564                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
565                         status = "disabled";
566                 };
567
568                 syscfg: system-config@40013800 {
569                         compatible = "syscon";
570                         reg = <0x40013800 0x400>;
571                 };
572
573                 exti: interrupt-controller@40013c00 {
574                         compatible = "st,stm32-exti";
575                         interrupt-controller;
576                         #interrupt-cells = <2>;
577                         reg = <0x40013C00 0x400>;
578                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
579                 };
580
581                 timers9: timers@40014000 {
582                         #address-cells = <1>;
583                         #size-cells = <0>;
584                         compatible = "st,stm32-timers";
585                         reg = <0x40014000 0x400>;
586                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
587                         clock-names = "int";
588                         status = "disabled";
589
590                         pwm {
591                                 compatible = "st,stm32-pwm";
592                                 status = "disabled";
593                         };
594
595                         timer@8 {
596                                 compatible = "st,stm32-timer-trigger";
597                                 reg = <8>;
598                                 status = "disabled";
599                         };
600                 };
601
602                 timers10: timers@40014400 {
603                         #address-cells = <1>;
604                         #size-cells = <0>;
605                         compatible = "st,stm32-timers";
606                         reg = <0x40014400 0x400>;
607                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
608                         clock-names = "int";
609                         status = "disabled";
610
611                         pwm {
612                                 compatible = "st,stm32-pwm";
613                                 status = "disabled";
614                         };
615                 };
616
617                 timers11: timers@40014800 {
618                         #address-cells = <1>;
619                         #size-cells = <0>;
620                         compatible = "st,stm32-timers";
621                         reg = <0x40014800 0x400>;
622                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
623                         clock-names = "int";
624                         status = "disabled";
625
626                         pwm {
627                                 compatible = "st,stm32-pwm";
628                                 status = "disabled";
629                         };
630                 };
631
632                 spi5: spi@40015000 {
633                         #address-cells = <1>;
634                         #size-cells = <0>;
635                         compatible = "st,stm32f4-spi";
636                         reg = <0x40015000 0x400>;
637                         interrupts = <85>;
638                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
639                         status = "disabled";
640                 };
641
642                 spi6: spi@40015400 {
643                         #address-cells = <1>;
644                         #size-cells = <0>;
645                         compatible = "st,stm32f4-spi";
646                         reg = <0x40015400 0x400>;
647                         interrupts = <86>;
648                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
649                         status = "disabled";
650                 };
651
652                 pwrcfg: power-config@40007000 {
653                         compatible = "syscon";
654                         reg = <0x40007000 0x400>;
655                 };
656
657                 ltdc: display-controller@40016800 {
658                         compatible = "st,stm32-ltdc";
659                         reg = <0x40016800 0x200>;
660                         interrupts = <88>, <89>;
661                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
662                         clocks = <&rcc 1 CLK_LCD>;
663                         clock-names = "lcd";
664                         status = "disabled";
665                 };
666
667                 crc: crc@40023000 {
668                         compatible = "st,stm32f4-crc";
669                         reg = <0x40023000 0x400>;
670                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
671                         status = "disabled";
672                 };
673
674                 rcc: rcc@40023810 {
675                         #reset-cells = <1>;
676                         #clock-cells = <2>;
677                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
678                         reg = <0x40023800 0x400>;
679                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
680                         st,syscfg = <&pwrcfg>;
681                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
682                         assigned-clock-rates = <1000000>;
683                 };
684
685                 dma1: dma-controller@40026000 {
686                         compatible = "st,stm32-dma";
687                         reg = <0x40026000 0x400>;
688                         interrupts = <11>,
689                                      <12>,
690                                      <13>,
691                                      <14>,
692                                      <15>,
693                                      <16>,
694                                      <17>,
695                                      <47>;
696                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
697                         #dma-cells = <4>;
698                 };
699
700                 dma2: dma-controller@40026400 {
701                         compatible = "st,stm32-dma";
702                         reg = <0x40026400 0x400>;
703                         interrupts = <56>,
704                                      <57>,
705                                      <58>,
706                                      <59>,
707                                      <60>,
708                                      <68>,
709                                      <69>,
710                                      <70>;
711                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
712                         #dma-cells = <4>;
713                         st,mem2mem;
714                 };
715
716                 mac: ethernet@40028000 {
717                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
718                         reg = <0x40028000 0x8000>;
719                         reg-names = "stmmaceth";
720                         interrupts = <61>;
721                         interrupt-names = "macirq";
722                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
723                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
724                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
725                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
726                         st,syscon = <&syscfg 0x4>;
727                         snps,pbl = <8>;
728                         snps,mixed-burst;
729                         status = "disabled";
730                 };
731
732                 usbotg_hs: usb@40040000 {
733                         compatible = "snps,dwc2";
734                         reg = <0x40040000 0x40000>;
735                         interrupts = <77>;
736                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
737                         clock-names = "otg";
738                         status = "disabled";
739                 };
740
741                 usbotg_fs: usb@50000000 {
742                         compatible = "st,stm32f4x9-fsotg";
743                         reg = <0x50000000 0x40000>;
744                         interrupts = <67>;
745                         clocks = <&rcc 0 39>;
746                         clock-names = "otg";
747                         status = "disabled";
748                 };
749
750                 dcmi: dcmi@50050000 {
751                         compatible = "st,stm32-dcmi";
752                         reg = <0x50050000 0x400>;
753                         interrupts = <78>;
754                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
755                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
756                         clock-names = "mclk";
757                         pinctrl-names = "default";
758                         pinctrl-0 = <&dcmi_pins>;
759                         dmas = <&dma2 1 1 0x414 0x3>;
760                         dma-names = "tx";
761                         status = "disabled";
762                 };
763
764                 rng: rng@50060800 {
765                         compatible = "st,stm32-rng";
766                         reg = <0x50060800 0x400>;
767                         interrupts = <80>;
768                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
769
770                 };
771         };
772 };
773
774 &systick {
775         clocks = <&rcc 1 SYSTICK>;
776         status = "okay";
777 };