Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[muen/linux.git] / arch / arm / boot / dts / stm32mp157c.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5  */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
9
10 / {
11         #address-cells = <1>;
12         #size-cells = <1>;
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17
18                 cpu0: cpu@0 {
19                         compatible = "arm,cortex-a7";
20                         device_type = "cpu";
21                         reg = <0>;
22                 };
23
24                 cpu1: cpu@1 {
25                         compatible = "arm,cortex-a7";
26                         device_type = "cpu";
27                         reg = <1>;
28                 };
29         };
30
31         psci {
32                 compatible = "arm,psci";
33                 method = "smc";
34                 cpu_off = <0x84000002>;
35                 cpu_on = <0x84000003>;
36         };
37
38         intc: interrupt-controller@a0021000 {
39                 compatible = "arm,cortex-a7-gic";
40                 #interrupt-cells = <3>;
41                 interrupt-controller;
42                 reg = <0xa0021000 0x1000>,
43                       <0xa0022000 0x2000>;
44         };
45
46         timer {
47                 compatible = "arm,armv7-timer";
48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52                 interrupt-parent = <&intc>;
53         };
54
55         clocks {
56                 clk_hse: clk-hse {
57                         #clock-cells = <0>;
58                         compatible = "fixed-clock";
59                         clock-frequency = <24000000>;
60                 };
61
62                 clk_hsi: clk-hsi {
63                         #clock-cells = <0>;
64                         compatible = "fixed-clock";
65                         clock-frequency = <64000000>;
66                 };
67
68                 clk_lse: clk-lse {
69                         #clock-cells = <0>;
70                         compatible = "fixed-clock";
71                         clock-frequency = <32768>;
72                 };
73
74                 clk_lsi: clk-lsi {
75                         #clock-cells = <0>;
76                         compatible = "fixed-clock";
77                         clock-frequency = <32000>;
78                 };
79
80                 clk_csi: clk-csi {
81                         #clock-cells = <0>;
82                         compatible = "fixed-clock";
83                         clock-frequency = <4000000>;
84                 };
85         };
86
87         soc {
88                 compatible = "simple-bus";
89                 #address-cells = <1>;
90                 #size-cells = <1>;
91                 interrupt-parent = <&intc>;
92                 ranges;
93
94                 timers2: timer@40000000 {
95                         #address-cells = <1>;
96                         #size-cells = <0>;
97                         compatible = "st,stm32-timers";
98                         reg = <0x40000000 0x400>;
99                         clocks = <&rcc TIM2_K>;
100                         clock-names = "int";
101                         status = "disabled";
102
103                         pwm {
104                                 compatible = "st,stm32-pwm";
105                                 status = "disabled";
106                         };
107
108                         timer@1 {
109                                 compatible = "st,stm32h7-timer-trigger";
110                                 reg = <1>;
111                                 status = "disabled";
112                         };
113                 };
114
115                 timers3: timer@40001000 {
116                         #address-cells = <1>;
117                         #size-cells = <0>;
118                         compatible = "st,stm32-timers";
119                         reg = <0x40001000 0x400>;
120                         clocks = <&rcc TIM3_K>;
121                         clock-names = "int";
122                         status = "disabled";
123
124                         pwm {
125                                 compatible = "st,stm32-pwm";
126                                 status = "disabled";
127                         };
128
129                         timer@2 {
130                                 compatible = "st,stm32h7-timer-trigger";
131                                 reg = <2>;
132                                 status = "disabled";
133                         };
134                 };
135
136                 timers4: timer@40002000 {
137                         #address-cells = <1>;
138                         #size-cells = <0>;
139                         compatible = "st,stm32-timers";
140                         reg = <0x40002000 0x400>;
141                         clocks = <&rcc TIM4_K>;
142                         clock-names = "int";
143                         status = "disabled";
144
145                         pwm {
146                                 compatible = "st,stm32-pwm";
147                                 status = "disabled";
148                         };
149
150                         timer@3 {
151                                 compatible = "st,stm32h7-timer-trigger";
152                                 reg = <3>;
153                                 status = "disabled";
154                         };
155                 };
156
157                 timers5: timer@40003000 {
158                         #address-cells = <1>;
159                         #size-cells = <0>;
160                         compatible = "st,stm32-timers";
161                         reg = <0x40003000 0x400>;
162                         clocks = <&rcc TIM5_K>;
163                         clock-names = "int";
164                         status = "disabled";
165
166                         pwm {
167                                 compatible = "st,stm32-pwm";
168                                 status = "disabled";
169                         };
170
171                         timer@4 {
172                                 compatible = "st,stm32h7-timer-trigger";
173                                 reg = <4>;
174                                 status = "disabled";
175                         };
176                 };
177
178                 timers6: timer@40004000 {
179                         #address-cells = <1>;
180                         #size-cells = <0>;
181                         compatible = "st,stm32-timers";
182                         reg = <0x40004000 0x400>;
183                         clocks = <&rcc TIM6_K>;
184                         clock-names = "int";
185                         status = "disabled";
186
187                         timer@5 {
188                                 compatible = "st,stm32h7-timer-trigger";
189                                 reg = <5>;
190                                 status = "disabled";
191                         };
192                 };
193
194                 timers7: timer@40005000 {
195                         #address-cells = <1>;
196                         #size-cells = <0>;
197                         compatible = "st,stm32-timers";
198                         reg = <0x40005000 0x400>;
199                         clocks = <&rcc TIM7_K>;
200                         clock-names = "int";
201                         status = "disabled";
202
203                         timer@6 {
204                                 compatible = "st,stm32h7-timer-trigger";
205                                 reg = <6>;
206                                 status = "disabled";
207                         };
208                 };
209
210                 timers12: timer@40006000 {
211                         #address-cells = <1>;
212                         #size-cells = <0>;
213                         compatible = "st,stm32-timers";
214                         reg = <0x40006000 0x400>;
215                         clocks = <&rcc TIM12_K>;
216                         clock-names = "int";
217                         status = "disabled";
218
219                         pwm {
220                                 compatible = "st,stm32-pwm";
221                                 status = "disabled";
222                         };
223
224                         timer@11 {
225                                 compatible = "st,stm32h7-timer-trigger";
226                                 reg = <11>;
227                                 status = "disabled";
228                         };
229                 };
230
231                 timers13: timer@40007000 {
232                         #address-cells = <1>;
233                         #size-cells = <0>;
234                         compatible = "st,stm32-timers";
235                         reg = <0x40007000 0x400>;
236                         clocks = <&rcc TIM13_K>;
237                         clock-names = "int";
238                         status = "disabled";
239
240                         pwm {
241                                 compatible = "st,stm32-pwm";
242                                 status = "disabled";
243                         };
244
245                         timer@12 {
246                                 compatible = "st,stm32h7-timer-trigger";
247                                 reg = <12>;
248                                 status = "disabled";
249                         };
250                 };
251
252                 timers14: timer@40008000 {
253                         #address-cells = <1>;
254                         #size-cells = <0>;
255                         compatible = "st,stm32-timers";
256                         reg = <0x40008000 0x400>;
257                         clocks = <&rcc TIM14_K>;
258                         clock-names = "int";
259                         status = "disabled";
260
261                         pwm {
262                                 compatible = "st,stm32-pwm";
263                                 status = "disabled";
264                         };
265
266                         timer@13 {
267                                 compatible = "st,stm32h7-timer-trigger";
268                                 reg = <13>;
269                                 status = "disabled";
270                         };
271                 };
272
273                 lptimer1: timer@40009000 {
274                         #address-cells = <1>;
275                         #size-cells = <0>;
276                         compatible = "st,stm32-lptimer";
277                         reg = <0x40009000 0x400>;
278                         clocks = <&rcc LPTIM1_K>;
279                         clock-names = "mux";
280                         status = "disabled";
281
282                         pwm {
283                                 compatible = "st,stm32-pwm-lp";
284                                 #pwm-cells = <3>;
285                                 status = "disabled";
286                         };
287
288                         trigger@0 {
289                                 compatible = "st,stm32-lptimer-trigger";
290                                 reg = <0>;
291                                 status = "disabled";
292                         };
293
294                         counter {
295                                 compatible = "st,stm32-lptimer-counter";
296                                 status = "disabled";
297                         };
298                 };
299
300                 spi2: spi@4000b000 {
301                         #address-cells = <1>;
302                         #size-cells = <0>;
303                         compatible = "st,stm32h7-spi";
304                         reg = <0x4000b000 0x400>;
305                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
306                         clocks = <&rcc SPI2_K>;
307                         resets = <&rcc SPI2_R>;
308                         dmas = <&dmamux1 39 0x400 0x05>,
309                                <&dmamux1 40 0x400 0x05>;
310                         dma-names = "rx", "tx";
311                         status = "disabled";
312                 };
313
314                 spi3: spi@4000c000 {
315                         #address-cells = <1>;
316                         #size-cells = <0>;
317                         compatible = "st,stm32h7-spi";
318                         reg = <0x4000c000 0x400>;
319                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
320                         clocks = <&rcc SPI3_K>;
321                         resets = <&rcc SPI3_R>;
322                         dmas = <&dmamux1 61 0x400 0x05>,
323                                <&dmamux1 62 0x400 0x05>;
324                         dma-names = "rx", "tx";
325                         status = "disabled";
326                 };
327
328                 usart2: serial@4000e000 {
329                         compatible = "st,stm32h7-uart";
330                         reg = <0x4000e000 0x400>;
331                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
332                         clocks = <&rcc USART2_K>;
333                         status = "disabled";
334                 };
335
336                 usart3: serial@4000f000 {
337                         compatible = "st,stm32h7-uart";
338                         reg = <0x4000f000 0x400>;
339                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
340                         clocks = <&rcc USART3_K>;
341                         status = "disabled";
342                 };
343
344                 uart4: serial@40010000 {
345                         compatible = "st,stm32h7-uart";
346                         reg = <0x40010000 0x400>;
347                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
348                         clocks = <&rcc UART4_K>;
349                         status = "disabled";
350                 };
351
352                 uart5: serial@40011000 {
353                         compatible = "st,stm32h7-uart";
354                         reg = <0x40011000 0x400>;
355                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
356                         clocks = <&rcc UART5_K>;
357                         status = "disabled";
358                 };
359
360                 i2c1: i2c@40012000 {
361                         compatible = "st,stm32f7-i2c";
362                         reg = <0x40012000 0x400>;
363                         interrupt-names = "event", "error";
364                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
365                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
366                         clocks = <&rcc I2C1_K>;
367                         resets = <&rcc I2C1_R>;
368                         #address-cells = <1>;
369                         #size-cells = <0>;
370                         status = "disabled";
371                 };
372
373                 i2c2: i2c@40013000 {
374                         compatible = "st,stm32f7-i2c";
375                         reg = <0x40013000 0x400>;
376                         interrupt-names = "event", "error";
377                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
378                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
379                         clocks = <&rcc I2C2_K>;
380                         resets = <&rcc I2C2_R>;
381                         #address-cells = <1>;
382                         #size-cells = <0>;
383                         status = "disabled";
384                 };
385
386                 i2c3: i2c@40014000 {
387                         compatible = "st,stm32f7-i2c";
388                         reg = <0x40014000 0x400>;
389                         interrupt-names = "event", "error";
390                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
391                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
392                         clocks = <&rcc I2C3_K>;
393                         resets = <&rcc I2C3_R>;
394                         #address-cells = <1>;
395                         #size-cells = <0>;
396                         status = "disabled";
397                 };
398
399                 i2c5: i2c@40015000 {
400                         compatible = "st,stm32f7-i2c";
401                         reg = <0x40015000 0x400>;
402                         interrupt-names = "event", "error";
403                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
404                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
405                         clocks = <&rcc I2C5_K>;
406                         resets = <&rcc I2C5_R>;
407                         #address-cells = <1>;
408                         #size-cells = <0>;
409                         status = "disabled";
410                 };
411
412                 cec: cec@40016000 {
413                         compatible = "st,stm32-cec";
414                         reg = <0x40016000 0x400>;
415                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
416                         clocks = <&rcc CEC_K>, <&clk_lse>;
417                         clock-names = "cec", "hdmi-cec";
418                         status = "disabled";
419                 };
420
421                 dac: dac@40017000 {
422                         compatible = "st,stm32h7-dac-core";
423                         reg = <0x40017000 0x400>;
424                         clocks = <&rcc DAC12>;
425                         clock-names = "pclk";
426                         #address-cells = <1>;
427                         #size-cells = <0>;
428                         status = "disabled";
429
430                         dac1: dac@1 {
431                                 compatible = "st,stm32-dac";
432                                 #io-channels-cells = <1>;
433                                 reg = <1>;
434                                 status = "disabled";
435                         };
436
437                         dac2: dac@2 {
438                                 compatible = "st,stm32-dac";
439                                 #io-channels-cells = <1>;
440                                 reg = <2>;
441                                 status = "disabled";
442                         };
443                 };
444
445                 uart7: serial@40018000 {
446                         compatible = "st,stm32h7-uart";
447                         reg = <0x40018000 0x400>;
448                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
449                         clocks = <&rcc UART7_K>;
450                         status = "disabled";
451                 };
452
453                 uart8: serial@40019000 {
454                         compatible = "st,stm32h7-uart";
455                         reg = <0x40019000 0x400>;
456                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
457                         clocks = <&rcc UART8_K>;
458                         status = "disabled";
459                 };
460
461                 timers1: timer@44000000 {
462                         #address-cells = <1>;
463                         #size-cells = <0>;
464                         compatible = "st,stm32-timers";
465                         reg = <0x44000000 0x400>;
466                         clocks = <&rcc TIM1_K>;
467                         clock-names = "int";
468                         status = "disabled";
469
470                         pwm {
471                                 compatible = "st,stm32-pwm";
472                                 status = "disabled";
473                         };
474
475                         timer@0 {
476                                 compatible = "st,stm32h7-timer-trigger";
477                                 reg = <0>;
478                                 status = "disabled";
479                         };
480                 };
481
482                 timers8: timer@44001000 {
483                         #address-cells = <1>;
484                         #size-cells = <0>;
485                         compatible = "st,stm32-timers";
486                         reg = <0x44001000 0x400>;
487                         clocks = <&rcc TIM8_K>;
488                         clock-names = "int";
489                         status = "disabled";
490
491                         pwm {
492                                 compatible = "st,stm32-pwm";
493                                 status = "disabled";
494                         };
495
496                         timer@7 {
497                                 compatible = "st,stm32h7-timer-trigger";
498                                 reg = <7>;
499                                 status = "disabled";
500                         };
501                 };
502
503                 usart6: serial@44003000 {
504                         compatible = "st,stm32h7-uart";
505                         reg = <0x44003000 0x400>;
506                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
507                         clocks = <&rcc USART6_K>;
508                         status = "disabled";
509                 };
510
511                 spi1: spi@44004000 {
512                         #address-cells = <1>;
513                         #size-cells = <0>;
514                         compatible = "st,stm32h7-spi";
515                         reg = <0x44004000 0x400>;
516                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
517                         clocks = <&rcc SPI1_K>;
518                         resets = <&rcc SPI1_R>;
519                         dmas = <&dmamux1 37 0x400 0x05>,
520                                <&dmamux1 38 0x400 0x05>;
521                         dma-names = "rx", "tx";
522                         status = "disabled";
523                 };
524
525                 spi4: spi@44005000 {
526                         #address-cells = <1>;
527                         #size-cells = <0>;
528                         compatible = "st,stm32h7-spi";
529                         reg = <0x44005000 0x400>;
530                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
531                         clocks = <&rcc SPI4_K>;
532                         resets = <&rcc SPI4_R>;
533                         dmas = <&dmamux1 83 0x400 0x05>,
534                                <&dmamux1 84 0x400 0x05>;
535                         dma-names = "rx", "tx";
536                         status = "disabled";
537                 };
538
539                 timers15: timer@44006000 {
540                         #address-cells = <1>;
541                         #size-cells = <0>;
542                         compatible = "st,stm32-timers";
543                         reg = <0x44006000 0x400>;
544                         clocks = <&rcc TIM15_K>;
545                         clock-names = "int";
546                         status = "disabled";
547
548                         pwm {
549                                 compatible = "st,stm32-pwm";
550                                 status = "disabled";
551                         };
552
553                         timer@14 {
554                                 compatible = "st,stm32h7-timer-trigger";
555                                 reg = <14>;
556                                 status = "disabled";
557                         };
558                 };
559
560                 timers16: timer@44007000 {
561                         #address-cells = <1>;
562                         #size-cells = <0>;
563                         compatible = "st,stm32-timers";
564                         reg = <0x44007000 0x400>;
565                         clocks = <&rcc TIM16_K>;
566                         clock-names = "int";
567                         status = "disabled";
568
569                         pwm {
570                                 compatible = "st,stm32-pwm";
571                                 status = "disabled";
572                         };
573                         timer@15 {
574                                 compatible = "st,stm32h7-timer-trigger";
575                                 reg = <15>;
576                                 status = "disabled";
577                         };
578                 };
579
580                 timers17: timer@44008000 {
581                         #address-cells = <1>;
582                         #size-cells = <0>;
583                         compatible = "st,stm32-timers";
584                         reg = <0x44008000 0x400>;
585                         clocks = <&rcc TIM17_K>;
586                         clock-names = "int";
587                         status = "disabled";
588
589                         pwm {
590                                 compatible = "st,stm32-pwm";
591                                 status = "disabled";
592                         };
593
594                         timer@16 {
595                                 compatible = "st,stm32h7-timer-trigger";
596                                 reg = <16>;
597                                 status = "disabled";
598                         };
599                 };
600
601                 spi5: spi@44009000 {
602                         #address-cells = <1>;
603                         #size-cells = <0>;
604                         compatible = "st,stm32h7-spi";
605                         reg = <0x44009000 0x400>;
606                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
607                         clocks = <&rcc SPI5_K>;
608                         resets = <&rcc SPI5_R>;
609                         dmas = <&dmamux1 85 0x400 0x05>,
610                                <&dmamux1 86 0x400 0x05>;
611                         dma-names = "rx", "tx";
612                         status = "disabled";
613                 };
614
615                 dfsdm: dfsdm@4400d000 {
616                         compatible = "st,stm32mp1-dfsdm";
617                         reg = <0x4400d000 0x800>;
618                         clocks = <&rcc DFSDM_K>;
619                         clock-names = "dfsdm";
620                         #address-cells = <1>;
621                         #size-cells = <0>;
622                         status = "disabled";
623
624                         dfsdm0: filter@0 {
625                                 compatible = "st,stm32-dfsdm-adc";
626                                 #io-channel-cells = <1>;
627                                 reg = <0>;
628                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
629                                 dmas = <&dmamux1 101 0x400 0x01>;
630                                 dma-names = "rx";
631                                 status = "disabled";
632                         };
633
634                         dfsdm1: filter@1 {
635                                 compatible = "st,stm32-dfsdm-adc";
636                                 #io-channel-cells = <1>;
637                                 reg = <1>;
638                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
639                                 dmas = <&dmamux1 102 0x400 0x01>;
640                                 dma-names = "rx";
641                                 status = "disabled";
642                         };
643
644                         dfsdm2: filter@2 {
645                                 compatible = "st,stm32-dfsdm-adc";
646                                 #io-channel-cells = <1>;
647                                 reg = <2>;
648                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
649                                 dmas = <&dmamux1 103 0x400 0x01>;
650                                 dma-names = "rx";
651                                 status = "disabled";
652                         };
653
654                         dfsdm3: filter@3 {
655                                 compatible = "st,stm32-dfsdm-adc";
656                                 #io-channel-cells = <1>;
657                                 reg = <3>;
658                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
659                                 dmas = <&dmamux1 104 0x400 0x01>;
660                                 dma-names = "rx";
661                                 status = "disabled";
662                         };
663
664                         dfsdm4: filter@4 {
665                                 compatible = "st,stm32-dfsdm-adc";
666                                 #io-channel-cells = <1>;
667                                 reg = <4>;
668                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
669                                 dmas = <&dmamux1 91 0x400 0x01>;
670                                 dma-names = "rx";
671                                 status = "disabled";
672                         };
673
674                         dfsdm5: filter@5 {
675                                 compatible = "st,stm32-dfsdm-adc";
676                                 #io-channel-cells = <1>;
677                                 reg = <5>;
678                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
679                                 dmas = <&dmamux1 92 0x400 0x01>;
680                                 dma-names = "rx";
681                                 status = "disabled";
682                         };
683                 };
684
685                 m_can1: can@4400e000 {
686                         compatible = "bosch,m_can";
687                         reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
688                         reg-names = "m_can", "message_ram";
689                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
690                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
691                         interrupt-names = "int0", "int1";
692                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
693                         clock-names = "hclk", "cclk";
694                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
695                         status = "disabled";
696                 };
697
698                 m_can2: can@4400f000 {
699                         compatible = "bosch,m_can";
700                         reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
701                         reg-names = "m_can", "message_ram";
702                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
703                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
704                         interrupt-names = "int0", "int1";
705                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
706                         clock-names = "hclk", "cclk";
707                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
708                         status = "disabled";
709                 };
710
711                 dma1: dma@48000000 {
712                         compatible = "st,stm32-dma";
713                         reg = <0x48000000 0x400>;
714                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
715                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
716                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
717                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
718                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
719                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
720                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
721                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
722                         clocks = <&rcc DMA1>;
723                         #dma-cells = <4>;
724                         st,mem2mem;
725                         dma-requests = <8>;
726                 };
727
728                 dma2: dma@48001000 {
729                         compatible = "st,stm32-dma";
730                         reg = <0x48001000 0x400>;
731                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
732                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
733                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
734                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
735                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
736                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
737                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
738                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
739                         clocks = <&rcc DMA2>;
740                         #dma-cells = <4>;
741                         st,mem2mem;
742                         dma-requests = <8>;
743                 };
744
745                 dmamux1: dma-router@48002000 {
746                         compatible = "st,stm32h7-dmamux";
747                         reg = <0x48002000 0x1c>;
748                         #dma-cells = <3>;
749                         dma-requests = <128>;
750                         dma-masters = <&dma1 &dma2>;
751                         dma-channels = <16>;
752                         clocks = <&rcc DMAMUX>;
753                 };
754
755                 adc: adc@48003000 {
756                         compatible = "st,stm32mp1-adc-core";
757                         reg = <0x48003000 0x400>;
758                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
759                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
760                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
761                         clock-names = "bus", "adc";
762                         interrupt-controller;
763                         #interrupt-cells = <1>;
764                         #address-cells = <1>;
765                         #size-cells = <0>;
766                         status = "disabled";
767
768                         adc1: adc@0 {
769                                 compatible = "st,stm32mp1-adc";
770                                 #io-channel-cells = <1>;
771                                 reg = <0x0>;
772                                 interrupt-parent = <&adc>;
773                                 interrupts = <0>;
774                                 dmas = <&dmamux1 9 0x400 0x01>;
775                                 dma-names = "rx";
776                                 status = "disabled";
777                         };
778
779                         adc2: adc@100 {
780                                 compatible = "st,stm32mp1-adc";
781                                 #io-channel-cells = <1>;
782                                 reg = <0x100>;
783                                 interrupt-parent = <&adc>;
784                                 interrupts = <1>;
785                                 dmas = <&dmamux1 10 0x400 0x01>;
786                                 dma-names = "rx";
787                                 status = "disabled";
788                         };
789                 };
790
791                 usbotg_hs: usb-otg@49000000 {
792                         compatible = "snps,dwc2";
793                         reg = <0x49000000 0x10000>;
794                         clocks = <&rcc USBO_K>;
795                         clock-names = "otg";
796                         resets = <&rcc USBO_R>;
797                         reset-names = "dwc2";
798                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
799                         g-rx-fifo-size = <256>;
800                         g-np-tx-fifo-size = <32>;
801                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
802                         dr_mode = "otg";
803                         status = "disabled";
804                 };
805
806                 rcc: rcc@50000000 {
807                         compatible = "st,stm32mp1-rcc", "syscon";
808                         reg = <0x50000000 0x1000>;
809                         #clock-cells = <1>;
810                         #reset-cells = <1>;
811                 };
812
813                 exti: interrupt-controller@5000d000 {
814                         compatible = "st,stm32mp1-exti", "syscon";
815                         interrupt-controller;
816                         #interrupt-cells = <2>;
817                         reg = <0x5000d000 0x400>;
818                 };
819
820                 syscfg: syscon@50020000 {
821                         compatible = "st,stm32mp157-syscfg", "syscon";
822                         reg = <0x50020000 0x400>;
823                 };
824
825                 lptimer2: timer@50021000 {
826                         #address-cells = <1>;
827                         #size-cells = <0>;
828                         compatible = "st,stm32-lptimer";
829                         reg = <0x50021000 0x400>;
830                         clocks = <&rcc LPTIM2_K>;
831                         clock-names = "mux";
832                         status = "disabled";
833
834                         pwm {
835                                 compatible = "st,stm32-pwm-lp";
836                                 #pwm-cells = <3>;
837                                 status = "disabled";
838                         };
839
840                         trigger@1 {
841                                 compatible = "st,stm32-lptimer-trigger";
842                                 reg = <1>;
843                                 status = "disabled";
844                         };
845
846                         counter {
847                                 compatible = "st,stm32-lptimer-counter";
848                                 status = "disabled";
849                         };
850                 };
851
852                 lptimer3: timer@50022000 {
853                         #address-cells = <1>;
854                         #size-cells = <0>;
855                         compatible = "st,stm32-lptimer";
856                         reg = <0x50022000 0x400>;
857                         clocks = <&rcc LPTIM3_K>;
858                         clock-names = "mux";
859                         status = "disabled";
860
861                         pwm {
862                                 compatible = "st,stm32-pwm-lp";
863                                 #pwm-cells = <3>;
864                                 status = "disabled";
865                         };
866
867                         trigger@2 {
868                                 compatible = "st,stm32-lptimer-trigger";
869                                 reg = <2>;
870                                 status = "disabled";
871                         };
872                 };
873
874                 lptimer4: timer@50023000 {
875                         compatible = "st,stm32-lptimer";
876                         reg = <0x50023000 0x400>;
877                         clocks = <&rcc LPTIM4_K>;
878                         clock-names = "mux";
879                         status = "disabled";
880
881                         pwm {
882                                 compatible = "st,stm32-pwm-lp";
883                                 #pwm-cells = <3>;
884                                 status = "disabled";
885                         };
886                 };
887
888                 lptimer5: timer@50024000 {
889                         compatible = "st,stm32-lptimer";
890                         reg = <0x50024000 0x400>;
891                         clocks = <&rcc LPTIM5_K>;
892                         clock-names = "mux";
893                         status = "disabled";
894
895                         pwm {
896                                 compatible = "st,stm32-pwm-lp";
897                                 #pwm-cells = <3>;
898                                 status = "disabled";
899                         };
900                 };
901
902                 vrefbuf: vrefbuf@50025000 {
903                         compatible = "st,stm32-vrefbuf";
904                         reg = <0x50025000 0x8>;
905                         regulator-min-microvolt = <1500000>;
906                         regulator-max-microvolt = <2500000>;
907                         clocks = <&rcc VREF>;
908                         status = "disabled";
909                 };
910
911                 cryp1: cryp@54001000 {
912                         compatible = "st,stm32mp1-cryp";
913                         reg = <0x54001000 0x400>;
914                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
915                         clocks = <&rcc CRYP1>;
916                         resets = <&rcc CRYP1_R>;
917                         status = "disabled";
918                 };
919
920                 hash1: hash@54002000 {
921                         compatible = "st,stm32f756-hash";
922                         reg = <0x54002000 0x400>;
923                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
924                         clocks = <&rcc HASH1>;
925                         resets = <&rcc HASH1_R>;
926                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>;
927                         dma-names = "in";
928                         dma-maxburst = <2>;
929                         status = "disabled";
930                 };
931
932                 rng1: rng@54003000 {
933                         compatible = "st,stm32-rng";
934                         reg = <0x54003000 0x400>;
935                         clocks = <&rcc RNG1_K>;
936                         resets = <&rcc RNG1_R>;
937                         status = "disabled";
938                 };
939
940                 mdma1: dma@58000000 {
941                         compatible = "st,stm32h7-mdma";
942                         reg = <0x58000000 0x1000>;
943                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
944                         clocks = <&rcc MDMA>;
945                         #dma-cells = <5>;
946                         dma-channels = <32>;
947                         dma-requests = <48>;
948                 };
949
950                 qspi: spi@58003000 {
951                         compatible = "st,stm32f469-qspi";
952                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
953                         reg-names = "qspi", "qspi_mm";
954                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
955                         clocks = <&rcc QSPI_K>;
956                         resets = <&rcc QSPI_R>;
957                         status = "disabled";
958                 };
959
960                 crc1: crc@58009000 {
961                         compatible = "st,stm32f7-crc";
962                         reg = <0x58009000 0x400>;
963                         clocks = <&rcc CRC1>;
964                         status = "disabled";
965                 };
966
967                 stmmac_axi_config_0: stmmac-axi-config {
968                         snps,wr_osr_lmt = <0x7>;
969                         snps,rd_osr_lmt = <0x7>;
970                         snps,blen = <0 0 0 0 16 8 4>;
971                 };
972
973                 ethernet0: ethernet@5800a000 {
974                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
975                         reg = <0x5800a000 0x2000>;
976                         reg-names = "stmmaceth";
977                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
978                         interrupt-names = "macirq";
979                         clock-names = "stmmaceth",
980                                       "mac-clk-tx",
981                                       "mac-clk-rx",
982                                       "ethstp",
983                                       "syscfg-clk";
984                         clocks = <&rcc ETHMAC>,
985                                  <&rcc ETHTX>,
986                                  <&rcc ETHRX>,
987                                  <&rcc ETHSTP>,
988                                  <&rcc SYSCFG>;
989                         st,syscon = <&syscfg 0x4>;
990                         snps,mixed-burst;
991                         snps,pbl = <2>;
992                         snps,axi-config = <&stmmac_axi_config_0>;
993                         snps,tso;
994                         status = "disabled";
995                 };
996
997                 usbh_ohci: usbh-ohci@5800c000 {
998                         compatible = "generic-ohci";
999                         reg = <0x5800c000 0x1000>;
1000                         clocks = <&rcc USBH>;
1001                         resets = <&rcc USBH_R>;
1002                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1003                         status = "disabled";
1004                 };
1005
1006                 usbh_ehci: usbh-ehci@5800d000 {
1007                         compatible = "generic-ehci";
1008                         reg = <0x5800d000 0x1000>;
1009                         clocks = <&rcc USBH>;
1010                         resets = <&rcc USBH_R>;
1011                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1012                         companion = <&usbh_ohci>;
1013                         status = "disabled";
1014                 };
1015
1016                 dsi: dsi@5a000000 {
1017                         compatible = "st,stm32-dsi";
1018                         reg = <0x5a000000 0x800>;
1019                         clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1020                         clock-names = "pclk", "ref", "px_clk";
1021                         resets = <&rcc DSI_R>;
1022                         reset-names = "apb";
1023                         status = "disabled";
1024                 };
1025
1026                 ltdc: display-controller@5a001000 {
1027                         compatible = "st,stm32-ltdc";
1028                         reg = <0x5a001000 0x400>;
1029                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1030                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1031                         clocks = <&rcc LTDC_PX>;
1032                         clock-names = "lcd";
1033                         resets = <&rcc LTDC_R>;
1034                         status = "disabled";
1035                 };
1036
1037                 iwdg2: watchdog@5a002000 {
1038                         compatible = "st,stm32mp1-iwdg";
1039                         reg = <0x5a002000 0x400>;
1040                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1041                         clock-names = "pclk", "lsi";
1042                         status = "disabled";
1043                 };
1044
1045                 usbphyc: usbphyc@5a006000 {
1046                         #address-cells = <1>;
1047                         #size-cells = <0>;
1048                         compatible = "st,stm32mp1-usbphyc";
1049                         reg = <0x5a006000 0x1000>;
1050                         clocks = <&rcc USBPHY_K>;
1051                         resets = <&rcc USBPHY_R>;
1052                         status = "disabled";
1053
1054                         usbphyc_port0: usb-phy@0 {
1055                                 #phy-cells = <0>;
1056                                 reg = <0>;
1057                         };
1058
1059                         usbphyc_port1: usb-phy@1 {
1060                                 #phy-cells = <1>;
1061                                 reg = <1>;
1062                         };
1063                 };
1064
1065                 usart1: serial@5c000000 {
1066                         compatible = "st,stm32h7-uart";
1067                         reg = <0x5c000000 0x400>;
1068                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1069                         clocks = <&rcc USART1_K>;
1070                         status = "disabled";
1071                 };
1072
1073                 spi6: spi@5c001000 {
1074                         #address-cells = <1>;
1075                         #size-cells = <0>;
1076                         compatible = "st,stm32h7-spi";
1077                         reg = <0x5c001000 0x400>;
1078                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1079                         clocks = <&rcc SPI6_K>;
1080                         resets = <&rcc SPI6_R>;
1081                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1082                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1083                         dma-names = "rx", "tx";
1084                         status = "disabled";
1085                 };
1086
1087                 i2c4: i2c@5c002000 {
1088                         compatible = "st,stm32f7-i2c";
1089                         reg = <0x5c002000 0x400>;
1090                         interrupt-names = "event", "error";
1091                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1092                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1093                         clocks = <&rcc I2C4_K>;
1094                         resets = <&rcc I2C4_R>;
1095                         #address-cells = <1>;
1096                         #size-cells = <0>;
1097                         status = "disabled";
1098                 };
1099
1100                 rtc: rtc@5c004000 {
1101                         compatible = "st,stm32mp1-rtc";
1102                         reg = <0x5c004000 0x400>;
1103                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1104                         clock-names = "pclk", "rtc_ck";
1105                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1106                         status = "disabled";
1107                 };
1108
1109                 i2c6: i2c@5c009000 {
1110                         compatible = "st,stm32f7-i2c";
1111                         reg = <0x5c009000 0x400>;
1112                         interrupt-names = "event", "error";
1113                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1114                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1115                         clocks = <&rcc I2C6_K>;
1116                         resets = <&rcc I2C6_R>;
1117                         #address-cells = <1>;
1118                         #size-cells = <0>;
1119                         status = "disabled";
1120                 };
1121         };
1122 };