Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[muen/linux.git] / arch / arm / boot / dts / sun8i-r40.dtsi
1 /*
2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
4  *
5  * This file is dual-licensed: you can use it either under the terms
6  * of the GPL or the X11 license, at your option. Note that this dual
7  * licensing only applies to this file, and not this project as a
8  * whole.
9  *
10  *  a) This file is free software; you can redistribute it and/or
11  *     modify it under the terms of the GNU General Public License as
12  *     published by the Free Software Foundation; either version 2 of the
13  *     License, or (at your option) any later version.
14  *
15  *     This file is distributed in the hope that it will be useful,
16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *     GNU General Public License for more details.
19  *
20  * Or, alternatively,
21  *
22  *  b) Permission is hereby granted, free of charge, to any person
23  *     obtaining a copy of this software and associated documentation
24  *     files (the "Software"), to deal in the Software without
25  *     restriction, including without limitation the rights to use,
26  *     copy, modify, merge, publish, distribute, sublicense, and/or
27  *     sell copies of the Software, and to permit persons to whom the
28  *     Software is furnished to do so, subject to the following
29  *     conditions:
30  *
31  *     The above copyright notice and this permission notice shall be
32  *     included in all copies or substantial portions of the Software.
33  *
34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41  *     OTHER DEALINGS IN THE SOFTWARE.
42  */
43
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49
50 / {
51         #address-cells = <1>;
52         #size-cells = <1>;
53         interrupt-parent = <&gic>;
54
55         clocks {
56                 #address-cells = <1>;
57                 #size-cells = <1>;
58                 ranges;
59
60                 osc24M: osc24M {
61                         #clock-cells = <0>;
62                         compatible = "fixed-clock";
63                         clock-frequency = <24000000>;
64                         clock-output-names = "osc24M";
65                 };
66
67                 osc32k: osc32k {
68                         #clock-cells = <0>;
69                         compatible = "fixed-clock";
70                         clock-frequency = <32768>;
71                         clock-output-names = "osc32k";
72                 };
73         };
74
75         cpus {
76                 #address-cells = <1>;
77                 #size-cells = <0>;
78
79                 cpu@0 {
80                         compatible = "arm,cortex-a7";
81                         device_type = "cpu";
82                         reg = <0>;
83                 };
84
85                 cpu@1 {
86                         compatible = "arm,cortex-a7";
87                         device_type = "cpu";
88                         reg = <1>;
89                 };
90
91                 cpu@2 {
92                         compatible = "arm,cortex-a7";
93                         device_type = "cpu";
94                         reg = <2>;
95                 };
96
97                 cpu@3 {
98                         compatible = "arm,cortex-a7";
99                         device_type = "cpu";
100                         reg = <3>;
101                 };
102         };
103
104         de: display-engine {
105                 compatible = "allwinner,sun8i-r40-display-engine";
106                 allwinner,pipelines = <&mixer0>, <&mixer1>;
107                 status = "disabled";
108         };
109
110         soc {
111                 compatible = "simple-bus";
112                 #address-cells = <1>;
113                 #size-cells = <1>;
114                 ranges;
115
116                 display_clocks: clock@1000000 {
117                         compatible = "allwinner,sun8i-r40-de2-clk",
118                                      "allwinner,sun8i-h3-de2-clk";
119                         reg = <0x01000000 0x100000>;
120                         clocks = <&ccu CLK_DE>,
121                                  <&ccu CLK_BUS_DE>;
122                         clock-names = "mod",
123                                       "bus";
124                         resets = <&ccu RST_BUS_DE>;
125                         #clock-cells = <1>;
126                         #reset-cells = <1>;
127                 };
128
129                 mixer0: mixer@1100000 {
130                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
131                         reg = <0x01100000 0x100000>;
132                         clocks = <&display_clocks CLK_BUS_MIXER0>,
133                                  <&display_clocks CLK_MIXER0>;
134                         clock-names = "bus",
135                                       "mod";
136                         resets = <&display_clocks RST_MIXER0>;
137
138                         ports {
139                                 #address-cells = <1>;
140                                 #size-cells = <0>;
141
142                                 mixer0_out: port@1 {
143                                         reg = <1>;
144                                         mixer0_out_tcon_top: endpoint {
145                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
146                                         };
147                                 };
148                         };
149                 };
150
151                 mixer1: mixer@1200000 {
152                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
153                         reg = <0x01200000 0x100000>;
154                         clocks = <&display_clocks CLK_BUS_MIXER1>,
155                                  <&display_clocks CLK_MIXER1>;
156                         clock-names = "bus",
157                                       "mod";
158                         resets = <&display_clocks RST_WB>;
159
160                         ports {
161                                 #address-cells = <1>;
162                                 #size-cells = <0>;
163
164                                 mixer1_out: port@1 {
165                                         reg = <1>;
166                                         mixer1_out_tcon_top: endpoint {
167                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
168                                         };
169                                 };
170                         };
171                 };
172
173                 nmi_intc: interrupt-controller@1c00030 {
174                         compatible = "allwinner,sun7i-a20-sc-nmi";
175                         interrupt-controller;
176                         #interrupt-cells = <2>;
177                         reg = <0x01c00030 0x0c>;
178                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
179                 };
180
181                 mmc0: mmc@1c0f000 {
182                         compatible = "allwinner,sun8i-r40-mmc",
183                                      "allwinner,sun50i-a64-mmc";
184                         reg = <0x01c0f000 0x1000>;
185                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
186                         clock-names = "ahb", "mmc";
187                         resets = <&ccu RST_BUS_MMC0>;
188                         reset-names = "ahb";
189                         pinctrl-0 = <&mmc0_pins>;
190                         pinctrl-names = "default";
191                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
192                         status = "disabled";
193                         #address-cells = <1>;
194                         #size-cells = <0>;
195                 };
196
197                 mmc1: mmc@1c10000 {
198                         compatible = "allwinner,sun8i-r40-mmc",
199                                      "allwinner,sun50i-a64-mmc";
200                         reg = <0x01c10000 0x1000>;
201                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
202                         clock-names = "ahb", "mmc";
203                         resets = <&ccu RST_BUS_MMC1>;
204                         reset-names = "ahb";
205                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
206                         status = "disabled";
207                         #address-cells = <1>;
208                         #size-cells = <0>;
209                 };
210
211                 mmc2: mmc@1c11000 {
212                         compatible = "allwinner,sun8i-r40-emmc",
213                                      "allwinner,sun50i-a64-emmc";
214                         reg = <0x01c11000 0x1000>;
215                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
216                         clock-names = "ahb", "mmc";
217                         resets = <&ccu RST_BUS_MMC2>;
218                         reset-names = "ahb";
219                         pinctrl-0 = <&mmc2_pins>;
220                         pinctrl-names = "default";
221                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
222                         status = "disabled";
223                         #address-cells = <1>;
224                         #size-cells = <0>;
225                 };
226
227                 mmc3: mmc@1c12000 {
228                         compatible = "allwinner,sun8i-r40-mmc",
229                                      "allwinner,sun50i-a64-mmc";
230                         reg = <0x01c12000 0x1000>;
231                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
232                         clock-names = "ahb", "mmc";
233                         resets = <&ccu RST_BUS_MMC3>;
234                         reset-names = "ahb";
235                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
236                         status = "disabled";
237                         #address-cells = <1>;
238                         #size-cells = <0>;
239                 };
240
241                 usbphy: phy@1c13400 {
242                         compatible = "allwinner,sun8i-r40-usb-phy";
243                         reg = <0x01c13400 0x14>,
244                               <0x01c14800 0x4>,
245                               <0x01c19800 0x4>,
246                               <0x01c1c800 0x4>;
247                         reg-names = "phy_ctrl",
248                                     "pmu0",
249                                     "pmu1",
250                                     "pmu2";
251                         clocks = <&ccu CLK_USB_PHY0>,
252                                  <&ccu CLK_USB_PHY1>,
253                                  <&ccu CLK_USB_PHY2>;
254                         clock-names = "usb0_phy",
255                                       "usb1_phy",
256                                       "usb2_phy";
257                         resets = <&ccu RST_USB_PHY0>,
258                                  <&ccu RST_USB_PHY1>,
259                                  <&ccu RST_USB_PHY2>;
260                         reset-names = "usb0_reset",
261                                       "usb1_reset",
262                                       "usb2_reset";
263                         status = "disabled";
264                         #phy-cells = <1>;
265                 };
266
267                 ehci1: usb@1c19000 {
268                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
269                         reg = <0x01c19000 0x100>;
270                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
271                         clocks = <&ccu CLK_BUS_EHCI1>;
272                         resets = <&ccu RST_BUS_EHCI1>;
273                         phys = <&usbphy 1>;
274                         phy-names = "usb";
275                         status = "disabled";
276                 };
277
278                 ohci1: usb@1c19400 {
279                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
280                         reg = <0x01c19400 0x100>;
281                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
282                         clocks = <&ccu CLK_BUS_OHCI1>,
283                                  <&ccu CLK_USB_OHCI1>;
284                         resets = <&ccu RST_BUS_OHCI1>;
285                         phys = <&usbphy 1>;
286                         phy-names = "usb";
287                         status = "disabled";
288                 };
289
290                 ehci2: usb@1c1c000 {
291                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
292                         reg = <0x01c1c000 0x100>;
293                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
294                         clocks = <&ccu CLK_BUS_EHCI2>;
295                         resets = <&ccu RST_BUS_EHCI2>;
296                         phys = <&usbphy 2>;
297                         phy-names = "usb";
298                         status = "disabled";
299                 };
300
301                 ohci2: usb@1c1c400 {
302                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
303                         reg = <0x01c1c400 0x100>;
304                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
305                         clocks = <&ccu CLK_BUS_OHCI2>,
306                                  <&ccu CLK_USB_OHCI2>;
307                         resets = <&ccu RST_BUS_OHCI2>;
308                         phys = <&usbphy 2>;
309                         phy-names = "usb";
310                         status = "disabled";
311                 };
312
313                 ccu: clock@1c20000 {
314                         compatible = "allwinner,sun8i-r40-ccu";
315                         reg = <0x01c20000 0x400>;
316                         clocks = <&osc24M>, <&osc32k>;
317                         clock-names = "hosc", "losc";
318                         #clock-cells = <1>;
319                         #reset-cells = <1>;
320                 };
321
322                 pio: pinctrl@1c20800 {
323                         compatible = "allwinner,sun8i-r40-pinctrl";
324                         reg = <0x01c20800 0x400>;
325                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
326                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
327                         clock-names = "apb", "hosc", "losc";
328                         gpio-controller;
329                         interrupt-controller;
330                         #interrupt-cells = <3>;
331                         #gpio-cells = <3>;
332
333                         gmac_rgmii_pins: gmac-rgmii-pins {
334                                 pins = "PA0", "PA1", "PA2", "PA3",
335                                        "PA4", "PA5", "PA6", "PA7",
336                                        "PA8", "PA10", "PA11", "PA12",
337                                        "PA13", "PA15", "PA16";
338                                 function = "gmac";
339                                 /*
340                                  * data lines in RGMII mode use DDR mode
341                                  * and need a higher signal drive strength
342                                  */
343                                 drive-strength = <40>;
344                         };
345
346                         i2c0_pins: i2c0-pins {
347                                 pins = "PB0", "PB1";
348                                 function = "i2c0";
349                         };
350
351                         mmc0_pins: mmc0-pins {
352                                 pins = "PF0", "PF1", "PF2",
353                                        "PF3", "PF4", "PF5";
354                                 function = "mmc0";
355                                 drive-strength = <30>;
356                                 bias-pull-up;
357                         };
358
359                         mmc1_pg_pins: mmc1-pg-pins {
360                                 pins = "PG0", "PG1", "PG2",
361                                        "PG3", "PG4", "PG5";
362                                 function = "mmc1";
363                                 drive-strength = <30>;
364                                 bias-pull-up;
365                         };
366
367                         mmc2_pins: mmc2-pins {
368                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
369                                        "PC10", "PC11", "PC12", "PC13", "PC14",
370                                        "PC15", "PC24";
371                                 function = "mmc2";
372                                 drive-strength = <30>;
373                                 bias-pull-up;
374                         };
375
376                         uart0_pb_pins: uart0-pb-pins {
377                                 pins = "PB22", "PB23";
378                                 function = "uart0";
379                         };
380                 };
381
382                 wdt: watchdog@1c20c90 {
383                         compatible = "allwinner,sun4i-a10-wdt";
384                         reg = <0x01c20c90 0x10>;
385                 };
386
387                 uart0: serial@1c28000 {
388                         compatible = "snps,dw-apb-uart";
389                         reg = <0x01c28000 0x400>;
390                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
391                         reg-shift = <2>;
392                         reg-io-width = <4>;
393                         clocks = <&ccu CLK_BUS_UART0>;
394                         resets = <&ccu RST_BUS_UART0>;
395                         status = "disabled";
396                 };
397
398                 uart1: serial@1c28400 {
399                         compatible = "snps,dw-apb-uart";
400                         reg = <0x01c28400 0x400>;
401                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
402                         reg-shift = <2>;
403                         reg-io-width = <4>;
404                         clocks = <&ccu CLK_BUS_UART1>;
405                         resets = <&ccu RST_BUS_UART1>;
406                         status = "disabled";
407                 };
408
409                 uart2: serial@1c28800 {
410                         compatible = "snps,dw-apb-uart";
411                         reg = <0x01c28800 0x400>;
412                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
413                         reg-shift = <2>;
414                         reg-io-width = <4>;
415                         clocks = <&ccu CLK_BUS_UART2>;
416                         resets = <&ccu RST_BUS_UART2>;
417                         status = "disabled";
418                 };
419
420                 uart3: serial@1c28c00 {
421                         compatible = "snps,dw-apb-uart";
422                         reg = <0x01c28c00 0x400>;
423                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
424                         reg-shift = <2>;
425                         reg-io-width = <4>;
426                         clocks = <&ccu CLK_BUS_UART3>;
427                         resets = <&ccu RST_BUS_UART3>;
428                         status = "disabled";
429                 };
430
431                 uart4: serial@1c29000 {
432                         compatible = "snps,dw-apb-uart";
433                         reg = <0x01c29000 0x400>;
434                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
435                         reg-shift = <2>;
436                         reg-io-width = <4>;
437                         clocks = <&ccu CLK_BUS_UART4>;
438                         resets = <&ccu RST_BUS_UART4>;
439                         status = "disabled";
440                 };
441
442                 uart5: serial@1c29400 {
443                         compatible = "snps,dw-apb-uart";
444                         reg = <0x01c29400 0x400>;
445                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
446                         reg-shift = <2>;
447                         reg-io-width = <4>;
448                         clocks = <&ccu CLK_BUS_UART5>;
449                         resets = <&ccu RST_BUS_UART5>;
450                         status = "disabled";
451                 };
452
453                 uart6: serial@1c29800 {
454                         compatible = "snps,dw-apb-uart";
455                         reg = <0x01c29800 0x400>;
456                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
457                         reg-shift = <2>;
458                         reg-io-width = <4>;
459                         clocks = <&ccu CLK_BUS_UART6>;
460                         resets = <&ccu RST_BUS_UART6>;
461                         status = "disabled";
462                 };
463
464                 uart7: serial@1c29c00 {
465                         compatible = "snps,dw-apb-uart";
466                         reg = <0x01c29c00 0x400>;
467                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
468                         reg-shift = <2>;
469                         reg-io-width = <4>;
470                         clocks = <&ccu CLK_BUS_UART7>;
471                         resets = <&ccu RST_BUS_UART7>;
472                         status = "disabled";
473                 };
474
475                 i2c0: i2c@1c2ac00 {
476                         compatible = "allwinner,sun6i-a31-i2c";
477                         reg = <0x01c2ac00 0x400>;
478                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
479                         clocks = <&ccu CLK_BUS_I2C0>;
480                         resets = <&ccu RST_BUS_I2C0>;
481                         pinctrl-0 = <&i2c0_pins>;
482                         pinctrl-names = "default";
483                         status = "disabled";
484                         #address-cells = <1>;
485                         #size-cells = <0>;
486                 };
487
488                 i2c1: i2c@1c2b000 {
489                         compatible = "allwinner,sun6i-a31-i2c";
490                         reg = <0x01c2b000 0x400>;
491                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
492                         clocks = <&ccu CLK_BUS_I2C1>;
493                         resets = <&ccu RST_BUS_I2C1>;
494                         status = "disabled";
495                         #address-cells = <1>;
496                         #size-cells = <0>;
497                 };
498
499                 i2c2: i2c@1c2b400 {
500                         compatible = "allwinner,sun6i-a31-i2c";
501                         reg = <0x01c2b400 0x400>;
502                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
503                         clocks = <&ccu CLK_BUS_I2C2>;
504                         resets = <&ccu RST_BUS_I2C2>;
505                         status = "disabled";
506                         #address-cells = <1>;
507                         #size-cells = <0>;
508                 };
509
510                 i2c3: i2c@1c2b800 {
511                         compatible = "allwinner,sun6i-a31-i2c";
512                         reg = <0x01c2b800 0x400>;
513                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
514                         clocks = <&ccu CLK_BUS_I2C3>;
515                         resets = <&ccu RST_BUS_I2C3>;
516                         status = "disabled";
517                         #address-cells = <1>;
518                         #size-cells = <0>;
519                 };
520
521                 i2c4: i2c@1c2c000 {
522                         compatible = "allwinner,sun6i-a31-i2c";
523                         reg = <0x01c2c000 0x400>;
524                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
525                         clocks = <&ccu CLK_BUS_I2C4>;
526                         resets = <&ccu RST_BUS_I2C4>;
527                         status = "disabled";
528                         #address-cells = <1>;
529                         #size-cells = <0>;
530                 };
531
532                 ahci: sata@1c18000 {
533                         compatible = "allwinner,sun8i-r40-ahci";
534                         reg = <0x01c18000 0x1000>;
535                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
536                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
537                         resets = <&ccu RST_BUS_SATA>;
538                         resets-name = "ahci";
539                         #address-cells = <1>;
540                         #size-cells = <0>;
541                         status = "disabled";
542
543                 };
544
545                 gmac: ethernet@1c50000 {
546                         compatible = "allwinner,sun8i-r40-gmac";
547                         syscon = <&ccu>;
548                         reg = <0x01c50000 0x10000>;
549                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
550                         interrupt-names = "macirq";
551                         resets = <&ccu RST_BUS_GMAC>;
552                         reset-names = "stmmaceth";
553                         clocks = <&ccu CLK_BUS_GMAC>;
554                         clock-names = "stmmaceth";
555                         status = "disabled";
556
557                         gmac_mdio: mdio {
558                                 compatible = "snps,dwmac-mdio";
559                                 #address-cells = <1>;
560                                 #size-cells = <0>;
561                         };
562                 };
563
564                 tcon_top: tcon-top@1c70000 {
565                         compatible = "allwinner,sun8i-r40-tcon-top";
566                         reg = <0x01c70000 0x1000>;
567                         clocks = <&ccu CLK_BUS_TCON_TOP>,
568                                  <&ccu CLK_TCON_TV0>,
569                                  <&ccu CLK_TVE0>,
570                                  <&ccu CLK_TCON_TV1>,
571                                  <&ccu CLK_TVE1>,
572                                  <&ccu CLK_DSI_DPHY>;
573                         clock-names = "bus",
574                                       "tcon-tv0",
575                                       "tve0",
576                                       "tcon-tv1",
577                                       "tve1",
578                                       "dsi";
579                         clock-output-names = "tcon-top-tv0",
580                                              "tcon-top-tv1",
581                                              "tcon-top-dsi";
582                         resets = <&ccu RST_BUS_TCON_TOP>;
583                         #clock-cells = <1>;
584
585                         ports {
586                                 #address-cells = <1>;
587                                 #size-cells = <0>;
588
589                                 tcon_top_mixer0_in: port@0 {
590                                         #address-cells = <1>;
591                                         #size-cells = <0>;
592                                         reg = <0>;
593
594                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
595                                                 reg = <0>;
596                                                 remote-endpoint = <&mixer0_out_tcon_top>;
597                                         };
598                                 };
599
600                                 tcon_top_mixer0_out: port@1 {
601                                         #address-cells = <1>;
602                                         #size-cells = <0>;
603                                         reg = <1>;
604
605                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
606                                                 reg = <0>;
607                                         };
608
609                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
610                                                 reg = <1>;
611                                         };
612
613                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
614                                                 reg = <2>;
615                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
616                                         };
617
618                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
619                                                 reg = <3>;
620                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
621                                         };
622                                 };
623
624                                 tcon_top_mixer1_in: port@2 {
625                                         #address-cells = <1>;
626                                         #size-cells = <0>;
627                                         reg = <2>;
628
629                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
630                                                 reg = <1>;
631                                                 remote-endpoint = <&mixer1_out_tcon_top>;
632                                         };
633                                 };
634
635                                 tcon_top_mixer1_out: port@3 {
636                                         #address-cells = <1>;
637                                         #size-cells = <0>;
638                                         reg = <3>;
639
640                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
641                                                 reg = <0>;
642                                         };
643
644                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
645                                                 reg = <1>;
646                                         };
647
648                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
649                                                 reg = <2>;
650                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
651                                         };
652
653                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
654                                                 reg = <3>;
655                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
656                                         };
657                                 };
658
659                                 tcon_top_hdmi_in: port@4 {
660                                         #address-cells = <1>;
661                                         #size-cells = <0>;
662                                         reg = <4>;
663
664                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
665                                                 reg = <0>;
666                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
667                                         };
668
669                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
670                                                 reg = <1>;
671                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
672                                         };
673                                 };
674
675                                 tcon_top_hdmi_out: port@5 {
676                                         reg = <5>;
677
678                                         tcon_top_hdmi_out_hdmi: endpoint {
679                                                 remote-endpoint = <&hdmi_in_tcon_top>;
680                                         };
681                                 };
682                         };
683                 };
684
685                 tcon_tv0: lcd-controller@1c73000 {
686                         compatible = "allwinner,sun8i-r40-tcon-tv";
687                         reg = <0x01c73000 0x1000>;
688                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
689                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
690                         clock-names = "ahb", "tcon-ch1";
691                         resets = <&ccu RST_BUS_TCON_TV0>;
692                         reset-names = "lcd";
693                         status = "disabled";
694
695                         ports {
696                                 #address-cells = <1>;
697                                 #size-cells = <0>;
698
699                                 tcon_tv0_in: port@0 {
700                                         #address-cells = <1>;
701                                         #size-cells = <0>;
702                                         reg = <0>;
703
704                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
705                                                 reg = <0>;
706                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
707                                         };
708
709                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
710                                                 reg = <1>;
711                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
712                                         };
713                                 };
714
715                                 tcon_tv0_out: port@1 {
716                                         #address-cells = <1>;
717                                         #size-cells = <0>;
718                                         reg = <1>;
719
720                                         tcon_tv0_out_tcon_top: endpoint@1 {
721                                                 reg = <1>;
722                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
723                                         };
724                                 };
725                         };
726                 };
727
728                 tcon_tv1: lcd-controller@1c74000 {
729                         compatible = "allwinner,sun8i-r40-tcon-tv";
730                         reg = <0x01c74000 0x1000>;
731                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
732                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
733                         clock-names = "ahb", "tcon-ch1";
734                         resets = <&ccu RST_BUS_TCON_TV1>;
735                         reset-names = "lcd";
736                         status = "disabled";
737
738                         ports {
739                                 #address-cells = <1>;
740                                 #size-cells = <0>;
741
742                                 tcon_tv1_in: port@0 {
743                                         #address-cells = <1>;
744                                         #size-cells = <0>;
745                                         reg = <0>;
746
747                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
748                                                 reg = <0>;
749                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
750                                         };
751
752                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
753                                                 reg = <1>;
754                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
755                                         };
756                                 };
757
758                                 tcon_tv1_out: port@1 {
759                                         #address-cells = <1>;
760                                         #size-cells = <0>;
761                                         reg = <1>;
762
763                                         tcon_tv1_out_tcon_top: endpoint@1 {
764                                                 reg = <1>;
765                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
766                                         };
767                                 };
768                         };
769                 };
770
771                 gic: interrupt-controller@1c81000 {
772                         compatible = "arm,gic-400";
773                         reg = <0x01c81000 0x1000>,
774                               <0x01c82000 0x1000>,
775                               <0x01c84000 0x2000>,
776                               <0x01c86000 0x2000>;
777                         interrupt-controller;
778                         #interrupt-cells = <3>;
779                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
780                 };
781
782                 hdmi: hdmi@1ee0000 {
783                         compatible = "allwinner,sun8i-r40-dw-hdmi",
784                                      "allwinner,sun8i-a83t-dw-hdmi";
785                         reg = <0x01ee0000 0x10000>;
786                         reg-io-width = <1>;
787                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
788                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
789                                  <&ccu CLK_HDMI>;
790                         clock-names = "iahb", "isfr", "tmds";
791                         resets = <&ccu RST_BUS_HDMI1>;
792                         reset-names = "ctrl";
793                         phys = <&hdmi_phy>;
794                         phy-names = "hdmi-phy";
795                         status = "disabled";
796
797                         ports {
798                                 #address-cells = <1>;
799                                 #size-cells = <0>;
800
801                                 hdmi_in: port@0 {
802                                         reg = <0>;
803
804                                         hdmi_in_tcon_top: endpoint {
805                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
806                                         };
807                                 };
808
809                                 hdmi_out: port@1 {
810                                         reg = <1>;
811                                 };
812                         };
813                 };
814
815                 hdmi_phy: hdmi-phy@1ef0000 {
816                         compatible = "allwinner,sun8i-r40-hdmi-phy";
817                         reg = <0x01ef0000 0x10000>;
818                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
819                                  <&ccu 7>, <&ccu 16>;
820                         clock-names = "bus", "mod", "pll-0", "pll-1";
821                         resets = <&ccu RST_BUS_HDMI0>;
822                         reset-names = "phy";
823                         #phy-cells = <0>;
824                 };
825         };
826
827         timer {
828                 compatible = "arm,armv7-timer";
829                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
830                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
831                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
832                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
833         };
834 };