76a0949df4a88b6693e769563b8393dc3506b32d
[muen/linux.git] / arch / arm / boot / dts / vf500.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
4
5 #include "vfxxx.dtsi"
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7
8 / {
9         #address-cells = <1>;
10         #size-cells = <1>;
11         chosen { };
12         aliases { };
13         memory { device_type = "memory"; };
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 a5_cpu: cpu@0 {
20                         compatible = "arm,cortex-a5";
21                         device_type = "cpu";
22                         reg = <0x0>;
23                 };
24         };
25
26         soc {
27                 aips-bus@40000000 {
28
29                         intc: interrupt-controller@40003000 {
30                                 compatible = "arm,cortex-a9-gic";
31                                 #interrupt-cells = <3>;
32                                 interrupt-controller;
33                                 interrupt-parent = <&intc>;
34                                 reg = <0x40003000 0x1000>,
35                                       <0x40002100 0x100>;
36                         };
37
38                         global_timer: timer@40002200 {
39                                 compatible = "arm,cortex-a9-global-timer";
40                                 reg = <0x40002200 0x20>;
41                                 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
42                                 interrupt-parent = <&intc>;
43                                 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
44                         };
45                 };
46
47                 aips-bus@40080000 {
48                         pmu@40089000 {
49                                 compatible = "arm,cortex-a5-pmu";
50                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
51                                 interrupt-affinity = <&a5_cpu>;
52                                 reg = <0x40089000 0x1000>;
53                         };
54                 };
55
56         };
57 };
58
59 &mscm_ir {
60         interrupt-parent = <&intc>;
61 };
62
63 &wdoga5 {
64         status = "okay";
65 };