Merge tag 'davinci-fixes-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel...
[muen/linux.git] / arch / arm / mach-davinci / dm365.c
1 /*
2  * TI DaVinci DM365 chip specific setup
3  *
4  * Copyright (C) 2009 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/clk-provider.h>
17 #include <linux/clk/davinci.h>
18 #include <linux/clkdev.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/init.h>
22 #include <linux/platform_data/edma.h>
23 #include <linux/platform_data/gpio-davinci.h>
24 #include <linux/platform_data/keyscan-davinci.h>
25 #include <linux/platform_data/spi-davinci.h>
26 #include <linux/platform_device.h>
27 #include <linux/serial_8250.h>
28 #include <linux/spi/spi.h>
29
30 #include <asm/mach/map.h>
31
32 #include <mach/common.h>
33 #include <mach/cputype.h>
34 #include <mach/irqs.h>
35 #include <mach/mux.h>
36 #include <mach/serial.h>
37 #include <mach/time.h>
38
39 #include "asp.h"
40 #include "davinci.h"
41 #include "mux.h"
42
43 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
44 #define DM365_RTC_BASE                  0x01c69000
45 #define DM365_KEYSCAN_BASE              0x01c69400
46 #define DM365_OSD_BASE                  0x01c71c00
47 #define DM365_VENC_BASE                 0x01c71e00
48 #define DAVINCI_DM365_VC_BASE           0x01d0c000
49 #define DAVINCI_DMA_VC_TX               2
50 #define DAVINCI_DMA_VC_RX               3
51 #define DM365_EMAC_BASE                 0x01d07000
52 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
53 #define DM365_EMAC_CNTRL_OFFSET         0x0000
54 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
55 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
56 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
57
58 #define INTMUX          0x18
59 #define EVTMUX          0x1c
60
61
62 static const struct mux_config dm365_pins[] = {
63 #ifdef CONFIG_DAVINCI_MUX
64 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
65
66 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
67 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
68 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
69 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
70 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
71 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
72
73 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
74 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
75
76 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
77 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
78 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
79 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
80 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
81 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
82 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
83 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
84
85 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
86 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
87 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
88 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
89 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
90 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
91
92 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
93 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
94 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
95 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
96 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
97
98 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
99 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
100 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
101 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
102 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
103 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
104
105 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
106 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
107 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
108 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
109 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
110 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
111 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
112 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
113 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
114 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
115 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
116 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
117 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
118 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
119 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
120 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
121 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
122
123 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
124
125 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
126 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
127 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
128 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
129 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
130 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
131 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
132 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
133 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
134 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
135 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
136 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
137
138 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
139 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
140 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
141 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
142 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
143
144 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
145 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
146 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
147 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
148 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
149
150 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
151 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
152 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
153 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
154 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
155
156 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
157 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
158 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
159 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
160 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
161
162 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
163 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
164 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
165
166 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
167 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
168 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
169 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
170 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
171 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
172 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
173
174 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
175 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
176 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
177 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
178 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
179 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
180 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
181 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
182 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
183 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
184
185 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
186 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
187 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
188 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
189 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
190 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
191 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
192 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
193 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
194 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
195 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
196 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
197 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
198 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
199 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
200 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
201 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
202 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
203
204 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
205 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
206 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
207 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
208 #endif
209 };
210
211 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
212
213 static struct davinci_spi_platform_data dm365_spi0_pdata = {
214         .version        = SPI_VERSION_1,
215         .num_chipselect = 2,
216         .dma_event_q    = EVENTQ_3,
217         .prescaler_limit = 1,
218 };
219
220 static struct resource dm365_spi0_resources[] = {
221         {
222                 .start = 0x01c66000,
223                 .end   = 0x01c667ff,
224                 .flags = IORESOURCE_MEM,
225         },
226         {
227                 .start = IRQ_DM365_SPIINT0_0,
228                 .flags = IORESOURCE_IRQ,
229         },
230 };
231
232 static struct platform_device dm365_spi0_device = {
233         .name = "spi_davinci",
234         .id = 0,
235         .dev = {
236                 .dma_mask = &dm365_spi0_dma_mask,
237                 .coherent_dma_mask = DMA_BIT_MASK(32),
238                 .platform_data = &dm365_spi0_pdata,
239         },
240         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
241         .resource = dm365_spi0_resources,
242 };
243
244 void __init dm365_init_spi0(unsigned chipselect_mask,
245                 const struct spi_board_info *info, unsigned len)
246 {
247         davinci_cfg_reg(DM365_SPI0_SCLK);
248         davinci_cfg_reg(DM365_SPI0_SDI);
249         davinci_cfg_reg(DM365_SPI0_SDO);
250
251         /* not all slaves will be wired up */
252         if (chipselect_mask & BIT(0))
253                 davinci_cfg_reg(DM365_SPI0_SDENA0);
254         if (chipselect_mask & BIT(1))
255                 davinci_cfg_reg(DM365_SPI0_SDENA1);
256
257         spi_register_board_info(info, len);
258
259         platform_device_register(&dm365_spi0_device);
260 }
261
262 static struct resource dm365_gpio_resources[] = {
263         {       /* registers */
264                 .start  = DAVINCI_GPIO_BASE,
265                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
266                 .flags  = IORESOURCE_MEM,
267         },
268         {       /* interrupt */
269                 .start  = IRQ_DM365_GPIO0,
270                 .end    = IRQ_DM365_GPIO0,
271                 .flags  = IORESOURCE_IRQ,
272         },
273         {
274                 .start  = IRQ_DM365_GPIO1,
275                 .end    = IRQ_DM365_GPIO1,
276                 .flags  = IORESOURCE_IRQ,
277         },
278         {
279                 .start  = IRQ_DM365_GPIO2,
280                 .end    = IRQ_DM365_GPIO2,
281                 .flags  = IORESOURCE_IRQ,
282         },
283         {
284                 .start  = IRQ_DM365_GPIO3,
285                 .end    = IRQ_DM365_GPIO3,
286                 .flags  = IORESOURCE_IRQ,
287         },
288         {
289                 .start  = IRQ_DM365_GPIO4,
290                 .end    = IRQ_DM365_GPIO4,
291                 .flags  = IORESOURCE_IRQ,
292         },
293         {
294                 .start  = IRQ_DM365_GPIO5,
295                 .end    = IRQ_DM365_GPIO5,
296                 .flags  = IORESOURCE_IRQ,
297         },
298         {
299                 .start  = IRQ_DM365_GPIO6,
300                 .end    = IRQ_DM365_GPIO6,
301                 .flags  = IORESOURCE_IRQ,
302         },
303         {
304                 .start  = IRQ_DM365_GPIO7,
305                 .end    = IRQ_DM365_GPIO7,
306                 .flags  = IORESOURCE_IRQ,
307         },
308 };
309
310 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
311         .no_auto_base   = true,
312         .base           = 0,
313         .ngpio          = 104,
314         .gpio_unbanked  = 8,
315 };
316
317 int __init dm365_gpio_register(void)
318 {
319         return davinci_gpio_register(dm365_gpio_resources,
320                                      ARRAY_SIZE(dm365_gpio_resources),
321                                      &dm365_gpio_platform_data);
322 }
323
324 static struct emac_platform_data dm365_emac_pdata = {
325         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
326         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
327         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
328         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
329         .version                = EMAC_VERSION_2,
330 };
331
332 static struct resource dm365_emac_resources[] = {
333         {
334                 .start  = DM365_EMAC_BASE,
335                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
336                 .flags  = IORESOURCE_MEM,
337         },
338         {
339                 .start  = IRQ_DM365_EMAC_RXTHRESH,
340                 .end    = IRQ_DM365_EMAC_RXTHRESH,
341                 .flags  = IORESOURCE_IRQ,
342         },
343         {
344                 .start  = IRQ_DM365_EMAC_RXPULSE,
345                 .end    = IRQ_DM365_EMAC_RXPULSE,
346                 .flags  = IORESOURCE_IRQ,
347         },
348         {
349                 .start  = IRQ_DM365_EMAC_TXPULSE,
350                 .end    = IRQ_DM365_EMAC_TXPULSE,
351                 .flags  = IORESOURCE_IRQ,
352         },
353         {
354                 .start  = IRQ_DM365_EMAC_MISCPULSE,
355                 .end    = IRQ_DM365_EMAC_MISCPULSE,
356                 .flags  = IORESOURCE_IRQ,
357         },
358 };
359
360 static struct platform_device dm365_emac_device = {
361         .name           = "davinci_emac",
362         .id             = 1,
363         .dev = {
364                 .platform_data  = &dm365_emac_pdata,
365         },
366         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
367         .resource       = dm365_emac_resources,
368 };
369
370 static struct resource dm365_mdio_resources[] = {
371         {
372                 .start  = DM365_EMAC_MDIO_BASE,
373                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
374                 .flags  = IORESOURCE_MEM,
375         },
376 };
377
378 static struct platform_device dm365_mdio_device = {
379         .name           = "davinci_mdio",
380         .id             = 0,
381         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
382         .resource       = dm365_mdio_resources,
383 };
384
385 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
386         [IRQ_VDINT0]                    = 2,
387         [IRQ_VDINT1]                    = 6,
388         [IRQ_VDINT2]                    = 6,
389         [IRQ_HISTINT]                   = 6,
390         [IRQ_H3AINT]                    = 6,
391         [IRQ_PRVUINT]                   = 6,
392         [IRQ_RSZINT]                    = 6,
393         [IRQ_DM365_INSFINT]             = 7,
394         [IRQ_VENCINT]                   = 6,
395         [IRQ_ASQINT]                    = 6,
396         [IRQ_IMXINT]                    = 6,
397         [IRQ_DM365_IMCOPINT]            = 4,
398         [IRQ_USBINT]                    = 4,
399         [IRQ_DM365_RTOINT]              = 7,
400         [IRQ_DM365_TINT5]               = 7,
401         [IRQ_DM365_TINT6]               = 5,
402         [IRQ_CCINT0]                    = 5,
403         [IRQ_CCERRINT]                  = 5,
404         [IRQ_TCERRINT0]                 = 5,
405         [IRQ_TCERRINT]                  = 7,
406         [IRQ_PSCIN]                     = 4,
407         [IRQ_DM365_SPINT2_1]            = 7,
408         [IRQ_DM365_TINT7]               = 7,
409         [IRQ_DM365_SDIOINT0]            = 7,
410         [IRQ_MBXINT]                    = 7,
411         [IRQ_MBRINT]                    = 7,
412         [IRQ_MMCINT]                    = 7,
413         [IRQ_DM365_MMCINT1]             = 7,
414         [IRQ_DM365_PWMINT3]             = 7,
415         [IRQ_AEMIFINT]                  = 2,
416         [IRQ_DM365_SDIOINT1]            = 2,
417         [IRQ_TINT0_TINT12]              = 7,
418         [IRQ_TINT0_TINT34]              = 7,
419         [IRQ_TINT1_TINT12]              = 7,
420         [IRQ_TINT1_TINT34]              = 7,
421         [IRQ_PWMINT0]                   = 7,
422         [IRQ_PWMINT1]                   = 3,
423         [IRQ_PWMINT2]                   = 3,
424         [IRQ_I2C]                       = 3,
425         [IRQ_UARTINT0]                  = 3,
426         [IRQ_UARTINT1]                  = 3,
427         [IRQ_DM365_RTCINT]              = 3,
428         [IRQ_DM365_SPIINT0_0]           = 3,
429         [IRQ_DM365_SPIINT3_0]           = 3,
430         [IRQ_DM365_GPIO0]               = 3,
431         [IRQ_DM365_GPIO1]               = 7,
432         [IRQ_DM365_GPIO2]               = 4,
433         [IRQ_DM365_GPIO3]               = 4,
434         [IRQ_DM365_GPIO4]               = 7,
435         [IRQ_DM365_GPIO5]               = 7,
436         [IRQ_DM365_GPIO6]               = 7,
437         [IRQ_DM365_GPIO7]               = 7,
438         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
439         [IRQ_DM365_EMAC_RXPULSE]        = 7,
440         [IRQ_DM365_EMAC_TXPULSE]        = 7,
441         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
442         [IRQ_DM365_GPIO12]              = 7,
443         [IRQ_DM365_GPIO13]              = 7,
444         [IRQ_DM365_GPIO14]              = 7,
445         [IRQ_DM365_GPIO15]              = 7,
446         [IRQ_DM365_KEYINT]              = 7,
447         [IRQ_DM365_TCERRINT2]           = 7,
448         [IRQ_DM365_TCERRINT3]           = 7,
449         [IRQ_DM365_EMUINT]              = 7,
450 };
451
452 /* Four Transfer Controllers on DM365 */
453 static s8 dm365_queue_priority_mapping[][2] = {
454         /* {event queue no, Priority} */
455         {0, 7},
456         {1, 7},
457         {2, 7},
458         {3, 0},
459         {-1, -1},
460 };
461
462 static const struct dma_slave_map dm365_edma_map[] = {
463         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
464         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
465         { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
466         { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
467         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
468         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
469         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
470         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
471         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
472         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
473         { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
474         { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
475         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
476         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
477         { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
478         { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
479 };
480
481 static struct edma_soc_info dm365_edma_pdata = {
482         .queue_priority_mapping = dm365_queue_priority_mapping,
483         .default_queue          = EVENTQ_3,
484         .slave_map              = dm365_edma_map,
485         .slavecnt               = ARRAY_SIZE(dm365_edma_map),
486 };
487
488 static struct resource edma_resources[] = {
489         {
490                 .name   = "edma3_cc",
491                 .start  = 0x01c00000,
492                 .end    = 0x01c00000 + SZ_64K - 1,
493                 .flags  = IORESOURCE_MEM,
494         },
495         {
496                 .name   = "edma3_tc0",
497                 .start  = 0x01c10000,
498                 .end    = 0x01c10000 + SZ_1K - 1,
499                 .flags  = IORESOURCE_MEM,
500         },
501         {
502                 .name   = "edma3_tc1",
503                 .start  = 0x01c10400,
504                 .end    = 0x01c10400 + SZ_1K - 1,
505                 .flags  = IORESOURCE_MEM,
506         },
507         {
508                 .name   = "edma3_tc2",
509                 .start  = 0x01c10800,
510                 .end    = 0x01c10800 + SZ_1K - 1,
511                 .flags  = IORESOURCE_MEM,
512         },
513         {
514                 .name   = "edma3_tc3",
515                 .start  = 0x01c10c00,
516                 .end    = 0x01c10c00 + SZ_1K - 1,
517                 .flags  = IORESOURCE_MEM,
518         },
519         {
520                 .name   = "edma3_ccint",
521                 .start  = IRQ_CCINT0,
522                 .flags  = IORESOURCE_IRQ,
523         },
524         {
525                 .name   = "edma3_ccerrint",
526                 .start  = IRQ_CCERRINT,
527                 .flags  = IORESOURCE_IRQ,
528         },
529         /* not using TC*_ERR */
530 };
531
532 static const struct platform_device_info dm365_edma_device __initconst = {
533         .name           = "edma",
534         .id             = 0,
535         .dma_mask       = DMA_BIT_MASK(32),
536         .res            = edma_resources,
537         .num_res        = ARRAY_SIZE(edma_resources),
538         .data           = &dm365_edma_pdata,
539         .size_data      = sizeof(dm365_edma_pdata),
540 };
541
542 static struct resource dm365_asp_resources[] = {
543         {
544                 .name   = "mpu",
545                 .start  = DAVINCI_DM365_ASP0_BASE,
546                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
547                 .flags  = IORESOURCE_MEM,
548         },
549         {
550                 .start  = DAVINCI_DMA_ASP0_TX,
551                 .end    = DAVINCI_DMA_ASP0_TX,
552                 .flags  = IORESOURCE_DMA,
553         },
554         {
555                 .start  = DAVINCI_DMA_ASP0_RX,
556                 .end    = DAVINCI_DMA_ASP0_RX,
557                 .flags  = IORESOURCE_DMA,
558         },
559 };
560
561 static struct platform_device dm365_asp_device = {
562         .name           = "davinci-mcbsp",
563         .id             = -1,
564         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
565         .resource       = dm365_asp_resources,
566 };
567
568 static struct resource dm365_vc_resources[] = {
569         {
570                 .start  = DAVINCI_DM365_VC_BASE,
571                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
572                 .flags  = IORESOURCE_MEM,
573         },
574         {
575                 .start  = DAVINCI_DMA_VC_TX,
576                 .end    = DAVINCI_DMA_VC_TX,
577                 .flags  = IORESOURCE_DMA,
578         },
579         {
580                 .start  = DAVINCI_DMA_VC_RX,
581                 .end    = DAVINCI_DMA_VC_RX,
582                 .flags  = IORESOURCE_DMA,
583         },
584 };
585
586 static struct platform_device dm365_vc_device = {
587         .name           = "davinci_voicecodec",
588         .id             = -1,
589         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
590         .resource       = dm365_vc_resources,
591 };
592
593 static struct resource dm365_rtc_resources[] = {
594         {
595                 .start = DM365_RTC_BASE,
596                 .end = DM365_RTC_BASE + SZ_1K - 1,
597                 .flags = IORESOURCE_MEM,
598         },
599         {
600                 .start = IRQ_DM365_RTCINT,
601                 .flags = IORESOURCE_IRQ,
602         },
603 };
604
605 static struct platform_device dm365_rtc_device = {
606         .name = "rtc_davinci",
607         .id = 0,
608         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
609         .resource = dm365_rtc_resources,
610 };
611
612 static struct map_desc dm365_io_desc[] = {
613         {
614                 .virtual        = IO_VIRT,
615                 .pfn            = __phys_to_pfn(IO_PHYS),
616                 .length         = IO_SIZE,
617                 .type           = MT_DEVICE
618         },
619 };
620
621 static struct resource dm365_ks_resources[] = {
622         {
623                 /* registers */
624                 .start = DM365_KEYSCAN_BASE,
625                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
626                 .flags = IORESOURCE_MEM,
627         },
628         {
629                 /* interrupt */
630                 .start = IRQ_DM365_KEYINT,
631                 .end = IRQ_DM365_KEYINT,
632                 .flags = IORESOURCE_IRQ,
633         },
634 };
635
636 static struct platform_device dm365_ks_device = {
637         .name           = "davinci_keyscan",
638         .id             = 0,
639         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
640         .resource       = dm365_ks_resources,
641 };
642
643 /* Contents of JTAG ID register used to identify exact cpu type */
644 static struct davinci_id dm365_ids[] = {
645         {
646                 .variant        = 0x0,
647                 .part_no        = 0xb83e,
648                 .manufacturer   = 0x017,
649                 .cpu_id         = DAVINCI_CPU_ID_DM365,
650                 .name           = "dm365_rev1.1",
651         },
652         {
653                 .variant        = 0x8,
654                 .part_no        = 0xb83e,
655                 .manufacturer   = 0x017,
656                 .cpu_id         = DAVINCI_CPU_ID_DM365,
657                 .name           = "dm365_rev1.2",
658         },
659 };
660
661 static struct davinci_timer_info dm365_timer_info = {
662         .timers         = davinci_timer_instance,
663         .clockevent_id  = T0_BOT,
664         .clocksource_id = T0_TOP,
665 };
666
667 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
668
669 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
670         {
671                 .mapbase        = DAVINCI_UART0_BASE,
672                 .irq            = IRQ_UARTINT0,
673                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
674                                   UPF_IOREMAP,
675                 .iotype         = UPIO_MEM,
676                 .regshift       = 2,
677         },
678         {
679                 .flags  = 0,
680         }
681 };
682 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
683         {
684                 .mapbase        = DM365_UART1_BASE,
685                 .irq            = IRQ_UARTINT1,
686                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
687                                   UPF_IOREMAP,
688                 .iotype         = UPIO_MEM,
689                 .regshift       = 2,
690         },
691         {
692                 .flags  = 0,
693         }
694 };
695
696 struct platform_device dm365_serial_device[] = {
697         {
698                 .name                   = "serial8250",
699                 .id                     = PLAT8250_DEV_PLATFORM,
700                 .dev                    = {
701                         .platform_data  = dm365_serial0_platform_data,
702                 }
703         },
704         {
705                 .name                   = "serial8250",
706                 .id                     = PLAT8250_DEV_PLATFORM1,
707                 .dev                    = {
708                         .platform_data  = dm365_serial1_platform_data,
709                 }
710         },
711         {
712         }
713 };
714
715 static const struct davinci_soc_info davinci_soc_info_dm365 = {
716         .io_desc                = dm365_io_desc,
717         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
718         .jtag_id_reg            = 0x01c40028,
719         .ids                    = dm365_ids,
720         .ids_num                = ARRAY_SIZE(dm365_ids),
721         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
722         .pinmux_pins            = dm365_pins,
723         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
724         .intc_base              = DAVINCI_ARM_INTC_BASE,
725         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
726         .intc_irq_prios         = dm365_default_priorities,
727         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
728         .timer_info             = &dm365_timer_info,
729         .emac_pdata             = &dm365_emac_pdata,
730         .sram_dma               = 0x00010000,
731         .sram_len               = SZ_32K,
732 };
733
734 void __init dm365_init_asp(void)
735 {
736         davinci_cfg_reg(DM365_MCBSP0_BDX);
737         davinci_cfg_reg(DM365_MCBSP0_X);
738         davinci_cfg_reg(DM365_MCBSP0_BFSX);
739         davinci_cfg_reg(DM365_MCBSP0_BDR);
740         davinci_cfg_reg(DM365_MCBSP0_R);
741         davinci_cfg_reg(DM365_MCBSP0_BFSR);
742         davinci_cfg_reg(DM365_EVT2_ASP_TX);
743         davinci_cfg_reg(DM365_EVT3_ASP_RX);
744         platform_device_register(&dm365_asp_device);
745 }
746
747 void __init dm365_init_vc(void)
748 {
749         davinci_cfg_reg(DM365_EVT2_VC_TX);
750         davinci_cfg_reg(DM365_EVT3_VC_RX);
751         platform_device_register(&dm365_vc_device);
752 }
753
754 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
755 {
756         dm365_ks_device.dev.platform_data = pdata;
757         platform_device_register(&dm365_ks_device);
758 }
759
760 void __init dm365_init_rtc(void)
761 {
762         davinci_cfg_reg(DM365_INT_PRTCSS);
763         platform_device_register(&dm365_rtc_device);
764 }
765
766 void __init dm365_init(void)
767 {
768         davinci_common_init(&davinci_soc_info_dm365);
769         davinci_map_sysmod();
770 }
771
772 void __init dm365_init_time(void)
773 {
774         void __iomem *pll1, *pll2, *psc;
775         struct clk *clk;
776
777         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
778
779         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
780         dm365_pll1_init(NULL, pll1, NULL);
781
782         pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
783         dm365_pll2_init(NULL, pll2, NULL);
784
785         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
786         dm365_psc_init(NULL, psc);
787
788         clk = clk_get(NULL, "timer0");
789
790         davinci_timer_init(clk);
791 }
792
793 void __init dm365_register_clocks(void)
794 {
795         /* all clocks are currently registered in dm365_init_time() */
796 }
797
798 static struct resource dm365_vpss_resources[] = {
799         {
800                 /* VPSS ISP5 Base address */
801                 .name           = "isp5",
802                 .start          = 0x01c70000,
803                 .end            = 0x01c70000 + 0xff,
804                 .flags          = IORESOURCE_MEM,
805         },
806         {
807                 /* VPSS CLK Base address */
808                 .name           = "vpss",
809                 .start          = 0x01c70200,
810                 .end            = 0x01c70200 + 0xff,
811                 .flags          = IORESOURCE_MEM,
812         },
813 };
814
815 static struct platform_device dm365_vpss_device = {
816        .name                   = "vpss",
817        .id                     = -1,
818        .dev.platform_data      = "dm365_vpss",
819        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
820        .resource               = dm365_vpss_resources,
821 };
822
823 static struct resource vpfe_resources[] = {
824         {
825                 .start          = IRQ_VDINT0,
826                 .end            = IRQ_VDINT0,
827                 .flags          = IORESOURCE_IRQ,
828         },
829         {
830                 .start          = IRQ_VDINT1,
831                 .end            = IRQ_VDINT1,
832                 .flags          = IORESOURCE_IRQ,
833         },
834 };
835
836 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
837 static struct platform_device vpfe_capture_dev = {
838         .name           = CAPTURE_DRV_NAME,
839         .id             = -1,
840         .num_resources  = ARRAY_SIZE(vpfe_resources),
841         .resource       = vpfe_resources,
842         .dev = {
843                 .dma_mask               = &vpfe_capture_dma_mask,
844                 .coherent_dma_mask      = DMA_BIT_MASK(32),
845         },
846 };
847
848 static void dm365_isif_setup_pinmux(void)
849 {
850         davinci_cfg_reg(DM365_VIN_CAM_WEN);
851         davinci_cfg_reg(DM365_VIN_CAM_VD);
852         davinci_cfg_reg(DM365_VIN_CAM_HD);
853         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
854         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
855 }
856
857 static struct resource isif_resource[] = {
858         /* ISIF Base address */
859         {
860                 .start          = 0x01c71000,
861                 .end            = 0x01c71000 + 0x1ff,
862                 .flags          = IORESOURCE_MEM,
863         },
864         /* ISIF Linearization table 0 */
865         {
866                 .start          = 0x1C7C000,
867                 .end            = 0x1C7C000 + 0x2ff,
868                 .flags          = IORESOURCE_MEM,
869         },
870         /* ISIF Linearization table 1 */
871         {
872                 .start          = 0x1C7C400,
873                 .end            = 0x1C7C400 + 0x2ff,
874                 .flags          = IORESOURCE_MEM,
875         },
876 };
877 static struct platform_device dm365_isif_dev = {
878         .name           = "isif",
879         .id             = -1,
880         .num_resources  = ARRAY_SIZE(isif_resource),
881         .resource       = isif_resource,
882         .dev = {
883                 .dma_mask               = &vpfe_capture_dma_mask,
884                 .coherent_dma_mask      = DMA_BIT_MASK(32),
885                 .platform_data          = dm365_isif_setup_pinmux,
886         },
887 };
888
889 static struct resource dm365_osd_resources[] = {
890         {
891                 .start = DM365_OSD_BASE,
892                 .end   = DM365_OSD_BASE + 0xff,
893                 .flags = IORESOURCE_MEM,
894         },
895 };
896
897 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
898
899 static struct platform_device dm365_osd_dev = {
900         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
901         .id             = -1,
902         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
903         .resource       = dm365_osd_resources,
904         .dev            = {
905                 .dma_mask               = &dm365_video_dma_mask,
906                 .coherent_dma_mask      = DMA_BIT_MASK(32),
907         },
908 };
909
910 static struct resource dm365_venc_resources[] = {
911         {
912                 .start = IRQ_VENCINT,
913                 .end   = IRQ_VENCINT,
914                 .flags = IORESOURCE_IRQ,
915         },
916         /* venc registers io space */
917         {
918                 .start = DM365_VENC_BASE,
919                 .end   = DM365_VENC_BASE + 0x177,
920                 .flags = IORESOURCE_MEM,
921         },
922         /* vdaccfg registers io space */
923         {
924                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
925                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
926                 .flags = IORESOURCE_MEM,
927         },
928 };
929
930 static struct resource dm365_v4l2_disp_resources[] = {
931         {
932                 .start = IRQ_VENCINT,
933                 .end   = IRQ_VENCINT,
934                 .flags = IORESOURCE_IRQ,
935         },
936         /* venc registers io space */
937         {
938                 .start = DM365_VENC_BASE,
939                 .end   = DM365_VENC_BASE + 0x177,
940                 .flags = IORESOURCE_MEM,
941         },
942 };
943
944 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
945 {
946         switch (if_type) {
947         case MEDIA_BUS_FMT_SGRBG8_1X8:
948                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
949                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
950                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
951                 break;
952         case MEDIA_BUS_FMT_YUYV10_1X20:
953                 if (field)
954                         davinci_cfg_reg(DM365_VOUT_FIELD);
955                 else
956                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
957                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
958                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
959                 break;
960         default:
961                 return -EINVAL;
962         }
963
964         return 0;
965 }
966
967 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
968                                   unsigned int pclock)
969 {
970         void __iomem *vpss_clkctl_reg;
971         u32 val;
972
973         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
974
975         switch (type) {
976         case VPBE_ENC_STD:
977                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
978                 break;
979         case VPBE_ENC_DV_TIMINGS:
980                 if (pclock <= 27000000) {
981                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
982                 } else {
983                         /* set sysclk4 to output 74.25 MHz from pll1 */
984                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
985                               VPSS_VENCCLKEN_ENABLE;
986                 }
987                 break;
988         default:
989                 return -EINVAL;
990         }
991         writel(val, vpss_clkctl_reg);
992
993         return 0;
994 }
995
996 static struct platform_device dm365_vpbe_display = {
997         .name           = "vpbe-v4l2",
998         .id             = -1,
999         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1000         .resource       = dm365_v4l2_disp_resources,
1001         .dev            = {
1002                 .dma_mask               = &dm365_video_dma_mask,
1003                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1004         },
1005 };
1006
1007 static struct venc_platform_data dm365_venc_pdata = {
1008         .setup_pinmux   = dm365_vpbe_setup_pinmux,
1009         .setup_clock    = dm365_venc_setup_clock,
1010 };
1011
1012 static struct platform_device dm365_venc_dev = {
1013         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
1014         .id             = -1,
1015         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1016         .resource       = dm365_venc_resources,
1017         .dev            = {
1018                 .dma_mask               = &dm365_video_dma_mask,
1019                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1020                 .platform_data          = (void *)&dm365_venc_pdata,
1021         },
1022 };
1023
1024 static struct platform_device dm365_vpbe_dev = {
1025         .name           = "vpbe_controller",
1026         .id             = -1,
1027         .dev            = {
1028                 .dma_mask               = &dm365_video_dma_mask,
1029                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1030         },
1031 };
1032
1033 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1034                                 struct vpbe_config *vpbe_cfg)
1035 {
1036         if (vpfe_cfg || vpbe_cfg)
1037                 platform_device_register(&dm365_vpss_device);
1038
1039         if (vpfe_cfg) {
1040                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1041                 platform_device_register(&dm365_isif_dev);
1042                 platform_device_register(&vpfe_capture_dev);
1043         }
1044         if (vpbe_cfg) {
1045                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1046                 platform_device_register(&dm365_osd_dev);
1047                 platform_device_register(&dm365_venc_dev);
1048                 platform_device_register(&dm365_vpbe_dev);
1049                 platform_device_register(&dm365_vpbe_display);
1050         }
1051
1052         return 0;
1053 }
1054
1055 static int __init dm365_init_devices(void)
1056 {
1057         struct platform_device *edma_pdev;
1058         int ret = 0;
1059
1060         if (!cpu_is_davinci_dm365())
1061                 return 0;
1062
1063         davinci_cfg_reg(DM365_INT_EDMA_CC);
1064         edma_pdev = platform_device_register_full(&dm365_edma_device);
1065         if (IS_ERR(edma_pdev)) {
1066                 pr_warn("%s: Failed to register eDMA\n", __func__);
1067                 return PTR_ERR(edma_pdev);
1068         }
1069
1070         platform_device_register(&dm365_mdio_device);
1071         platform_device_register(&dm365_emac_device);
1072
1073         ret = davinci_init_wdt();
1074         if (ret)
1075                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1076
1077         return ret;
1078 }
1079 postcore_initcall(dm365_init_devices);