Merge tag 'v4.20-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel...
[muen/linux.git] / arch / arm / mach-davinci / dm365.c
1 /*
2  * TI DaVinci DM365 chip specific setup
3  *
4  * Copyright (C) 2009 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/clk-provider.h>
17 #include <linux/clk/davinci.h>
18 #include <linux/clkdev.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/init.h>
22 #include <linux/platform_data/edma.h>
23 #include <linux/platform_data/gpio-davinci.h>
24 #include <linux/platform_data/keyscan-davinci.h>
25 #include <linux/platform_data/spi-davinci.h>
26 #include <linux/platform_device.h>
27 #include <linux/serial_8250.h>
28 #include <linux/spi/spi.h>
29
30 #include <asm/mach/map.h>
31
32 #include <mach/common.h>
33 #include <mach/cputype.h>
34 #include <mach/irqs.h>
35 #include <mach/mux.h>
36 #include <mach/serial.h>
37 #include <mach/time.h>
38
39 #include "asp.h"
40 #include "davinci.h"
41 #include "mux.h"
42
43 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
44 #define DM365_RTC_BASE                  0x01c69000
45 #define DM365_KEYSCAN_BASE              0x01c69400
46 #define DM365_OSD_BASE                  0x01c71c00
47 #define DM365_VENC_BASE                 0x01c71e00
48 #define DAVINCI_DM365_VC_BASE           0x01d0c000
49 #define DAVINCI_DMA_VC_TX               2
50 #define DAVINCI_DMA_VC_RX               3
51 #define DM365_EMAC_BASE                 0x01d07000
52 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
53 #define DM365_EMAC_CNTRL_OFFSET         0x0000
54 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
55 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
56 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
57
58 #define INTMUX          0x18
59 #define EVTMUX          0x1c
60
61
62 static const struct mux_config dm365_pins[] = {
63 #ifdef CONFIG_DAVINCI_MUX
64 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
65
66 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
67 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
68 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
69 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
70 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
71 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
72
73 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
74 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
75
76 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
77 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
78 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
79 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
80 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
81 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
82 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
83 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
84
85 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
86 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
87 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
88 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
89 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
90 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
91
92 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
93 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
94 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
95 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
96 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
97
98 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
99 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
100 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
101 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
102 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
103 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
104
105 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
106 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
107 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
108 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
109 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
110 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
111 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
112 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
113 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
114 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
115 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
116 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
117 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
118 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
119 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
120 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
121 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
122
123 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
124
125 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
126 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
127 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
128 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
129 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
130 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
131 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
132 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
133 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
134 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
135 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
136 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
137
138 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
139 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
140 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
141 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
142 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
143
144 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
145 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
146 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
147 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
148 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
149
150 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
151 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
152 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
153 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
154 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
155
156 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
157 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
158 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
159 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
160 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
161
162 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
163 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
164 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
165
166 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
167 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
168 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
169 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
170 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
171 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
172 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
173
174 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
175 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
176 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
177 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
178 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
179 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
180 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
181 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
182 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
183 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
184
185 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
186 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
187 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
188 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
189 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
190 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
191 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
192 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
193 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
194 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
195 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
196 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
197 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
198 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
199 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
200 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
201 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
202 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
203
204 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
205 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
206 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
207 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
208 #endif
209 };
210
211 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
212
213 static struct davinci_spi_platform_data dm365_spi0_pdata = {
214         .version        = SPI_VERSION_1,
215         .num_chipselect = 2,
216         .dma_event_q    = EVENTQ_3,
217         .prescaler_limit = 1,
218 };
219
220 static struct resource dm365_spi0_resources[] = {
221         {
222                 .start = 0x01c66000,
223                 .end   = 0x01c667ff,
224                 .flags = IORESOURCE_MEM,
225         },
226         {
227                 .start = IRQ_DM365_SPIINT0_0,
228                 .flags = IORESOURCE_IRQ,
229         },
230 };
231
232 static struct platform_device dm365_spi0_device = {
233         .name = "spi_davinci",
234         .id = 0,
235         .dev = {
236                 .dma_mask = &dm365_spi0_dma_mask,
237                 .coherent_dma_mask = DMA_BIT_MASK(32),
238                 .platform_data = &dm365_spi0_pdata,
239         },
240         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
241         .resource = dm365_spi0_resources,
242 };
243
244 void __init dm365_init_spi0(unsigned chipselect_mask,
245                 const struct spi_board_info *info, unsigned len)
246 {
247         davinci_cfg_reg(DM365_SPI0_SCLK);
248         davinci_cfg_reg(DM365_SPI0_SDI);
249         davinci_cfg_reg(DM365_SPI0_SDO);
250
251         /* not all slaves will be wired up */
252         if (chipselect_mask & BIT(0))
253                 davinci_cfg_reg(DM365_SPI0_SDENA0);
254         if (chipselect_mask & BIT(1))
255                 davinci_cfg_reg(DM365_SPI0_SDENA1);
256
257         spi_register_board_info(info, len);
258
259         platform_device_register(&dm365_spi0_device);
260 }
261
262 static struct resource dm365_gpio_resources[] = {
263         {       /* registers */
264                 .start  = DAVINCI_GPIO_BASE,
265                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
266                 .flags  = IORESOURCE_MEM,
267         },
268         {       /* interrupt */
269                 .start  = IRQ_DM365_GPIO0,
270                 .end    = IRQ_DM365_GPIO7,
271                 .flags  = IORESOURCE_IRQ,
272         },
273 };
274
275 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
276         .ngpio          = 104,
277         .gpio_unbanked  = 8,
278 };
279
280 int __init dm365_gpio_register(void)
281 {
282         return davinci_gpio_register(dm365_gpio_resources,
283                                      ARRAY_SIZE(dm365_gpio_resources),
284                                      &dm365_gpio_platform_data);
285 }
286
287 static struct emac_platform_data dm365_emac_pdata = {
288         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
289         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
290         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
291         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
292         .version                = EMAC_VERSION_2,
293 };
294
295 static struct resource dm365_emac_resources[] = {
296         {
297                 .start  = DM365_EMAC_BASE,
298                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
299                 .flags  = IORESOURCE_MEM,
300         },
301         {
302                 .start  = IRQ_DM365_EMAC_RXTHRESH,
303                 .end    = IRQ_DM365_EMAC_RXTHRESH,
304                 .flags  = IORESOURCE_IRQ,
305         },
306         {
307                 .start  = IRQ_DM365_EMAC_RXPULSE,
308                 .end    = IRQ_DM365_EMAC_RXPULSE,
309                 .flags  = IORESOURCE_IRQ,
310         },
311         {
312                 .start  = IRQ_DM365_EMAC_TXPULSE,
313                 .end    = IRQ_DM365_EMAC_TXPULSE,
314                 .flags  = IORESOURCE_IRQ,
315         },
316         {
317                 .start  = IRQ_DM365_EMAC_MISCPULSE,
318                 .end    = IRQ_DM365_EMAC_MISCPULSE,
319                 .flags  = IORESOURCE_IRQ,
320         },
321 };
322
323 static struct platform_device dm365_emac_device = {
324         .name           = "davinci_emac",
325         .id             = 1,
326         .dev = {
327                 .platform_data  = &dm365_emac_pdata,
328         },
329         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
330         .resource       = dm365_emac_resources,
331 };
332
333 static struct resource dm365_mdio_resources[] = {
334         {
335                 .start  = DM365_EMAC_MDIO_BASE,
336                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
337                 .flags  = IORESOURCE_MEM,
338         },
339 };
340
341 static struct platform_device dm365_mdio_device = {
342         .name           = "davinci_mdio",
343         .id             = 0,
344         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
345         .resource       = dm365_mdio_resources,
346 };
347
348 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
349         [IRQ_VDINT0]                    = 2,
350         [IRQ_VDINT1]                    = 6,
351         [IRQ_VDINT2]                    = 6,
352         [IRQ_HISTINT]                   = 6,
353         [IRQ_H3AINT]                    = 6,
354         [IRQ_PRVUINT]                   = 6,
355         [IRQ_RSZINT]                    = 6,
356         [IRQ_DM365_INSFINT]             = 7,
357         [IRQ_VENCINT]                   = 6,
358         [IRQ_ASQINT]                    = 6,
359         [IRQ_IMXINT]                    = 6,
360         [IRQ_DM365_IMCOPINT]            = 4,
361         [IRQ_USBINT]                    = 4,
362         [IRQ_DM365_RTOINT]              = 7,
363         [IRQ_DM365_TINT5]               = 7,
364         [IRQ_DM365_TINT6]               = 5,
365         [IRQ_CCINT0]                    = 5,
366         [IRQ_CCERRINT]                  = 5,
367         [IRQ_TCERRINT0]                 = 5,
368         [IRQ_TCERRINT]                  = 7,
369         [IRQ_PSCIN]                     = 4,
370         [IRQ_DM365_SPINT2_1]            = 7,
371         [IRQ_DM365_TINT7]               = 7,
372         [IRQ_DM365_SDIOINT0]            = 7,
373         [IRQ_MBXINT]                    = 7,
374         [IRQ_MBRINT]                    = 7,
375         [IRQ_MMCINT]                    = 7,
376         [IRQ_DM365_MMCINT1]             = 7,
377         [IRQ_DM365_PWMINT3]             = 7,
378         [IRQ_AEMIFINT]                  = 2,
379         [IRQ_DM365_SDIOINT1]            = 2,
380         [IRQ_TINT0_TINT12]              = 7,
381         [IRQ_TINT0_TINT34]              = 7,
382         [IRQ_TINT1_TINT12]              = 7,
383         [IRQ_TINT1_TINT34]              = 7,
384         [IRQ_PWMINT0]                   = 7,
385         [IRQ_PWMINT1]                   = 3,
386         [IRQ_PWMINT2]                   = 3,
387         [IRQ_I2C]                       = 3,
388         [IRQ_UARTINT0]                  = 3,
389         [IRQ_UARTINT1]                  = 3,
390         [IRQ_DM365_RTCINT]              = 3,
391         [IRQ_DM365_SPIINT0_0]           = 3,
392         [IRQ_DM365_SPIINT3_0]           = 3,
393         [IRQ_DM365_GPIO0]               = 3,
394         [IRQ_DM365_GPIO1]               = 7,
395         [IRQ_DM365_GPIO2]               = 4,
396         [IRQ_DM365_GPIO3]               = 4,
397         [IRQ_DM365_GPIO4]               = 7,
398         [IRQ_DM365_GPIO5]               = 7,
399         [IRQ_DM365_GPIO6]               = 7,
400         [IRQ_DM365_GPIO7]               = 7,
401         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
402         [IRQ_DM365_EMAC_RXPULSE]        = 7,
403         [IRQ_DM365_EMAC_TXPULSE]        = 7,
404         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
405         [IRQ_DM365_GPIO12]              = 7,
406         [IRQ_DM365_GPIO13]              = 7,
407         [IRQ_DM365_GPIO14]              = 7,
408         [IRQ_DM365_GPIO15]              = 7,
409         [IRQ_DM365_KEYINT]              = 7,
410         [IRQ_DM365_TCERRINT2]           = 7,
411         [IRQ_DM365_TCERRINT3]           = 7,
412         [IRQ_DM365_EMUINT]              = 7,
413 };
414
415 /* Four Transfer Controllers on DM365 */
416 static s8 dm365_queue_priority_mapping[][2] = {
417         /* {event queue no, Priority} */
418         {0, 7},
419         {1, 7},
420         {2, 7},
421         {3, 0},
422         {-1, -1},
423 };
424
425 static const struct dma_slave_map dm365_edma_map[] = {
426         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
427         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
428         { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
429         { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
430         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
431         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
432         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
433         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
434         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
435         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
436         { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
437         { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
438         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
439         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
440         { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
441         { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
442 };
443
444 static struct edma_soc_info dm365_edma_pdata = {
445         .queue_priority_mapping = dm365_queue_priority_mapping,
446         .default_queue          = EVENTQ_3,
447         .slave_map              = dm365_edma_map,
448         .slavecnt               = ARRAY_SIZE(dm365_edma_map),
449 };
450
451 static struct resource edma_resources[] = {
452         {
453                 .name   = "edma3_cc",
454                 .start  = 0x01c00000,
455                 .end    = 0x01c00000 + SZ_64K - 1,
456                 .flags  = IORESOURCE_MEM,
457         },
458         {
459                 .name   = "edma3_tc0",
460                 .start  = 0x01c10000,
461                 .end    = 0x01c10000 + SZ_1K - 1,
462                 .flags  = IORESOURCE_MEM,
463         },
464         {
465                 .name   = "edma3_tc1",
466                 .start  = 0x01c10400,
467                 .end    = 0x01c10400 + SZ_1K - 1,
468                 .flags  = IORESOURCE_MEM,
469         },
470         {
471                 .name   = "edma3_tc2",
472                 .start  = 0x01c10800,
473                 .end    = 0x01c10800 + SZ_1K - 1,
474                 .flags  = IORESOURCE_MEM,
475         },
476         {
477                 .name   = "edma3_tc3",
478                 .start  = 0x01c10c00,
479                 .end    = 0x01c10c00 + SZ_1K - 1,
480                 .flags  = IORESOURCE_MEM,
481         },
482         {
483                 .name   = "edma3_ccint",
484                 .start  = IRQ_CCINT0,
485                 .flags  = IORESOURCE_IRQ,
486         },
487         {
488                 .name   = "edma3_ccerrint",
489                 .start  = IRQ_CCERRINT,
490                 .flags  = IORESOURCE_IRQ,
491         },
492         /* not using TC*_ERR */
493 };
494
495 static const struct platform_device_info dm365_edma_device __initconst = {
496         .name           = "edma",
497         .id             = 0,
498         .dma_mask       = DMA_BIT_MASK(32),
499         .res            = edma_resources,
500         .num_res        = ARRAY_SIZE(edma_resources),
501         .data           = &dm365_edma_pdata,
502         .size_data      = sizeof(dm365_edma_pdata),
503 };
504
505 static struct resource dm365_asp_resources[] = {
506         {
507                 .name   = "mpu",
508                 .start  = DAVINCI_DM365_ASP0_BASE,
509                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
510                 .flags  = IORESOURCE_MEM,
511         },
512         {
513                 .start  = DAVINCI_DMA_ASP0_TX,
514                 .end    = DAVINCI_DMA_ASP0_TX,
515                 .flags  = IORESOURCE_DMA,
516         },
517         {
518                 .start  = DAVINCI_DMA_ASP0_RX,
519                 .end    = DAVINCI_DMA_ASP0_RX,
520                 .flags  = IORESOURCE_DMA,
521         },
522 };
523
524 static struct platform_device dm365_asp_device = {
525         .name           = "davinci-mcbsp",
526         .id             = -1,
527         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
528         .resource       = dm365_asp_resources,
529 };
530
531 static struct resource dm365_vc_resources[] = {
532         {
533                 .start  = DAVINCI_DM365_VC_BASE,
534                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
535                 .flags  = IORESOURCE_MEM,
536         },
537         {
538                 .start  = DAVINCI_DMA_VC_TX,
539                 .end    = DAVINCI_DMA_VC_TX,
540                 .flags  = IORESOURCE_DMA,
541         },
542         {
543                 .start  = DAVINCI_DMA_VC_RX,
544                 .end    = DAVINCI_DMA_VC_RX,
545                 .flags  = IORESOURCE_DMA,
546         },
547 };
548
549 static struct platform_device dm365_vc_device = {
550         .name           = "davinci_voicecodec",
551         .id             = -1,
552         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
553         .resource       = dm365_vc_resources,
554 };
555
556 static struct resource dm365_rtc_resources[] = {
557         {
558                 .start = DM365_RTC_BASE,
559                 .end = DM365_RTC_BASE + SZ_1K - 1,
560                 .flags = IORESOURCE_MEM,
561         },
562         {
563                 .start = IRQ_DM365_RTCINT,
564                 .flags = IORESOURCE_IRQ,
565         },
566 };
567
568 static struct platform_device dm365_rtc_device = {
569         .name = "rtc_davinci",
570         .id = 0,
571         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
572         .resource = dm365_rtc_resources,
573 };
574
575 static struct map_desc dm365_io_desc[] = {
576         {
577                 .virtual        = IO_VIRT,
578                 .pfn            = __phys_to_pfn(IO_PHYS),
579                 .length         = IO_SIZE,
580                 .type           = MT_DEVICE
581         },
582 };
583
584 static struct resource dm365_ks_resources[] = {
585         {
586                 /* registers */
587                 .start = DM365_KEYSCAN_BASE,
588                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
589                 .flags = IORESOURCE_MEM,
590         },
591         {
592                 /* interrupt */
593                 .start = IRQ_DM365_KEYINT,
594                 .end = IRQ_DM365_KEYINT,
595                 .flags = IORESOURCE_IRQ,
596         },
597 };
598
599 static struct platform_device dm365_ks_device = {
600         .name           = "davinci_keyscan",
601         .id             = 0,
602         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
603         .resource       = dm365_ks_resources,
604 };
605
606 /* Contents of JTAG ID register used to identify exact cpu type */
607 static struct davinci_id dm365_ids[] = {
608         {
609                 .variant        = 0x0,
610                 .part_no        = 0xb83e,
611                 .manufacturer   = 0x017,
612                 .cpu_id         = DAVINCI_CPU_ID_DM365,
613                 .name           = "dm365_rev1.1",
614         },
615         {
616                 .variant        = 0x8,
617                 .part_no        = 0xb83e,
618                 .manufacturer   = 0x017,
619                 .cpu_id         = DAVINCI_CPU_ID_DM365,
620                 .name           = "dm365_rev1.2",
621         },
622 };
623
624 static struct davinci_timer_info dm365_timer_info = {
625         .timers         = davinci_timer_instance,
626         .clockevent_id  = T0_BOT,
627         .clocksource_id = T0_TOP,
628 };
629
630 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
631
632 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
633         {
634                 .mapbase        = DAVINCI_UART0_BASE,
635                 .irq            = IRQ_UARTINT0,
636                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
637                                   UPF_IOREMAP,
638                 .iotype         = UPIO_MEM,
639                 .regshift       = 2,
640         },
641         {
642                 .flags  = 0,
643         }
644 };
645 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
646         {
647                 .mapbase        = DM365_UART1_BASE,
648                 .irq            = IRQ_UARTINT1,
649                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
650                                   UPF_IOREMAP,
651                 .iotype         = UPIO_MEM,
652                 .regshift       = 2,
653         },
654         {
655                 .flags  = 0,
656         }
657 };
658
659 struct platform_device dm365_serial_device[] = {
660         {
661                 .name                   = "serial8250",
662                 .id                     = PLAT8250_DEV_PLATFORM,
663                 .dev                    = {
664                         .platform_data  = dm365_serial0_platform_data,
665                 }
666         },
667         {
668                 .name                   = "serial8250",
669                 .id                     = PLAT8250_DEV_PLATFORM1,
670                 .dev                    = {
671                         .platform_data  = dm365_serial1_platform_data,
672                 }
673         },
674         {
675         }
676 };
677
678 static const struct davinci_soc_info davinci_soc_info_dm365 = {
679         .io_desc                = dm365_io_desc,
680         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
681         .jtag_id_reg            = 0x01c40028,
682         .ids                    = dm365_ids,
683         .ids_num                = ARRAY_SIZE(dm365_ids),
684         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
685         .pinmux_pins            = dm365_pins,
686         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
687         .intc_base              = DAVINCI_ARM_INTC_BASE,
688         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
689         .intc_irq_prios         = dm365_default_priorities,
690         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
691         .timer_info             = &dm365_timer_info,
692         .emac_pdata             = &dm365_emac_pdata,
693         .sram_dma               = 0x00010000,
694         .sram_len               = SZ_32K,
695 };
696
697 void __init dm365_init_asp(void)
698 {
699         davinci_cfg_reg(DM365_MCBSP0_BDX);
700         davinci_cfg_reg(DM365_MCBSP0_X);
701         davinci_cfg_reg(DM365_MCBSP0_BFSX);
702         davinci_cfg_reg(DM365_MCBSP0_BDR);
703         davinci_cfg_reg(DM365_MCBSP0_R);
704         davinci_cfg_reg(DM365_MCBSP0_BFSR);
705         davinci_cfg_reg(DM365_EVT2_ASP_TX);
706         davinci_cfg_reg(DM365_EVT3_ASP_RX);
707         platform_device_register(&dm365_asp_device);
708 }
709
710 void __init dm365_init_vc(void)
711 {
712         davinci_cfg_reg(DM365_EVT2_VC_TX);
713         davinci_cfg_reg(DM365_EVT3_VC_RX);
714         platform_device_register(&dm365_vc_device);
715 }
716
717 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
718 {
719         dm365_ks_device.dev.platform_data = pdata;
720         platform_device_register(&dm365_ks_device);
721 }
722
723 void __init dm365_init_rtc(void)
724 {
725         davinci_cfg_reg(DM365_INT_PRTCSS);
726         platform_device_register(&dm365_rtc_device);
727 }
728
729 void __init dm365_init(void)
730 {
731         davinci_common_init(&davinci_soc_info_dm365);
732         davinci_map_sysmod();
733 }
734
735 void __init dm365_init_time(void)
736 {
737         void __iomem *pll1, *pll2, *psc;
738         struct clk *clk;
739
740         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
741
742         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
743         dm365_pll1_init(NULL, pll1, NULL);
744
745         pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
746         dm365_pll2_init(NULL, pll2, NULL);
747
748         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
749         dm365_psc_init(NULL, psc);
750
751         clk = clk_get(NULL, "timer0");
752
753         davinci_timer_init(clk);
754 }
755
756 void __init dm365_register_clocks(void)
757 {
758         /* all clocks are currently registered in dm365_init_time() */
759 }
760
761 static struct resource dm365_vpss_resources[] = {
762         {
763                 /* VPSS ISP5 Base address */
764                 .name           = "isp5",
765                 .start          = 0x01c70000,
766                 .end            = 0x01c70000 + 0xff,
767                 .flags          = IORESOURCE_MEM,
768         },
769         {
770                 /* VPSS CLK Base address */
771                 .name           = "vpss",
772                 .start          = 0x01c70200,
773                 .end            = 0x01c70200 + 0xff,
774                 .flags          = IORESOURCE_MEM,
775         },
776 };
777
778 static struct platform_device dm365_vpss_device = {
779        .name                   = "vpss",
780        .id                     = -1,
781        .dev.platform_data      = "dm365_vpss",
782        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
783        .resource               = dm365_vpss_resources,
784 };
785
786 static struct resource vpfe_resources[] = {
787         {
788                 .start          = IRQ_VDINT0,
789                 .end            = IRQ_VDINT0,
790                 .flags          = IORESOURCE_IRQ,
791         },
792         {
793                 .start          = IRQ_VDINT1,
794                 .end            = IRQ_VDINT1,
795                 .flags          = IORESOURCE_IRQ,
796         },
797 };
798
799 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
800 static struct platform_device vpfe_capture_dev = {
801         .name           = CAPTURE_DRV_NAME,
802         .id             = -1,
803         .num_resources  = ARRAY_SIZE(vpfe_resources),
804         .resource       = vpfe_resources,
805         .dev = {
806                 .dma_mask               = &vpfe_capture_dma_mask,
807                 .coherent_dma_mask      = DMA_BIT_MASK(32),
808         },
809 };
810
811 static void dm365_isif_setup_pinmux(void)
812 {
813         davinci_cfg_reg(DM365_VIN_CAM_WEN);
814         davinci_cfg_reg(DM365_VIN_CAM_VD);
815         davinci_cfg_reg(DM365_VIN_CAM_HD);
816         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
817         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
818 }
819
820 static struct resource isif_resource[] = {
821         /* ISIF Base address */
822         {
823                 .start          = 0x01c71000,
824                 .end            = 0x01c71000 + 0x1ff,
825                 .flags          = IORESOURCE_MEM,
826         },
827         /* ISIF Linearization table 0 */
828         {
829                 .start          = 0x1C7C000,
830                 .end            = 0x1C7C000 + 0x2ff,
831                 .flags          = IORESOURCE_MEM,
832         },
833         /* ISIF Linearization table 1 */
834         {
835                 .start          = 0x1C7C400,
836                 .end            = 0x1C7C400 + 0x2ff,
837                 .flags          = IORESOURCE_MEM,
838         },
839 };
840 static struct platform_device dm365_isif_dev = {
841         .name           = "isif",
842         .id             = -1,
843         .num_resources  = ARRAY_SIZE(isif_resource),
844         .resource       = isif_resource,
845         .dev = {
846                 .dma_mask               = &vpfe_capture_dma_mask,
847                 .coherent_dma_mask      = DMA_BIT_MASK(32),
848                 .platform_data          = dm365_isif_setup_pinmux,
849         },
850 };
851
852 static struct resource dm365_osd_resources[] = {
853         {
854                 .start = DM365_OSD_BASE,
855                 .end   = DM365_OSD_BASE + 0xff,
856                 .flags = IORESOURCE_MEM,
857         },
858 };
859
860 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
861
862 static struct platform_device dm365_osd_dev = {
863         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
864         .id             = -1,
865         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
866         .resource       = dm365_osd_resources,
867         .dev            = {
868                 .dma_mask               = &dm365_video_dma_mask,
869                 .coherent_dma_mask      = DMA_BIT_MASK(32),
870         },
871 };
872
873 static struct resource dm365_venc_resources[] = {
874         {
875                 .start = IRQ_VENCINT,
876                 .end   = IRQ_VENCINT,
877                 .flags = IORESOURCE_IRQ,
878         },
879         /* venc registers io space */
880         {
881                 .start = DM365_VENC_BASE,
882                 .end   = DM365_VENC_BASE + 0x177,
883                 .flags = IORESOURCE_MEM,
884         },
885         /* vdaccfg registers io space */
886         {
887                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
888                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
889                 .flags = IORESOURCE_MEM,
890         },
891 };
892
893 static struct resource dm365_v4l2_disp_resources[] = {
894         {
895                 .start = IRQ_VENCINT,
896                 .end   = IRQ_VENCINT,
897                 .flags = IORESOURCE_IRQ,
898         },
899         /* venc registers io space */
900         {
901                 .start = DM365_VENC_BASE,
902                 .end   = DM365_VENC_BASE + 0x177,
903                 .flags = IORESOURCE_MEM,
904         },
905 };
906
907 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
908 {
909         switch (if_type) {
910         case MEDIA_BUS_FMT_SGRBG8_1X8:
911                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
912                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
913                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
914                 break;
915         case MEDIA_BUS_FMT_YUYV10_1X20:
916                 if (field)
917                         davinci_cfg_reg(DM365_VOUT_FIELD);
918                 else
919                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
920                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
921                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
922                 break;
923         default:
924                 return -EINVAL;
925         }
926
927         return 0;
928 }
929
930 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
931                                   unsigned int pclock)
932 {
933         void __iomem *vpss_clkctl_reg;
934         u32 val;
935
936         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
937
938         switch (type) {
939         case VPBE_ENC_STD:
940                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
941                 break;
942         case VPBE_ENC_DV_TIMINGS:
943                 if (pclock <= 27000000) {
944                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
945                 } else {
946                         /* set sysclk4 to output 74.25 MHz from pll1 */
947                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
948                               VPSS_VENCCLKEN_ENABLE;
949                 }
950                 break;
951         default:
952                 return -EINVAL;
953         }
954         writel(val, vpss_clkctl_reg);
955
956         return 0;
957 }
958
959 static struct platform_device dm365_vpbe_display = {
960         .name           = "vpbe-v4l2",
961         .id             = -1,
962         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
963         .resource       = dm365_v4l2_disp_resources,
964         .dev            = {
965                 .dma_mask               = &dm365_video_dma_mask,
966                 .coherent_dma_mask      = DMA_BIT_MASK(32),
967         },
968 };
969
970 static struct venc_platform_data dm365_venc_pdata = {
971         .setup_pinmux   = dm365_vpbe_setup_pinmux,
972         .setup_clock    = dm365_venc_setup_clock,
973 };
974
975 static struct platform_device dm365_venc_dev = {
976         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
977         .id             = -1,
978         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
979         .resource       = dm365_venc_resources,
980         .dev            = {
981                 .dma_mask               = &dm365_video_dma_mask,
982                 .coherent_dma_mask      = DMA_BIT_MASK(32),
983                 .platform_data          = (void *)&dm365_venc_pdata,
984         },
985 };
986
987 static struct platform_device dm365_vpbe_dev = {
988         .name           = "vpbe_controller",
989         .id             = -1,
990         .dev            = {
991                 .dma_mask               = &dm365_video_dma_mask,
992                 .coherent_dma_mask      = DMA_BIT_MASK(32),
993         },
994 };
995
996 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
997                                 struct vpbe_config *vpbe_cfg)
998 {
999         if (vpfe_cfg || vpbe_cfg)
1000                 platform_device_register(&dm365_vpss_device);
1001
1002         if (vpfe_cfg) {
1003                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1004                 platform_device_register(&dm365_isif_dev);
1005                 platform_device_register(&vpfe_capture_dev);
1006         }
1007         if (vpbe_cfg) {
1008                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1009                 platform_device_register(&dm365_osd_dev);
1010                 platform_device_register(&dm365_venc_dev);
1011                 platform_device_register(&dm365_vpbe_dev);
1012                 platform_device_register(&dm365_vpbe_display);
1013         }
1014
1015         return 0;
1016 }
1017
1018 static int __init dm365_init_devices(void)
1019 {
1020         struct platform_device *edma_pdev;
1021         int ret = 0;
1022
1023         if (!cpu_is_davinci_dm365())
1024                 return 0;
1025
1026         davinci_cfg_reg(DM365_INT_EDMA_CC);
1027         edma_pdev = platform_device_register_full(&dm365_edma_device);
1028         if (IS_ERR(edma_pdev)) {
1029                 pr_warn("%s: Failed to register eDMA\n", __func__);
1030                 return PTR_ERR(edma_pdev);
1031         }
1032
1033         platform_device_register(&dm365_mdio_device);
1034         platform_device_register(&dm365_emac_device);
1035
1036         ret = davinci_init_wdt();
1037         if (ret)
1038                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1039
1040         return ret;
1041 }
1042 postcore_initcall(dm365_init_devices);