Merge tag 'davinci-fixes-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel...
[muen/linux.git] / arch / arm / mach-davinci / dm644x.c
1 /*
2  * TI DaVinci DM644x chip specific setup
3  *
4  * Author: Kevin Hilman, Deep Root Systems, LLC
5  *
6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  */
11
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dmaengine.h>
16 #include <linux/init.h>
17 #include <linux/platform_data/edma.h>
18 #include <linux/platform_data/gpio-davinci.h>
19 #include <linux/platform_device.h>
20 #include <linux/serial_8250.h>
21
22 #include <asm/mach/map.h>
23
24 #include <mach/common.h>
25 #include <mach/cputype.h>
26 #include <mach/irqs.h>
27 #include <mach/mux.h>
28 #include <mach/serial.h>
29 #include <mach/time.h>
30
31 #include "asp.h"
32 #include "davinci.h"
33 #include "mux.h"
34
35 /*
36  * Device specific clocks
37  */
38 #define DM644X_REF_FREQ         27000000
39
40 #define DM644X_EMAC_BASE                0x01c80000
41 #define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
42 #define DM644X_EMAC_CNTRL_OFFSET        0x0000
43 #define DM644X_EMAC_CNTRL_MOD_OFFSET    0x1000
44 #define DM644X_EMAC_CNTRL_RAM_OFFSET    0x2000
45 #define DM644X_EMAC_CNTRL_RAM_SIZE      0x2000
46
47 static struct emac_platform_data dm644x_emac_pdata = {
48         .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
49         .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
50         .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
51         .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
52         .version                = EMAC_VERSION_1,
53 };
54
55 static struct resource dm644x_emac_resources[] = {
56         {
57                 .start  = DM644X_EMAC_BASE,
58                 .end    = DM644X_EMAC_BASE + SZ_16K - 1,
59                 .flags  = IORESOURCE_MEM,
60         },
61         {
62                 .start = IRQ_EMACINT,
63                 .end   = IRQ_EMACINT,
64                 .flags = IORESOURCE_IRQ,
65         },
66 };
67
68 static struct platform_device dm644x_emac_device = {
69        .name            = "davinci_emac",
70        .id              = 1,
71        .dev = {
72                .platform_data   = &dm644x_emac_pdata,
73        },
74        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
75        .resource        = dm644x_emac_resources,
76 };
77
78 static struct resource dm644x_mdio_resources[] = {
79         {
80                 .start  = DM644X_EMAC_MDIO_BASE,
81                 .end    = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
82                 .flags  = IORESOURCE_MEM,
83         },
84 };
85
86 static struct platform_device dm644x_mdio_device = {
87         .name           = "davinci_mdio",
88         .id             = 0,
89         .num_resources  = ARRAY_SIZE(dm644x_mdio_resources),
90         .resource       = dm644x_mdio_resources,
91 };
92
93 /*
94  * Device specific mux setup
95  *
96  *      soc     description     mux  mode   mode  mux    dbg
97  *                              reg  offset mask  mode
98  */
99 static const struct mux_config dm644x_pins[] = {
100 #ifdef CONFIG_DAVINCI_MUX
101 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
102 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
103 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
104
105 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
106
107 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
108 MUX_CFG(DM644X, AEAW0,          0,   0,     1,    0,     true)
109 MUX_CFG(DM644X, AEAW1,          0,   1,     1,    0,     true)
110 MUX_CFG(DM644X, AEAW2,          0,   2,     1,    0,     true)
111 MUX_CFG(DM644X, AEAW3,          0,   3,     1,    0,     true)
112 MUX_CFG(DM644X, AEAW4,          0,   4,     1,    0,     true)
113
114 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
115
116 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
117
118 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
119
120 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
121 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
122
123 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
124
125 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
126
127 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
128
129 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
130 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
131 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
132
133 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
134
135 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
136
137 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
138 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
139 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
140 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
141
142 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
143
144 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
145 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
146 #endif
147 };
148
149 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
150 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
151         [IRQ_VDINT0]            = 2,
152         [IRQ_VDINT1]            = 6,
153         [IRQ_VDINT2]            = 6,
154         [IRQ_HISTINT]           = 6,
155         [IRQ_H3AINT]            = 6,
156         [IRQ_PRVUINT]           = 6,
157         [IRQ_RSZINT]            = 6,
158         [7]                     = 7,
159         [IRQ_VENCINT]           = 6,
160         [IRQ_ASQINT]            = 6,
161         [IRQ_IMXINT]            = 6,
162         [IRQ_VLCDINT]           = 6,
163         [IRQ_USBINT]            = 4,
164         [IRQ_EMACINT]           = 4,
165         [14]                    = 7,
166         [15]                    = 7,
167         [IRQ_CCINT0]            = 5,    /* dma */
168         [IRQ_CCERRINT]          = 5,    /* dma */
169         [IRQ_TCERRINT0]         = 5,    /* dma */
170         [IRQ_TCERRINT]          = 5,    /* dma */
171         [IRQ_PSCIN]             = 7,
172         [21]                    = 7,
173         [IRQ_IDE]               = 4,
174         [23]                    = 7,
175         [IRQ_MBXINT]            = 7,
176         [IRQ_MBRINT]            = 7,
177         [IRQ_MMCINT]            = 7,
178         [IRQ_SDIOINT]           = 7,
179         [28]                    = 7,
180         [IRQ_DDRINT]            = 7,
181         [IRQ_AEMIFINT]          = 7,
182         [IRQ_VLQINT]            = 4,
183         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
184         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
185         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
186         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
187         [IRQ_PWMINT0]           = 7,
188         [IRQ_PWMINT1]           = 7,
189         [IRQ_PWMINT2]           = 7,
190         [IRQ_I2C]               = 3,
191         [IRQ_UARTINT0]          = 3,
192         [IRQ_UARTINT1]          = 3,
193         [IRQ_UARTINT2]          = 3,
194         [IRQ_SPINT0]            = 3,
195         [IRQ_SPINT1]            = 3,
196         [45]                    = 7,
197         [IRQ_DSP2ARM0]          = 4,
198         [IRQ_DSP2ARM1]          = 4,
199         [IRQ_GPIO0]             = 7,
200         [IRQ_GPIO1]             = 7,
201         [IRQ_GPIO2]             = 7,
202         [IRQ_GPIO3]             = 7,
203         [IRQ_GPIO4]             = 7,
204         [IRQ_GPIO5]             = 7,
205         [IRQ_GPIO6]             = 7,
206         [IRQ_GPIO7]             = 7,
207         [IRQ_GPIOBNK0]          = 7,
208         [IRQ_GPIOBNK1]          = 7,
209         [IRQ_GPIOBNK2]          = 7,
210         [IRQ_GPIOBNK3]          = 7,
211         [IRQ_GPIOBNK4]          = 7,
212         [IRQ_COMMTX]            = 7,
213         [IRQ_COMMRX]            = 7,
214         [IRQ_EMUINT]            = 7,
215 };
216
217 /*----------------------------------------------------------------------*/
218
219 static s8 queue_priority_mapping[][2] = {
220         /* {event queue no, Priority} */
221         {0, 3},
222         {1, 7},
223         {-1, -1},
224 };
225
226 static const struct dma_slave_map dm644x_edma_map[] = {
227         { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
228         { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
229         { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
230         { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
231         { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
232         { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
233 };
234
235 static struct edma_soc_info dm644x_edma_pdata = {
236         .queue_priority_mapping = queue_priority_mapping,
237         .default_queue          = EVENTQ_1,
238         .slave_map              = dm644x_edma_map,
239         .slavecnt               = ARRAY_SIZE(dm644x_edma_map),
240 };
241
242 static struct resource edma_resources[] = {
243         {
244                 .name   = "edma3_cc",
245                 .start  = 0x01c00000,
246                 .end    = 0x01c00000 + SZ_64K - 1,
247                 .flags  = IORESOURCE_MEM,
248         },
249         {
250                 .name   = "edma3_tc0",
251                 .start  = 0x01c10000,
252                 .end    = 0x01c10000 + SZ_1K - 1,
253                 .flags  = IORESOURCE_MEM,
254         },
255         {
256                 .name   = "edma3_tc1",
257                 .start  = 0x01c10400,
258                 .end    = 0x01c10400 + SZ_1K - 1,
259                 .flags  = IORESOURCE_MEM,
260         },
261         {
262                 .name   = "edma3_ccint",
263                 .start  = IRQ_CCINT0,
264                 .flags  = IORESOURCE_IRQ,
265         },
266         {
267                 .name   = "edma3_ccerrint",
268                 .start  = IRQ_CCERRINT,
269                 .flags  = IORESOURCE_IRQ,
270         },
271         /* not using TC*_ERR */
272 };
273
274 static const struct platform_device_info dm644x_edma_device __initconst = {
275         .name           = "edma",
276         .id             = 0,
277         .dma_mask       = DMA_BIT_MASK(32),
278         .res            = edma_resources,
279         .num_res        = ARRAY_SIZE(edma_resources),
280         .data           = &dm644x_edma_pdata,
281         .size_data      = sizeof(dm644x_edma_pdata),
282 };
283
284 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
285 static struct resource dm644x_asp_resources[] = {
286         {
287                 .name   = "mpu",
288                 .start  = DAVINCI_ASP0_BASE,
289                 .end    = DAVINCI_ASP0_BASE + SZ_8K - 1,
290                 .flags  = IORESOURCE_MEM,
291         },
292         {
293                 .start  = DAVINCI_DMA_ASP0_TX,
294                 .end    = DAVINCI_DMA_ASP0_TX,
295                 .flags  = IORESOURCE_DMA,
296         },
297         {
298                 .start  = DAVINCI_DMA_ASP0_RX,
299                 .end    = DAVINCI_DMA_ASP0_RX,
300                 .flags  = IORESOURCE_DMA,
301         },
302 };
303
304 static struct platform_device dm644x_asp_device = {
305         .name           = "davinci-mcbsp",
306         .id             = -1,
307         .num_resources  = ARRAY_SIZE(dm644x_asp_resources),
308         .resource       = dm644x_asp_resources,
309 };
310
311 #define DM644X_VPSS_BASE        0x01c73400
312
313 static struct resource dm644x_vpss_resources[] = {
314         {
315                 /* VPSS Base address */
316                 .name           = "vpss",
317                 .start          = DM644X_VPSS_BASE,
318                 .end            = DM644X_VPSS_BASE + 0xff,
319                 .flags          = IORESOURCE_MEM,
320         },
321 };
322
323 static struct platform_device dm644x_vpss_device = {
324         .name                   = "vpss",
325         .id                     = -1,
326         .dev.platform_data      = "dm644x_vpss",
327         .num_resources          = ARRAY_SIZE(dm644x_vpss_resources),
328         .resource               = dm644x_vpss_resources,
329 };
330
331 static struct resource dm644x_vpfe_resources[] = {
332         {
333                 .start          = IRQ_VDINT0,
334                 .end            = IRQ_VDINT0,
335                 .flags          = IORESOURCE_IRQ,
336         },
337         {
338                 .start          = IRQ_VDINT1,
339                 .end            = IRQ_VDINT1,
340                 .flags          = IORESOURCE_IRQ,
341         },
342 };
343
344 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
345 static struct resource dm644x_ccdc_resource[] = {
346         /* CCDC Base address */
347         {
348                 .start          = 0x01c70400,
349                 .end            = 0x01c70400 + 0xff,
350                 .flags          = IORESOURCE_MEM,
351         },
352 };
353
354 static struct platform_device dm644x_ccdc_dev = {
355         .name           = "dm644x_ccdc",
356         .id             = -1,
357         .num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),
358         .resource       = dm644x_ccdc_resource,
359         .dev = {
360                 .dma_mask               = &dm644x_video_dma_mask,
361                 .coherent_dma_mask      = DMA_BIT_MASK(32),
362         },
363 };
364
365 static struct platform_device dm644x_vpfe_dev = {
366         .name           = CAPTURE_DRV_NAME,
367         .id             = -1,
368         .num_resources  = ARRAY_SIZE(dm644x_vpfe_resources),
369         .resource       = dm644x_vpfe_resources,
370         .dev = {
371                 .dma_mask               = &dm644x_video_dma_mask,
372                 .coherent_dma_mask      = DMA_BIT_MASK(32),
373         },
374 };
375
376 #define DM644X_OSD_BASE         0x01c72600
377
378 static struct resource dm644x_osd_resources[] = {
379         {
380                 .start  = DM644X_OSD_BASE,
381                 .end    = DM644X_OSD_BASE + 0x1ff,
382                 .flags  = IORESOURCE_MEM,
383         },
384 };
385
386 static struct platform_device dm644x_osd_dev = {
387         .name           = DM644X_VPBE_OSD_SUBDEV_NAME,
388         .id             = -1,
389         .num_resources  = ARRAY_SIZE(dm644x_osd_resources),
390         .resource       = dm644x_osd_resources,
391         .dev            = {
392                 .dma_mask               = &dm644x_video_dma_mask,
393                 .coherent_dma_mask      = DMA_BIT_MASK(32),
394         },
395 };
396
397 #define DM644X_VENC_BASE                0x01c72400
398
399 static struct resource dm644x_venc_resources[] = {
400         {
401                 .start  = DM644X_VENC_BASE,
402                 .end    = DM644X_VENC_BASE + 0x17f,
403                 .flags  = IORESOURCE_MEM,
404         },
405 };
406
407 #define DM644X_VPSS_MUXSEL_PLL2_MODE          BIT(0)
408 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE       BIT(1)
409 #define DM644X_VPSS_VENCLKEN                  BIT(3)
410 #define DM644X_VPSS_DACCLKEN                  BIT(4)
411
412 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
413                                    unsigned int pclock)
414 {
415         int ret = 0;
416         u32 v = DM644X_VPSS_VENCLKEN;
417
418         switch (type) {
419         case VPBE_ENC_STD:
420                 v |= DM644X_VPSS_DACCLKEN;
421                 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
422                 break;
423         case VPBE_ENC_DV_TIMINGS:
424                 if (pclock <= 27000000) {
425                         v |= DM644X_VPSS_DACCLKEN;
426                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
427                 } else {
428                         /*
429                          * For HD, use external clock source since
430                          * HD requires higher clock rate
431                          */
432                         v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
433                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
434                 }
435                 break;
436         default:
437                 ret  = -EINVAL;
438         }
439
440         return ret;
441 }
442
443 static struct resource dm644x_v4l2_disp_resources[] = {
444         {
445                 .start  = IRQ_VENCINT,
446                 .end    = IRQ_VENCINT,
447                 .flags  = IORESOURCE_IRQ,
448         },
449 };
450
451 static struct platform_device dm644x_vpbe_display = {
452         .name           = "vpbe-v4l2",
453         .id             = -1,
454         .num_resources  = ARRAY_SIZE(dm644x_v4l2_disp_resources),
455         .resource       = dm644x_v4l2_disp_resources,
456         .dev            = {
457                 .dma_mask               = &dm644x_video_dma_mask,
458                 .coherent_dma_mask      = DMA_BIT_MASK(32),
459         },
460 };
461
462 static struct venc_platform_data dm644x_venc_pdata = {
463         .setup_clock    = dm644x_venc_setup_clock,
464 };
465
466 static struct platform_device dm644x_venc_dev = {
467         .name           = DM644X_VPBE_VENC_SUBDEV_NAME,
468         .id             = -1,
469         .num_resources  = ARRAY_SIZE(dm644x_venc_resources),
470         .resource       = dm644x_venc_resources,
471         .dev            = {
472                 .dma_mask               = &dm644x_video_dma_mask,
473                 .coherent_dma_mask      = DMA_BIT_MASK(32),
474                 .platform_data          = &dm644x_venc_pdata,
475         },
476 };
477
478 static struct platform_device dm644x_vpbe_dev = {
479         .name           = "vpbe_controller",
480         .id             = -1,
481         .dev            = {
482                 .dma_mask               = &dm644x_video_dma_mask,
483                 .coherent_dma_mask      = DMA_BIT_MASK(32),
484         },
485 };
486
487 static struct resource dm644_gpio_resources[] = {
488         {       /* registers */
489                 .start  = DAVINCI_GPIO_BASE,
490                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
491                 .flags  = IORESOURCE_MEM,
492         },
493         {       /* interrupt */
494                 .start  = IRQ_GPIOBNK0,
495                 .end    = IRQ_GPIOBNK0,
496                 .flags  = IORESOURCE_IRQ,
497         },
498         {
499                 .start  = IRQ_GPIOBNK1,
500                 .end    = IRQ_GPIOBNK1,
501                 .flags  = IORESOURCE_IRQ,
502         },
503         {
504                 .start  = IRQ_GPIOBNK2,
505                 .end    = IRQ_GPIOBNK2,
506                 .flags  = IORESOURCE_IRQ,
507         },
508         {
509                 .start  = IRQ_GPIOBNK3,
510                 .end    = IRQ_GPIOBNK3,
511                 .flags  = IORESOURCE_IRQ,
512         },
513         {
514                 .start  = IRQ_GPIOBNK4,
515                 .end    = IRQ_GPIOBNK4,
516                 .flags  = IORESOURCE_IRQ,
517         },
518 };
519
520 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
521         .no_auto_base   = true,
522         .base           = 0,
523         .ngpio          = 71,
524 };
525
526 int __init dm644x_gpio_register(void)
527 {
528         return davinci_gpio_register(dm644_gpio_resources,
529                                      ARRAY_SIZE(dm644_gpio_resources),
530                                      &dm644_gpio_platform_data);
531 }
532 /*----------------------------------------------------------------------*/
533
534 static struct map_desc dm644x_io_desc[] = {
535         {
536                 .virtual        = IO_VIRT,
537                 .pfn            = __phys_to_pfn(IO_PHYS),
538                 .length         = IO_SIZE,
539                 .type           = MT_DEVICE
540         },
541 };
542
543 /* Contents of JTAG ID register used to identify exact cpu type */
544 static struct davinci_id dm644x_ids[] = {
545         {
546                 .variant        = 0x0,
547                 .part_no        = 0xb700,
548                 .manufacturer   = 0x017,
549                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
550                 .name           = "dm6446",
551         },
552         {
553                 .variant        = 0x1,
554                 .part_no        = 0xb700,
555                 .manufacturer   = 0x017,
556                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
557                 .name           = "dm6446a",
558         },
559 };
560
561 /*
562  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
563  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
564  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
565  * T1_TOP: Timer 1, top   :  <unused>
566  */
567 static struct davinci_timer_info dm644x_timer_info = {
568         .timers         = davinci_timer_instance,
569         .clockevent_id  = T0_BOT,
570         .clocksource_id = T0_TOP,
571 };
572
573 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
574         {
575                 .mapbase        = DAVINCI_UART0_BASE,
576                 .irq            = IRQ_UARTINT0,
577                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
578                                   UPF_IOREMAP,
579                 .iotype         = UPIO_MEM,
580                 .regshift       = 2,
581         },
582         {
583                 .flags  = 0,
584         }
585 };
586 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
587         {
588                 .mapbase        = DAVINCI_UART1_BASE,
589                 .irq            = IRQ_UARTINT1,
590                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
591                                   UPF_IOREMAP,
592                 .iotype         = UPIO_MEM,
593                 .regshift       = 2,
594         },
595         {
596                 .flags  = 0,
597         }
598 };
599 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
600         {
601                 .mapbase        = DAVINCI_UART2_BASE,
602                 .irq            = IRQ_UARTINT2,
603                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
604                                   UPF_IOREMAP,
605                 .iotype         = UPIO_MEM,
606                 .regshift       = 2,
607         },
608         {
609                 .flags  = 0,
610         }
611 };
612
613 struct platform_device dm644x_serial_device[] = {
614         {
615                 .name                   = "serial8250",
616                 .id                     = PLAT8250_DEV_PLATFORM,
617                 .dev                    = {
618                         .platform_data  = dm644x_serial0_platform_data,
619                 }
620         },
621         {
622                 .name                   = "serial8250",
623                 .id                     = PLAT8250_DEV_PLATFORM1,
624                 .dev                    = {
625                         .platform_data  = dm644x_serial1_platform_data,
626                 }
627         },
628         {
629                 .name                   = "serial8250",
630                 .id                     = PLAT8250_DEV_PLATFORM2,
631                 .dev                    = {
632                         .platform_data  = dm644x_serial2_platform_data,
633                 }
634         },
635         {
636         }
637 };
638
639 static const struct davinci_soc_info davinci_soc_info_dm644x = {
640         .io_desc                = dm644x_io_desc,
641         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
642         .jtag_id_reg            = 0x01c40028,
643         .ids                    = dm644x_ids,
644         .ids_num                = ARRAY_SIZE(dm644x_ids),
645         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
646         .pinmux_pins            = dm644x_pins,
647         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
648         .intc_base              = DAVINCI_ARM_INTC_BASE,
649         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
650         .intc_irq_prios         = dm644x_default_priorities,
651         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
652         .timer_info             = &dm644x_timer_info,
653         .emac_pdata             = &dm644x_emac_pdata,
654         .sram_dma               = 0x00008000,
655         .sram_len               = SZ_16K,
656 };
657
658 void __init dm644x_init_asp(void)
659 {
660         davinci_cfg_reg(DM644X_MCBSP);
661         platform_device_register(&dm644x_asp_device);
662 }
663
664 void __init dm644x_init(void)
665 {
666         davinci_common_init(&davinci_soc_info_dm644x);
667         davinci_map_sysmod();
668 }
669
670 void __init dm644x_init_time(void)
671 {
672         void __iomem *pll1, *psc;
673         struct clk *clk;
674
675         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
676
677         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
678         dm644x_pll1_init(NULL, pll1, NULL);
679
680         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
681         dm644x_psc_init(NULL, psc);
682
683         clk = clk_get(NULL, "timer0");
684
685         davinci_timer_init(clk);
686 }
687
688 static struct resource dm644x_pll2_resources[] = {
689         {
690                 .start  = DAVINCI_PLL2_BASE,
691                 .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
692                 .flags  = IORESOURCE_MEM,
693         },
694 };
695
696 static struct platform_device dm644x_pll2_device = {
697         .name           = "dm644x-pll2",
698         .id             = -1,
699         .resource       = dm644x_pll2_resources,
700         .num_resources  = ARRAY_SIZE(dm644x_pll2_resources),
701 };
702
703 void __init dm644x_register_clocks(void)
704 {
705         /* PLL1 and PSC are registered in dm644x_init_time() */
706         platform_device_register(&dm644x_pll2_device);
707 }
708
709 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
710                                 struct vpbe_config *vpbe_cfg)
711 {
712         if (vpfe_cfg || vpbe_cfg)
713                 platform_device_register(&dm644x_vpss_device);
714
715         if (vpfe_cfg) {
716                 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
717                 platform_device_register(&dm644x_ccdc_dev);
718                 platform_device_register(&dm644x_vpfe_dev);
719         }
720
721         if (vpbe_cfg) {
722                 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
723                 platform_device_register(&dm644x_osd_dev);
724                 platform_device_register(&dm644x_venc_dev);
725                 platform_device_register(&dm644x_vpbe_dev);
726                 platform_device_register(&dm644x_vpbe_display);
727         }
728
729         return 0;
730 }
731
732 void __init dm644x_init_devices(void)
733 {
734         struct platform_device *edma_pdev;
735         int ret;
736
737         edma_pdev = platform_device_register_full(&dm644x_edma_device);
738         if (IS_ERR(edma_pdev))
739                 pr_warn("%s: Failed to register eDMA\n", __func__);
740
741         platform_device_register(&dm644x_mdio_device);
742         platform_device_register(&dm644x_emac_device);
743
744         ret = davinci_init_wdt();
745         if (ret)
746                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
747
748 }