2334ba05b12e9a72721b2288752b553432f65ca5
[muen/linux.git] / arch / arm64 / boot / dts / allwinner / sun50i-h6.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 /*
3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4  */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/reset/sun50i-h6-ccu.h>
9
10 / {
11         interrupt-parent = <&gic>;
12         #address-cells = <1>;
13         #size-cells = <1>;
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu0: cpu@0 {
20                         compatible = "arm,cortex-a53", "arm,armv8";
21                         device_type = "cpu";
22                         reg = <0>;
23                         enable-method = "psci";
24                 };
25
26                 cpu1: cpu@1 {
27                         compatible = "arm,cortex-a53", "arm,armv8";
28                         device_type = "cpu";
29                         reg = <1>;
30                         enable-method = "psci";
31                 };
32
33                 cpu2: cpu@2 {
34                         compatible = "arm,cortex-a53", "arm,armv8";
35                         device_type = "cpu";
36                         reg = <2>;
37                         enable-method = "psci";
38                 };
39
40                 cpu3: cpu@3 {
41                         compatible = "arm,cortex-a53", "arm,armv8";
42                         device_type = "cpu";
43                         reg = <3>;
44                         enable-method = "psci";
45                 };
46         };
47
48         iosc: internal-osc-clk {
49                 #clock-cells = <0>;
50                 compatible = "fixed-clock";
51                 clock-frequency = <16000000>;
52                 clock-accuracy = <300000000>;
53                 clock-output-names = "iosc";
54         };
55
56         osc24M: osc24M_clk {
57                 #clock-cells = <0>;
58                 compatible = "fixed-clock";
59                 clock-frequency = <24000000>;
60                 clock-output-names = "osc24M";
61         };
62
63         osc32k: osc32k_clk {
64                 #clock-cells = <0>;
65                 compatible = "fixed-clock";
66                 clock-frequency = <32768>;
67                 clock-output-names = "osc32k";
68         };
69
70         psci {
71                 compatible = "arm,psci-0.2";
72                 method = "smc";
73         };
74
75         timer {
76                 compatible = "arm,armv8-timer";
77                 interrupts = <GIC_PPI 13
78                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
79                              <GIC_PPI 14
80                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
81                              <GIC_PPI 11
82                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
83                              <GIC_PPI 10
84                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
85         };
86
87         soc {
88                 compatible = "simple-bus";
89                 #address-cells = <1>;
90                 #size-cells = <1>;
91                 ranges;
92
93                 ccu: clock@3001000 {
94                         compatible = "allwinner,sun50i-h6-ccu";
95                         reg = <0x03001000 0x1000>;
96                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
97                         clock-names = "hosc", "losc", "iosc";
98                         #clock-cells = <1>;
99                         #reset-cells = <1>;
100                 };
101
102                 gic: interrupt-controller@3021000 {
103                         compatible = "arm,gic-400";
104                         reg = <0x03021000 0x1000>,
105                               <0x03022000 0x2000>,
106                               <0x03024000 0x2000>,
107                               <0x03026000 0x2000>;
108                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109                         interrupt-controller;
110                         #interrupt-cells = <3>;
111                 };
112
113                 pio: pinctrl@300b000 {
114                         compatible = "allwinner,sun50i-h6-pinctrl";
115                         reg = <0x0300b000 0x400>;
116                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
117                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
118                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
119                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
120                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
121                         clock-names = "apb", "hosc", "losc";
122                         gpio-controller;
123                         #gpio-cells = <3>;
124                         interrupt-controller;
125                         #interrupt-cells = <3>;
126
127                         uart0_ph_pins: uart0-ph {
128                                 pins = "PH0", "PH1";
129                                 function = "uart0";
130                         };
131                 };
132
133                 uart0: serial@5000000 {
134                         compatible = "snps,dw-apb-uart";
135                         reg = <0x05000000 0x400>;
136                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
137                         reg-shift = <2>;
138                         reg-io-width = <4>;
139                         clocks = <&ccu CLK_BUS_UART0>;
140                         resets = <&ccu RST_BUS_UART0>;
141                         status = "disabled";
142                 };
143
144                 uart1: serial@5000400 {
145                         compatible = "snps,dw-apb-uart";
146                         reg = <0x05000400 0x400>;
147                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
148                         reg-shift = <2>;
149                         reg-io-width = <4>;
150                         clocks = <&ccu CLK_BUS_UART1>;
151                         resets = <&ccu RST_BUS_UART1>;
152                         status = "disabled";
153                 };
154
155                 uart2: serial@5000800 {
156                         compatible = "snps,dw-apb-uart";
157                         reg = <0x05000800 0x400>;
158                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
159                         reg-shift = <2>;
160                         reg-io-width = <4>;
161                         clocks = <&ccu CLK_BUS_UART2>;
162                         resets = <&ccu RST_BUS_UART2>;
163                         status = "disabled";
164                 };
165
166                 uart3: serial@5000c00 {
167                         compatible = "snps,dw-apb-uart";
168                         reg = <0x05000c00 0x400>;
169                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
170                         reg-shift = <2>;
171                         reg-io-width = <4>;
172                         clocks = <&ccu CLK_BUS_UART3>;
173                         resets = <&ccu RST_BUS_UART3>;
174                         status = "disabled";
175                 };
176
177                 r_ccu: clock@7010000 {
178                         compatible = "allwinner,sun50i-h6-r-ccu";
179                         reg = <0x07010000 0x400>;
180                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
181                                  <&ccu CLK_PLL_PERIPH0>;
182                         clock-names = "hosc", "losc", "iosc", "pll-periph";
183                         #clock-cells = <1>;
184                         #reset-cells = <1>;
185                 };
186
187                 r_intc: interrupt-controller@7021000 {
188                         compatible = "allwinner,sun50i-h6-r-intc",
189                                      "allwinner,sun6i-a31-r-intc";
190                         interrupt-controller;
191                         #interrupt-cells = <2>;
192                         reg = <0x07021000 0x400>;
193                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
194                 };
195
196                 r_pio: pinctrl@7022000 {
197                         compatible = "allwinner,sun50i-h6-r-pinctrl";
198                         reg = <0x07022000 0x400>;
199                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
200                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
201                         clocks = <&r_ccu 2>, <&osc24M>, <&osc32k>;
202                         clock-names = "apb", "hosc", "losc";
203                         gpio-controller;
204                         #gpio-cells = <3>;
205                         interrupt-controller;
206                         #interrupt-cells = <3>;
207                 };
208         };
209 };