1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/axg-audio-clkc.h>
10 #include <dt-bindings/clock/axg-clkc.h>
11 #include <dt-bindings/clock/axg-aoclkc.h>
12 #include <dt-bindings/gpio/meson-axg-gpio.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
16 compatible = "amlogic,meson-axg";
18 interrupt-parent = <&gic>;
27 /* 16 MiB reserved for Hardware ROM Firmware */
28 hwrom_reserved: hwrom@0 {
29 reg = <0x0 0x0 0x0 0x1000000>;
33 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
34 secmon_reserved: secmon@5000000 {
35 reg = <0x0 0x05000000 0x0 0x300000>;
41 #address-cells = <0x2>;
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
49 next-level-cache = <&l2>;
54 compatible = "arm,cortex-a53", "arm,armv8";
56 enable-method = "psci";
57 next-level-cache = <&l2>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 enable-method = "psci";
65 next-level-cache = <&l2>;
70 compatible = "arm,cortex-a53", "arm,armv8";
72 enable-method = "psci";
73 next-level-cache = <&l2>;
82 compatible = "arm,cortex-a53-pmu";
83 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
91 compatible = "arm,psci-1.0";
96 compatible = "arm,armv8-timer";
97 interrupts = <GIC_PPI 13
98 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
102 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
104 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
108 compatible = "fixed-clock";
109 clock-frequency = <24000000>;
110 clock-output-names = "xtal";
114 ao_alt_xtal: ao_alt_xtal-clk {
115 compatible = "fixed-clock";
116 clock-frequency = <32000000>;
117 clock-output-names = "ao_alt_xtal";
122 compatible = "simple-bus";
123 #address-cells = <2>;
128 compatible = "simple-bus";
129 reg = <0x0 0xffe00000 0x0 0x200000>;
130 #address-cells = <2>;
132 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
135 compatible = "amlogic,meson-axg-mmc";
136 reg = <0x0 0x5000 0x0 0x800>;
137 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
139 clocks = <&clkc CLKID_SD_EMMC_B>,
140 <&clkc CLKID_SD_EMMC_B_CLK0>,
141 <&clkc CLKID_FCLK_DIV2>;
142 clock-names = "core", "clkin0", "clkin1";
143 resets = <&reset RESET_SD_EMMC_B>;
146 sd_emmc_c: mmc@7000 {
147 compatible = "amlogic,meson-axg-mmc";
148 reg = <0x0 0x7000 0x0 0x800>;
149 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
151 clocks = <&clkc CLKID_SD_EMMC_C>,
152 <&clkc CLKID_SD_EMMC_C_CLK0>,
153 <&clkc CLKID_FCLK_DIV2>;
154 clock-names = "core", "clkin0", "clkin1";
155 resets = <&reset RESET_SD_EMMC_C>;
159 audio: bus@ff642000 {
160 compatible = "simple-bus";
161 reg = <0x0 0xff642000 0x0 0x2000>;
162 #address-cells = <2>;
164 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
166 clkc_audio: clock-controller@0 {
167 compatible = "amlogic,axg-audio-clkc";
168 reg = <0x0 0x0 0x0 0xb4>;
171 clocks = <&clkc CLKID_AUDIO>,
176 <&clkc CLKID_HIFI_PLL>,
177 <&clkc CLKID_FCLK_DIV3>,
178 <&clkc CLKID_FCLK_DIV4>,
179 <&clkc CLKID_GP0_PLL>;
180 clock-names = "pclk",
190 resets = <&reset RESET_AUDIO>;
195 compatible = "simple-bus";
196 reg = <0x0 0xffd00000 0x0 0x25000>;
197 #address-cells = <2>;
199 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
201 gpio_intc: interrupt-controller@f080 {
202 compatible = "amlogic,meson-gpio-intc";
203 reg = <0x0 0xf080 0x0 0x10>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
211 compatible = "amlogic,meson-axg-ee-pwm";
212 reg = <0x0 0x1b000 0x0 0x20>;
218 compatible = "amlogic,meson-axg-ee-pwm";
219 reg = <0x0 0x1a000 0x0 0x20>;
224 reset: reset-controller@1004 {
225 compatible = "amlogic,meson-axg-reset";
226 reg = <0x0 0x01004 0x0 0x9c>;
231 compatible = "amlogic,meson-axg-spicc";
232 reg = <0x0 0x13000 0x0 0x3c>;
233 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clkc CLKID_SPICC0>;
235 clock-names = "core";
236 #address-cells = <1>;
242 compatible = "amlogic,meson-axg-spicc";
243 reg = <0x0 0x15000 0x0 0x3c>;
244 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clkc CLKID_SPICC1>;
246 clock-names = "core";
247 #address-cells = <1>;
253 compatible = "amlogic,meson-axg-i2c";
254 reg = <0x0 0x1f000 0x0 0x20>;
255 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
256 clocks = <&clkc CLKID_I2C>;
257 #address-cells = <1>;
263 compatible = "amlogic,meson-axg-i2c";
264 reg = <0x0 0x1e000 0x0 0x20>;
265 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
266 clocks = <&clkc CLKID_I2C>;
267 #address-cells = <1>;
273 compatible = "amlogic,meson-axg-i2c";
274 reg = <0x0 0x1d000 0x0 0x20>;
275 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
276 clocks = <&clkc CLKID_I2C>;
277 #address-cells = <1>;
283 compatible = "amlogic,meson-axg-i2c";
284 reg = <0x0 0x1c000 0x0 0x20>;
285 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
286 clocks = <&clkc CLKID_I2C>;
287 #address-cells = <1>;
292 uart_A: serial@24000 {
293 compatible = "amlogic,meson-gx-uart";
294 reg = <0x0 0x24000 0x0 0x18>;
295 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
297 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
298 clock-names = "xtal", "pclk", "baud";
301 uart_B: serial@23000 {
302 compatible = "amlogic,meson-gx-uart";
303 reg = <0x0 0x23000 0x0 0x18>;
304 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
306 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
307 clock-names = "xtal", "pclk", "baud";
311 ethmac: ethernet@ff3f0000 {
312 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
313 reg = <0x0 0xff3f0000 0x0 0x10000
314 0x0 0xff634540 0x0 0x8>;
315 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
316 interrupt-names = "macirq";
317 clocks = <&clkc CLKID_ETH>,
318 <&clkc CLKID_FCLK_DIV2>,
320 clock-names = "stmmaceth", "clkin0", "clkin1";
324 gic: interrupt-controller@ffc01000 {
325 compatible = "arm,gic-400";
326 reg = <0x0 0xffc01000 0 0x1000>,
327 <0x0 0xffc02000 0 0x2000>,
328 <0x0 0xffc04000 0 0x2000>,
329 <0x0 0xffc06000 0 0x2000>;
330 interrupt-controller;
331 interrupts = <GIC_PPI 9
332 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
333 #interrupt-cells = <3>;
334 #address-cells = <0>;
337 hiubus: bus@ff63c000 {
338 compatible = "simple-bus";
339 reg = <0x0 0xff63c000 0x0 0x1c00>;
340 #address-cells = <2>;
342 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
344 sysctrl: system-controller@0 {
345 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
348 clkc: clock-controller {
349 compatible = "amlogic,axg-clkc";
355 mailbox: mailbox@ff63dc00 {
356 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
357 reg = <0 0xff63dc00 0 0x400>;
358 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
359 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
360 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
364 periphs: periphs@ff634000 {
365 compatible = "simple-bus";
366 reg = <0x0 0xff634000 0x0 0x2000>;
367 #address-cells = <2>;
369 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
372 compatible = "amlogic,meson-rng";
373 reg = <0x0 0x18 0x0 0x4>;
374 clocks = <&clkc CLKID_RNG0>;
375 clock-names = "core";
378 pinctrl_periphs: pinctrl@480 {
379 compatible = "amlogic,meson-axg-periphs-pinctrl";
380 #address-cells = <2>;
385 reg = <0x0 0x00480 0x0 0x40>,
386 <0x0 0x004e8 0x0 0x14>,
387 <0x0 0x00520 0x0 0x14>,
388 <0x0 0x00430 0x0 0x3c>;
389 reg-names = "mux", "pull", "pull-enable", "gpio";
392 gpio-ranges = <&pinctrl_periphs 0 0 86>;
397 groups = "emmc_nand_d0",
412 emmc_clk_gate_pins: emmc_clk_gate {
415 function = "gpio_periphs";
435 sdio_clk_gate_pins: sdio_clk_gate {
438 function = "gpio_periphs";
446 eth_rmii_x_pins: eth-x-rmii {
448 groups = "eth_mdio_x",
450 "eth_rgmii_rx_clk_x",
461 eth_rmii_y_pins: eth-y-rmii {
463 groups = "eth_mdio_y",
465 "eth_rgmii_rx_clk_y",
476 eth_rgmii_x_pins: eth-x-rgmii {
478 groups = "eth_mdio_x",
480 "eth_rgmii_rx_clk_x",
496 eth_rgmii_y_pins: eth-y-rgmii {
498 groups = "eth_mdio_y",
500 "eth_rgmii_rx_clk_y",
516 pdm_dclk_a14_pins: pdm_dclk_a14 {
518 groups = "pdm_dclk_a14";
523 pdm_dclk_a19_pins: pdm_dclk_a19 {
525 groups = "pdm_dclk_a19";
530 pdm_din0_pins: pdm_din0 {
537 pdm_din1_pins: pdm_din1 {
544 pdm_din2_pins: pdm_din2 {
551 pdm_din3_pins: pdm_din3 {
558 pwm_a_a_pins: pwm_a_a {
565 pwm_a_x18_pins: pwm_a_x18 {
567 groups = "pwm_a_x18";
572 pwm_a_x20_pins: pwm_a_x20 {
574 groups = "pwm_a_x20";
579 pwm_a_z_pins: pwm_a_z {
586 pwm_b_a_pins: pwm_b_a {
593 pwm_b_x_pins: pwm_b_x {
600 pwm_b_z_pins: pwm_b_z {
607 pwm_c_a_pins: pwm_c_a {
614 pwm_c_x10_pins: pwm_c_x10 {
616 groups = "pwm_c_x10";
621 pwm_c_x17_pins: pwm_c_x17 {
623 groups = "pwm_c_x17";
628 pwm_d_x11_pins: pwm_d_x11 {
630 groups = "pwm_d_x11";
635 pwm_d_x16_pins: pwm_d_x16 {
637 groups = "pwm_d_x16";
642 spdif_in_z_pins: spdif_in_z {
644 groups = "spdif_in_z";
645 function = "spdif_in";
649 spdif_in_a1_pins: spdif_in_a1 {
651 groups = "spdif_in_a1";
652 function = "spdif_in";
656 spdif_in_a7_pins: spdif_in_a7 {
658 groups = "spdif_in_a7";
659 function = "spdif_in";
663 spdif_in_a19_pins: spdif_in_a19 {
665 groups = "spdif_in_a19";
666 function = "spdif_in";
670 spdif_in_a20_pins: spdif_in_a20 {
672 groups = "spdif_in_a20";
673 function = "spdif_in";
677 spdif_out_z_pins: spdif_out_z {
679 groups = "spdif_out_z";
680 function = "spdif_out";
684 spdif_out_a1_pins: spdif_out_a1 {
686 groups = "spdif_out_a1";
687 function = "spdif_out";
691 spdif_out_a11_pins: spdif_out_a11 {
693 groups = "spdif_out_a11";
694 function = "spdif_out";
698 spdif_out_a19_pins: spdif_out_a19 {
700 groups = "spdif_out_a19";
701 function = "spdif_out";
705 spdif_out_a20_pins: spdif_out_a20 {
707 groups = "spdif_out_a20";
708 function = "spdif_out";
714 groups = "spi0_miso",
721 spi0_ss0_pins: spi0_ss0 {
728 spi0_ss1_pins: spi0_ss1 {
735 spi0_ss2_pins: spi0_ss2 {
743 spi1_a_pins: spi1_a {
745 groups = "spi1_miso_a",
752 spi1_ss0_a_pins: spi1_ss0_a {
754 groups = "spi1_ss0_a";
759 spi1_ss1_pins: spi1_ss1 {
766 spi1_x_pins: spi1_x {
768 groups = "spi1_miso_x",
775 spi1_ss0_x_pins: spi1_ss0_x {
777 groups = "spi1_ss0_x";
790 i2c1_z_pins: i2c1_z {
792 groups = "i2c1_sck_z",
798 i2c1_x_pins: i2c1_x {
800 groups = "i2c1_sck_x",
806 i2c2_x_pins: i2c2_x {
808 groups = "i2c2_sck_x",
814 i2c2_a_pins: i2c2_a {
816 groups = "i2c2_sck_a",
822 i2c3_a6_pins: i2c3_a6 {
824 groups = "i2c3_sda_a6",
830 i2c3_a12_pins: i2c3_a12 {
832 groups = "i2c3_sda_a12",
838 i2c3_a19_pins: i2c3_a19 {
840 groups = "i2c3_sda_a19",
846 uart_a_pins: uart_a {
848 groups = "uart_tx_a",
854 uart_a_cts_rts_pins: uart_a_cts_rts {
856 groups = "uart_cts_a",
862 uart_b_x_pins: uart_b_x {
864 groups = "uart_tx_b_x",
870 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
872 groups = "uart_cts_b_x",
878 uart_b_z_pins: uart_b_z {
880 groups = "uart_tx_b_z",
886 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
888 groups = "uart_cts_b_z",
894 uart_ao_b_z_pins: uart_ao_b_z {
896 groups = "uart_ao_tx_b_z",
898 function = "uart_ao_b_z";
902 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
904 groups = "uart_ao_cts_b_z",
906 function = "uart_ao_b_z";
910 mclk_b_pins: mclk_b {
917 mclk_c_pins: mclk_c {
924 tdma_sclk_pins: tdma_sclk {
926 groups = "tdma_sclk";
931 tdma_sclk_slv_pins: tdma_sclk_slv {
933 groups = "tdma_sclk_slv";
938 tdma_fs_pins: tdma_fs {
945 tdma_fs_slv_pins: tdma_fs_slv {
947 groups = "tdma_fs_slv";
952 tdma_din0_pins: tdma_din0 {
954 groups = "tdma_din0";
959 tdma_dout0_x14_pins: tdma_dout0_x14 {
961 groups = "tdma_dout0_x14";
966 tdma_dout0_x15_pins: tdma_dout0_x15 {
968 groups = "tdma_dout0_x15";
973 tdma_dout1_pins: tdma_dout1 {
975 groups = "tdma_dout1";
980 tdma_din1_pins: tdma_din1 {
982 groups = "tdma_din1";
987 tdmb_sclk_pins: tdmb_sclk {
989 groups = "tdmb_sclk";
994 tdmb_sclk_slv_pins: tdmb_sclk_slv {
996 groups = "tdmb_sclk_slv";
1001 tdmb_fs_pins: tdmb_fs {
1008 tdmb_fs_slv_pins: tdmb_fs_slv {
1010 groups = "tdmb_fs_slv";
1015 tdmb_din0_pins: tdmb_din0 {
1017 groups = "tdmb_din0";
1022 tdmb_dout0_pins: tdmb_dout0 {
1024 groups = "tdmb_dout0";
1029 tdmb_din1_pins: tdmb_din1 {
1031 groups = "tdmb_din1";
1036 tdmb_dout1_pins: tdmb_dout1 {
1038 groups = "tdmb_dout1";
1043 tdmb_din2_pins: tdmb_din2 {
1045 groups = "tdmb_din2";
1050 tdmb_dout2_pins: tdmb_dout2 {
1052 groups = "tdmb_dout2";
1057 tdmb_din3_pins: tdmb_din3 {
1059 groups = "tdmb_din3";
1064 tdmb_dout3_pins: tdmb_dout3 {
1066 groups = "tdmb_dout3";
1071 tdmc_sclk_pins: tdmc_sclk {
1073 groups = "tdmc_sclk";
1078 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1080 groups = "tdmc_sclk_slv";
1085 tdmc_fs_pins: tdmc_fs {
1092 tdmc_fs_slv_pins: tdmc_fs_slv {
1094 groups = "tdmc_fs_slv";
1099 tdmc_din0_pins: tdmc_din0 {
1101 groups = "tdmc_din0";
1106 tdmc_dout0_pins: tdmc_dout0 {
1108 groups = "tdmc_dout0";
1113 tdmc_din1_pins: tdmc_din1 {
1115 groups = "tdmc_din1";
1120 tdmc_dout1_pins: tdmc_dout1 {
1122 groups = "tdmc_dout1";
1127 tdmc_din2_pins: tdmc_din2 {
1129 groups = "tdmc_din2";
1134 tdmc_dout2_pins: tdmc_dout2 {
1136 groups = "tdmc_dout2";
1141 tdmc_din3_pins: tdmc_din3 {
1143 groups = "tdmc_din3";
1148 tdmc_dout3_pins: tdmc_dout3 {
1150 groups = "tdmc_dout3";
1157 sram: sram@fffc0000 {
1158 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1159 reg = <0x0 0xfffc0000 0x0 0x20000>;
1160 #address-cells = <1>;
1162 ranges = <0 0x0 0xfffc0000 0x20000>;
1164 cpu_scp_lpri: scp-shmem@0 {
1165 compatible = "amlogic,meson-axg-scp-shmem";
1166 reg = <0x13000 0x400>;
1169 cpu_scp_hpri: scp-shmem@200 {
1170 compatible = "amlogic,meson-axg-scp-shmem";
1171 reg = <0x13400 0x400>;
1175 aobus: bus@ff800000 {
1176 compatible = "simple-bus";
1177 reg = <0x0 0xff800000 0x0 0x100000>;
1178 #address-cells = <2>;
1180 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1182 sysctrl_AO: sys-ctrl@0 {
1183 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1184 reg = <0x0 0x0 0x0 0x100>;
1186 clkc_AO: clock-controller {
1187 compatible = "amlogic,meson-axg-aoclkc";
1193 pinctrl_aobus: pinctrl@14 {
1194 compatible = "amlogic,meson-axg-aobus-pinctrl";
1195 #address-cells = <2>;
1200 reg = <0x0 0x00014 0x0 0x8>,
1201 <0x0 0x0002c 0x0 0x4>,
1202 <0x0 0x00024 0x0 0x8>;
1203 reg-names = "mux", "pull", "gpio";
1206 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1209 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1211 groups = "i2c_ao_sck_4";
1212 function = "i2c_ao";
1216 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1218 groups = "i2c_ao_sck_8";
1219 function = "i2c_ao";
1223 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1225 groups = "i2c_ao_sck_10";
1226 function = "i2c_ao";
1230 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1232 groups = "i2c_ao_sda_5";
1233 function = "i2c_ao";
1237 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1239 groups = "i2c_ao_sda_9";
1240 function = "i2c_ao";
1244 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1246 groups = "i2c_ao_sda_11";
1247 function = "i2c_ao";
1251 remote_input_ao_pins: remote_input_ao {
1253 groups = "remote_input_ao";
1254 function = "remote_input_ao";
1258 uart_ao_a_pins: uart_ao_a {
1260 groups = "uart_ao_tx_a",
1262 function = "uart_ao_a";
1266 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1268 groups = "uart_ao_cts_a",
1270 function = "uart_ao_a";
1274 uart_ao_b_pins: uart_ao_b {
1276 groups = "uart_ao_tx_b",
1278 function = "uart_ao_b";
1282 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1284 groups = "uart_ao_cts_b",
1286 function = "uart_ao_b";
1291 sec_AO: ao-secure@140 {
1292 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1293 reg = <0x0 0x140 0x0 0x140>;
1294 amlogic,has-chip-id;
1297 pwm_AO_ab: pwm@7000 {
1298 compatible = "amlogic,meson-axg-ao-pwm";
1299 reg = <0x0 0x07000 0x0 0x20>;
1301 status = "disabled";
1304 pwm_AO_cd: pwm@2000 {
1305 compatible = "amlogic,meson-axg-ao-pwm";
1306 reg = <0x0 0x02000 0x0 0x20>;
1308 status = "disabled";
1312 compatible = "amlogic,meson-axg-i2c";
1313 reg = <0x0 0x05000 0x0 0x20>;
1314 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1315 clocks = <&clkc CLKID_AO_I2C>;
1316 #address-cells = <1>;
1318 status = "disabled";
1321 uart_AO: serial@3000 {
1322 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1323 reg = <0x0 0x3000 0x0 0x18>;
1324 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1325 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1326 clock-names = "xtal", "pclk", "baud";
1327 status = "disabled";
1330 uart_AO_B: serial@4000 {
1331 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1332 reg = <0x0 0x4000 0x0 0x18>;
1333 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1334 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1335 clock-names = "xtal", "pclk", "baud";
1336 status = "disabled";
1340 compatible = "amlogic,meson-gxbb-ir";
1341 reg = <0x0 0x8000 0x0 0x20>;
1342 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1343 status = "disabled";
1347 compatible = "amlogic,meson-axg-saradc",
1348 "amlogic,meson-saradc";
1349 reg = <0x0 0x9000 0x0 0x38>;
1350 #io-channel-cells = <1>;
1351 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1353 <&clkc_AO CLKID_AO_SAR_ADC>,
1354 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1355 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1356 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1357 status = "disabled";