arch/arm64/boot/dts/amlogic/meson-axg.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/axg-audio-clkc.h>
  10 #include <dt-bindings/clock/axg-clkc.h>
  11 #include <dt-bindings/clock/axg-aoclkc.h>
  12 #include <dt-bindings/gpio/meson-axg-gpio.h>
  13 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  14
  15 / {
  16         compatible = "amlogic,meson-axg";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         reserved-memory {
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges;
  26
  27                 /* 16 MiB reserved for Hardware ROM Firmware */
  28                 hwrom_reserved: hwrom@0 {
  29                         reg = <0x0 0x0 0x0 0x1000000>;
  30                         no-map;
  31                 };
  32
  33                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  34                 secmon_reserved: secmon@5000000 {
  35                         reg = <0x0 0x05000000 0x0 0x300000>;
  36                         no-map;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <0x2>;
  42                 #size-cells = <0x0>;
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         reg = <0x0 0x0>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&l2>;
  50                 };
  51
  52                 cpu1: cpu@1 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x1>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&l2>;
  58                 };
  59
  60                 cpu2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53", "arm,armv8";
  63                         reg = <0x0 0x2>;
  64                         enable-method = "psci";
  65                         next-level-cache = <&l2>;
  66                 };
  67
  68                 cpu3: cpu@3 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53", "arm,armv8";
  71                         reg = <0x0 0x3>;
  72                         enable-method = "psci";
  73                         next-level-cache = <&l2>;
  74                 };
  75
  76                 l2: l2-cache0 {
  77                         compatible = "cache";
  78                 };
  79         };
  80
  81         arm-pmu {
  82                 compatible = "arm,cortex-a53-pmu";
  83                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  87                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  88         };
  89
  90         psci {
  91                 compatible = "arm,psci-1.0";
  92                 method = "smc";
  93         };
  94
  95         timer {
  96                 compatible = "arm,armv8-timer";
  97                 interrupts = <GIC_PPI 13
  98                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 14
 100                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 101                              <GIC_PPI 11
 102                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 103                              <GIC_PPI 10
 104                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 105         };
 106
 107         xtal: xtal-clk {
 108                 compatible = "fixed-clock";
 109                 clock-frequency = <24000000>;
 110                 clock-output-names = "xtal";
 111                 #clock-cells = <0>;
 112         };
 113
 114         ao_alt_xtal: ao_alt_xtal-clk {
 115                 compatible = "fixed-clock";
 116                 clock-frequency = <32000000>;
 117                 clock-output-names = "ao_alt_xtal";
 118                 #clock-cells = <0>;
 119         };
 120
 121         soc {
 122                 compatible = "simple-bus";
 123                 #address-cells = <2>;
 124                 #size-cells = <2>;
 125                 ranges;
 126
 127                 apb: apb@ffe00000 {
 128                         compatible = "simple-bus";
 129                         reg = <0x0 0xffe00000 0x0 0x200000>;
 130                         #address-cells = <2>;
 131                         #size-cells = <2>;
 132                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
 133
 134                         sd_emmc_b: sd@5000 {
 135                                 compatible = "amlogic,meson-axg-mmc";
 136                                 reg = <0x0 0x5000 0x0 0x800>;
 137                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
 138                                 status = "disabled";
 139                                 clocks = <&clkc CLKID_SD_EMMC_B>,
 140                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
 141                                         <&clkc CLKID_FCLK_DIV2>;
 142                                 clock-names = "core", "clkin0", "clkin1";
 143                                 resets = <&reset RESET_SD_EMMC_B>;
 144                         };
 145
 146                         sd_emmc_c: mmc@7000 {
 147                                 compatible = "amlogic,meson-axg-mmc";
 148                                 reg = <0x0 0x7000 0x0 0x800>;
 149                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
 150                                 status = "disabled";
 151                                 clocks = <&clkc CLKID_SD_EMMC_C>,
 152                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
 153                                         <&clkc CLKID_FCLK_DIV2>;
 154                                 clock-names = "core", "clkin0", "clkin1";
 155                                 resets = <&reset RESET_SD_EMMC_C>;
 156                         };
 157                 };
 158
 159                 audio: bus@ff642000 {
 160                         compatible = "simple-bus";
 161                         reg = <0x0 0xff642000 0x0 0x2000>;
 162                         #address-cells = <2>;
 163                         #size-cells = <2>;
 164                         ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
 165
 166                         clkc_audio: clock-controller@0 {
 167                                 compatible = "amlogic,axg-audio-clkc";
 168                                 reg = <0x0 0x0 0x0 0xb4>;
 169                                 #clock-cells = <1>;
 170
 171                                 clocks = <&clkc CLKID_AUDIO>,
 172                                          <&clkc CLKID_MPLL0>,
 173                                          <&clkc CLKID_MPLL1>,
 174                                          <&clkc CLKID_MPLL2>,
 175                                          <&clkc CLKID_MPLL3>,
 176                                          <&clkc CLKID_HIFI_PLL>,
 177                                          <&clkc CLKID_FCLK_DIV3>,
 178                                          <&clkc CLKID_FCLK_DIV4>,
 179                                          <&clkc CLKID_GP0_PLL>;
 180                                 clock-names = "pclk",
 181                                               "mst_in0",
 182                                               "mst_in1",
 183                                               "mst_in2",
 184                                               "mst_in3",
 185                                               "mst_in4",
 186                                               "mst_in5",
 187                                               "mst_in6",
 188                                               "mst_in7";
 189
 190                                 resets = <&reset RESET_AUDIO>;
 191                         };
 192                 };
 193
 194                 cbus: bus@ffd00000 {
 195                         compatible = "simple-bus";
 196                         reg = <0x0 0xffd00000 0x0 0x25000>;
 197                         #address-cells = <2>;
 198                         #size-cells = <2>;
 199                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 200
 201                         gpio_intc: interrupt-controller@f080 {
 202                                 compatible = "amlogic,meson-gpio-intc";
 203                                 reg = <0x0 0xf080 0x0 0x10>;
 204                                 interrupt-controller;
 205                                 #interrupt-cells = <2>;
 206                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
 207                                 status = "disabled";
 208                         };
 209
 210                         pwm_ab: pwm@1b000 {
 211                                 compatible = "amlogic,meson-axg-ee-pwm";
 212                                 reg = <0x0 0x1b000 0x0 0x20>;
 213                                 #pwm-cells = <3>;
 214                                 status = "disabled";
 215                         };
 216
 217                         pwm_cd: pwm@1a000 {
 218                                 compatible = "amlogic,meson-axg-ee-pwm";
 219                                 reg = <0x0 0x1a000 0x0 0x20>;
 220                                 #pwm-cells = <3>;
 221                                 status = "disabled";
 222                         };
 223
 224                         reset: reset-controller@1004 {
 225                                 compatible = "amlogic,meson-axg-reset";
 226                                 reg = <0x0 0x01004 0x0 0x9c>;
 227                                 #reset-cells = <1>;
 228                         };
 229
 230                         spicc0: spi@13000 {
 231                                 compatible = "amlogic,meson-axg-spicc";
 232                                 reg = <0x0 0x13000 0x0 0x3c>;
 233                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 234                                 clocks = <&clkc CLKID_SPICC0>;
 235                                 clock-names = "core";
 236                                 #address-cells = <1>;
 237                                 #size-cells = <0>;
 238                                 status = "disabled";
 239                         };
 240
 241                         spicc1: spi@15000 {
 242                                 compatible = "amlogic,meson-axg-spicc";
 243                                 reg = <0x0 0x15000 0x0 0x3c>;
 244                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 245                                 clocks = <&clkc CLKID_SPICC1>;
 246                                 clock-names = "core";
 247                                 #address-cells = <1>;
 248                                 #size-cells = <0>;
 249                                 status = "disabled";
 250                         };
 251
 252                         i2c0: i2c@1f000 {
 253                                 compatible = "amlogic,meson-axg-i2c";
 254                                 reg = <0x0 0x1f000 0x0 0x20>;
 255                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
 256                                 clocks = <&clkc CLKID_I2C>;
 257                                 #address-cells = <1>;
 258                                 #size-cells = <0>;
 259                                 status = "disabled";
 260                         };
 261
 262                         i2c1: i2c@1e000 {
 263                                 compatible = "amlogic,meson-axg-i2c";
 264                                 reg = <0x0 0x1e000 0x0 0x20>;
 265                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
 266                                 clocks = <&clkc CLKID_I2C>;
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269                                 status = "disabled";
 270                         };
 271
 272                         i2c2: i2c@1d000 {
 273                                 compatible = "amlogic,meson-axg-i2c";
 274                                 reg = <0x0 0x1d000 0x0 0x20>;
 275                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
 276                                 clocks = <&clkc CLKID_I2C>;
 277                                 #address-cells = <1>;
 278                                 #size-cells = <0>;
 279                                 status = "disabled";
 280                         };
 281
 282                         i2c3: i2c@1c000 {
 283                                 compatible = "amlogic,meson-axg-i2c";
 284                                 reg = <0x0 0x1c000 0x0 0x20>;
 285                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
 286                                 clocks = <&clkc CLKID_I2C>;
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289                                 status = "disabled";
 290                         };
 291
 292                         uart_A: serial@24000 {
 293                                 compatible = "amlogic,meson-gx-uart";
 294                                 reg = <0x0 0x24000 0x0 0x18>;
 295                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 296                                 status = "disabled";
 297                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 298                                 clock-names = "xtal", "pclk", "baud";
 299                         };
 300
 301                         uart_B: serial@23000 {
 302                                 compatible = "amlogic,meson-gx-uart";
 303                                 reg = <0x0 0x23000 0x0 0x18>;
 304                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 305                                 status = "disabled";
 306                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 307                                 clock-names = "xtal", "pclk", "baud";
 308                         };
 309                 };
 310
 311                 ethmac: ethernet@ff3f0000 {
 312                         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 313                         reg = <0x0 0xff3f0000 0x0 0x10000
 314                                 0x0 0xff634540 0x0 0x8>;
 315                         interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 316                         interrupt-names = "macirq";
 317                         clocks = <&clkc CLKID_ETH>,
 318                                  <&clkc CLKID_FCLK_DIV2>,
 319                                  <&clkc CLKID_MPLL2>;
 320                         clock-names = "stmmaceth", "clkin0", "clkin1";
 321                         status = "disabled";
 322                 };
 323
 324                 gic: interrupt-controller@ffc01000 {
 325                         compatible = "arm,gic-400";
 326                         reg = <0x0 0xffc01000 0 0x1000>,
 327                               <0x0 0xffc02000 0 0x2000>,
 328                               <0x0 0xffc04000 0 0x2000>,
 329                               <0x0 0xffc06000 0 0x2000>;
 330                         interrupt-controller;
 331                         interrupts = <GIC_PPI 9
 332                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 333                         #interrupt-cells = <3>;
 334                         #address-cells = <0>;
 335                 };
 336
 337                 hiubus: bus@ff63c000 {
 338                         compatible = "simple-bus";
 339                         reg = <0x0 0xff63c000 0x0 0x1c00>;
 340                         #address-cells = <2>;
 341                         #size-cells = <2>;
 342                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
 343
 344                         sysctrl: system-controller@0 {
 345                                 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
 346                                 reg = <0 0 0 0x400>;
 347
 348                                 clkc: clock-controller {
 349                                         compatible = "amlogic,axg-clkc";
 350                                         #clock-cells = <1>;
 351                                 };
 352                         };
 353                 };
 354
 355                 mailbox: mailbox@ff63dc00 {
 356                         compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 357                         reg = <0 0xff63dc00 0 0x400>;
 358                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
 359                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
 360                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
 361                         #mbox-cells = <1>;
 362                 };
 363
 364                 periphs: periphs@ff634000 {
 365                         compatible = "simple-bus";
 366                         reg = <0x0 0xff634000 0x0 0x2000>;
 367                         #address-cells = <2>;
 368                         #size-cells = <2>;
 369                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 370
 371                         hwrng: rng {
 372                                 compatible = "amlogic,meson-rng";
 373                                 reg = <0x0 0x18 0x0 0x4>;
 374                                 clocks = <&clkc CLKID_RNG0>;
 375                                 clock-names = "core";
 376                         };
 377
 378                         pinctrl_periphs: pinctrl@480 {
 379                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
 380                                 #address-cells = <2>;
 381                                 #size-cells = <2>;
 382                                 ranges;
 383
 384                                 gpio: bank@480 {
 385                                         reg = <0x0 0x00480 0x0 0x40>,
 386                                                 <0x0 0x004e8 0x0 0x14>,
 387                                                 <0x0 0x00520 0x0 0x14>,
 388                                                 <0x0 0x00430 0x0 0x3c>;
 389                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 390                                         gpio-controller;
 391                                         #gpio-cells = <2>;
 392                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
 393                                 };
 394
 395                                 emmc_pins: emmc {
 396                                         mux {
 397                                                 groups = "emmc_nand_d0",
 398                                                         "emmc_nand_d1",
 399                                                         "emmc_nand_d2",
 400                                                         "emmc_nand_d3",
 401                                                         "emmc_nand_d4",
 402                                                         "emmc_nand_d5",
 403                                                         "emmc_nand_d6",
 404                                                         "emmc_nand_d7",
 405                                                         "emmc_clk",
 406                                                         "emmc_cmd",
 407                                                         "emmc_ds";
 408                                                 function = "emmc";
 409                                         };
 410                                 };
 411
 412                                 emmc_clk_gate_pins: emmc_clk_gate {
 413                                         mux {
 414                                                 groups = "BOOT_8";
 415                                                 function = "gpio_periphs";
 416                                         };
 417                                         cfg-pull-down {
 418                                                 pins = "BOOT_8";
 419                                                 bias-pull-down;
 420                                         };
 421                                 };
 422
 423                                 sdio_pins: sdio {
 424                                         mux {
 425                                                 groups = "sdio_d0",
 426                                                         "sdio_d1",
 427                                                         "sdio_d2",
 428                                                         "sdio_d3",
 429                                                         "sdio_cmd",
 430                                                         "sdio_clk";
 431                                                 function = "sdio";
 432                                         };
 433                                 };
 434
 435                                 sdio_clk_gate_pins: sdio_clk_gate {
 436                                         mux {
 437                                                 groups = "GPIOX_4";
 438                                                 function = "gpio_periphs";
 439                                         };
 440                                         cfg-pull-down {
 441                                                 pins = "GPIOX_4";
 442                                                 bias-pull-down;
 443                                         };
 444                                 };
 445
 446                                 eth_rmii_x_pins: eth-x-rmii {
 447                                         mux {
 448                                                 groups = "eth_mdio_x",
 449                                                        "eth_mdc_x",
 450                                                        "eth_rgmii_rx_clk_x",
 451                                                        "eth_rx_dv_x",
 452                                                        "eth_rxd0_x",
 453                                                        "eth_rxd1_x",
 454                                                        "eth_txen_x",
 455                                                        "eth_txd0_x",
 456                                                        "eth_txd1_x";
 457                                                 function = "eth";
 458                                         };
 459                                 };
 460
 461                                 eth_rmii_y_pins: eth-y-rmii {
 462                                         mux {
 463                                                 groups = "eth_mdio_y",
 464                                                        "eth_mdc_y",
 465                                                        "eth_rgmii_rx_clk_y",
 466                                                        "eth_rx_dv_y",
 467                                                        "eth_rxd0_y",
 468                                                        "eth_rxd1_y",
 469                                                        "eth_txen_y",
 470                                                        "eth_txd0_y",
 471                                                        "eth_txd1_y";
 472                                                 function = "eth";
 473                                         };
 474                                 };
 475
 476                                 eth_rgmii_x_pins: eth-x-rgmii {
 477                                         mux {
 478                                                 groups = "eth_mdio_x",
 479                                                        "eth_mdc_x",
 480                                                        "eth_rgmii_rx_clk_x",
 481                                                        "eth_rx_dv_x",
 482                                                        "eth_rxd0_x",
 483                                                        "eth_rxd1_x",
 484                                                        "eth_rxd2_rgmii",
 485                                                        "eth_rxd3_rgmii",
 486                                                        "eth_rgmii_tx_clk",
 487                                                        "eth_txen_x",
 488                                                        "eth_txd0_x",
 489                                                        "eth_txd1_x",
 490                                                        "eth_txd2_rgmii",
 491                                                        "eth_txd3_rgmii";
 492                                                 function = "eth";
 493                                         };
 494                                 };
 495
 496                                 eth_rgmii_y_pins: eth-y-rgmii {
 497                                         mux {
 498                                                 groups = "eth_mdio_y",
 499                                                        "eth_mdc_y",
 500                                                        "eth_rgmii_rx_clk_y",
 501                                                        "eth_rx_dv_y",
 502                                                        "eth_rxd0_y",
 503                                                        "eth_rxd1_y",
 504                                                        "eth_rxd2_rgmii",
 505                                                        "eth_rxd3_rgmii",
 506                                                        "eth_rgmii_tx_clk",
 507                                                        "eth_txen_y",
 508                                                        "eth_txd0_y",
 509                                                        "eth_txd1_y",
 510                                                        "eth_txd2_rgmii",
 511                                                        "eth_txd3_rgmii";
 512                                                 function = "eth";
 513                                         };
 514                                 };
 515
 516                                 pdm_dclk_a14_pins: pdm_dclk_a14 {
 517                                         mux {
 518                                                 groups = "pdm_dclk_a14";
 519                                                 function = "pdm";
 520                                         };
 521                                 };
 522
 523                                 pdm_dclk_a19_pins: pdm_dclk_a19 {
 524                                         mux {
 525                                                 groups = "pdm_dclk_a19";
 526                                                 function = "pdm";
 527                                         };
 528                                 };
 529
 530                                 pdm_din0_pins: pdm_din0 {
 531                                         mux {
 532                                                 groups = "pdm_din0";
 533                                                 function = "pdm";
 534                                         };
 535                                 };
 536
 537                                 pdm_din1_pins: pdm_din1 {
 538                                         mux {
 539                                                 groups = "pdm_din1";
 540                                                 function = "pdm";
 541                                         };
 542                                 };
 543
 544                                 pdm_din2_pins: pdm_din2 {
 545                                         mux {
 546                                                 groups = "pdm_din2";
 547                                                 function = "pdm";
 548                                         };
 549                                 };
 550
 551                                 pdm_din3_pins: pdm_din3 {
 552                                         mux {
 553                                                 groups = "pdm_din3";
 554                                                 function = "pdm";
 555                                         };
 556                                 };
 557
 558                                 pwm_a_a_pins: pwm_a_a {
 559                                         mux {
 560                                                 groups = "pwm_a_a";
 561                                                 function = "pwm_a";
 562                                         };
 563                                 };
 564
 565                                 pwm_a_x18_pins: pwm_a_x18 {
 566                                         mux {
 567                                                 groups = "pwm_a_x18";
 568                                                 function = "pwm_a";
 569                                         };
 570                                 };
 571
 572                                 pwm_a_x20_pins: pwm_a_x20 {
 573                                         mux {
 574                                                 groups = "pwm_a_x20";
 575                                                 function = "pwm_a";
 576                                         };
 577                                 };
 578
 579                                 pwm_a_z_pins: pwm_a_z {
 580                                         mux {
 581                                                 groups = "pwm_a_z";
 582                                                 function = "pwm_a";
 583                                         };
 584                                 };
 585
 586                                 pwm_b_a_pins: pwm_b_a {
 587                                         mux {
 588                                                 groups = "pwm_b_a";
 589                                                 function = "pwm_b";
 590                                         };
 591                                 };
 592
 593                                 pwm_b_x_pins: pwm_b_x {
 594                                         mux {
 595                                                 groups = "pwm_b_x";
 596                                                 function = "pwm_b";
 597                                         };
 598                                 };
 599
 600                                 pwm_b_z_pins: pwm_b_z {
 601                                         mux {
 602                                                 groups = "pwm_b_z";
 603                                                 function = "pwm_b";
 604                                         };
 605                                 };
 606
 607                                 pwm_c_a_pins: pwm_c_a {
 608                                         mux {
 609                                                 groups = "pwm_c_a";
 610                                                 function = "pwm_c";
 611                                         };
 612                                 };
 613
 614                                 pwm_c_x10_pins: pwm_c_x10 {
 615                                         mux {
 616                                                 groups = "pwm_c_x10";
 617                                                 function = "pwm_c";
 618                                         };
 619                                 };
 620
 621                                 pwm_c_x17_pins: pwm_c_x17 {
 622                                         mux {
 623                                                 groups = "pwm_c_x17";
 624                                                 function = "pwm_c";
 625                                         };
 626                                 };
 627
 628                                 pwm_d_x11_pins: pwm_d_x11 {
 629                                         mux {
 630                                                 groups = "pwm_d_x11";
 631                                                 function = "pwm_d";
 632                                         };
 633                                 };
 634
 635                                 pwm_d_x16_pins: pwm_d_x16 {
 636                                         mux {
 637                                                 groups = "pwm_d_x16";
 638                                                 function = "pwm_d";
 639                                         };
 640                                 };
 641
 642                                 spdif_in_z_pins: spdif_in_z {
 643                                         mux {
 644                                                 groups = "spdif_in_z";
 645                                                 function = "spdif_in";
 646                                         };
 647                                 };
 648
 649                                 spdif_in_a1_pins: spdif_in_a1 {
 650                                         mux {
 651                                                 groups = "spdif_in_a1";
 652                                                 function = "spdif_in";
 653                                         };
 654                                 };
 655
 656                                 spdif_in_a7_pins: spdif_in_a7 {
 657                                         mux {
 658                                                 groups = "spdif_in_a7";
 659                                                 function = "spdif_in";
 660                                         };
 661                                 };
 662
 663                                 spdif_in_a19_pins: spdif_in_a19 {
 664                                         mux {
 665                                                 groups = "spdif_in_a19";
 666                                                 function = "spdif_in";
 667                                         };
 668                                 };
 669
 670                                 spdif_in_a20_pins: spdif_in_a20 {
 671                                         mux {
 672                                                 groups = "spdif_in_a20";
 673                                                 function = "spdif_in";
 674                                         };
 675                                 };
 676
 677                                 spdif_out_z_pins: spdif_out_z {
 678                                         mux {
 679                                                 groups = "spdif_out_z";
 680                                                 function = "spdif_out";
 681                                         };
 682                                 };
 683
 684                                 spdif_out_a1_pins: spdif_out_a1 {
 685                                         mux {
 686                                                 groups = "spdif_out_a1";
 687                                                 function = "spdif_out";
 688                                         };
 689                                 };
 690
 691                                 spdif_out_a11_pins: spdif_out_a11 {
 692                                         mux {
 693                                                 groups = "spdif_out_a11";
 694                                                 function = "spdif_out";
 695                                         };
 696                                 };
 697
 698                                 spdif_out_a19_pins: spdif_out_a19 {
 699                                         mux {
 700                                                 groups = "spdif_out_a19";
 701                                                 function = "spdif_out";
 702                                         };
 703                                 };
 704
 705                                 spdif_out_a20_pins: spdif_out_a20 {
 706                                         mux {
 707                                                 groups = "spdif_out_a20";
 708                                                 function = "spdif_out";
 709                                         };
 710                                 };
 711
 712                                 spi0_pins: spi0 {
 713                                         mux {
 714                                                 groups = "spi0_miso",
 715                                                         "spi0_mosi",
 716                                                         "spi0_clk";
 717                                                 function = "spi0";
 718                                         };
 719                                 };
 720
 721                                 spi0_ss0_pins: spi0_ss0 {
 722                                         mux {
 723                                                 groups = "spi0_ss0";
 724                                                 function = "spi0";
 725                                         };
 726                                 };
 727
 728                                 spi0_ss1_pins: spi0_ss1 {
 729                                         mux {
 730                                                 groups = "spi0_ss1";
 731                                                 function = "spi0";
 732                                         };
 733                                 };
 734
 735                                 spi0_ss2_pins: spi0_ss2 {
 736                                         mux {
 737                                                 groups = "spi0_ss2";
 738                                                 function = "spi0";
 739                                         };
 740                                 };
 741
 742
 743                                 spi1_a_pins: spi1_a {
 744                                         mux {
 745                                                 groups = "spi1_miso_a",
 746                                                         "spi1_mosi_a",
 747                                                         "spi1_clk_a";
 748                                                 function = "spi1";
 749                                         };
 750                                 };
 751
 752                                 spi1_ss0_a_pins: spi1_ss0_a {
 753                                         mux {
 754                                                 groups = "spi1_ss0_a";
 755                                                 function = "spi1";
 756                                         };
 757                                 };
 758
 759                                 spi1_ss1_pins: spi1_ss1 {
 760                                         mux {
 761                                                 groups = "spi1_ss1";
 762                                                 function = "spi1";
 763                                         };
 764                                 };
 765
 766                                 spi1_x_pins: spi1_x {
 767                                         mux {
 768                                                 groups = "spi1_miso_x",
 769                                                         "spi1_mosi_x",
 770                                                         "spi1_clk_x";
 771                                                 function = "spi1";
 772                                         };
 773                                 };
 774
 775                                 spi1_ss0_x_pins: spi1_ss0_x {
 776                                         mux {
 777                                                 groups = "spi1_ss0_x";
 778                                                 function = "spi1";
 779                                         };
 780                                 };
 781
 782                                 i2c0_pins: i2c0 {
 783                                         mux {
 784                                                 groups = "i2c0_sck",
 785                                                         "i2c0_sda";
 786                                                 function = "i2c0";
 787                                         };
 788                                 };
 789
 790                                 i2c1_z_pins: i2c1_z {
 791                                         mux {
 792                                                 groups = "i2c1_sck_z",
 793                                                         "i2c1_sda_z";
 794                                                 function = "i2c1";
 795                                         };
 796                                 };
 797
 798                                 i2c1_x_pins: i2c1_x {
 799                                         mux {
 800                                                 groups = "i2c1_sck_x",
 801                                                         "i2c1_sda_x";
 802                                                 function = "i2c1";
 803                                         };
 804                                 };
 805
 806                                 i2c2_x_pins: i2c2_x {
 807                                         mux {
 808                                                 groups = "i2c2_sck_x",
 809                                                         "i2c2_sda_x";
 810                                                 function = "i2c2";
 811                                         };
 812                                 };
 813
 814                                 i2c2_a_pins: i2c2_a {
 815                                         mux {
 816                                                 groups = "i2c2_sck_a",
 817                                                         "i2c2_sda_a";
 818                                                 function = "i2c2";
 819                                         };
 820                                 };
 821
 822                                 i2c3_a6_pins: i2c3_a6 {
 823                                         mux {
 824                                                 groups = "i2c3_sda_a6",
 825                                                         "i2c3_sck_a7";
 826                                                 function = "i2c3";
 827                                         };
 828                                 };
 829
 830                                 i2c3_a12_pins: i2c3_a12 {
 831                                         mux {
 832                                                 groups = "i2c3_sda_a12",
 833                                                         "i2c3_sck_a13";
 834                                                 function = "i2c3";
 835                                         };
 836                                 };
 837
 838                                 i2c3_a19_pins: i2c3_a19 {
 839                                         mux {
 840                                                 groups = "i2c3_sda_a19",
 841                                                         "i2c3_sck_a20";
 842                                                 function = "i2c3";
 843                                         };
 844                                 };
 845
 846                                 uart_a_pins: uart_a {
 847                                         mux {
 848                                                 groups = "uart_tx_a",
 849                                                         "uart_rx_a";
 850                                                 function = "uart_a";
 851                                         };
 852                                 };
 853
 854                                 uart_a_cts_rts_pins: uart_a_cts_rts {
 855                                         mux {
 856                                                 groups = "uart_cts_a",
 857                                                         "uart_rts_a";
 858                                                 function = "uart_a";
 859                                         };
 860                                 };
 861
 862                                 uart_b_x_pins: uart_b_x {
 863                                         mux {
 864                                                 groups = "uart_tx_b_x",
 865                                                         "uart_rx_b_x";
 866                                                 function = "uart_b";
 867                                         };
 868                                 };
 869
 870                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
 871                                         mux {
 872                                                 groups = "uart_cts_b_x",
 873                                                         "uart_rts_b_x";
 874                                                 function = "uart_b";
 875                                         };
 876                                 };
 877
 878                                 uart_b_z_pins: uart_b_z {
 879                                         mux {
 880                                                 groups = "uart_tx_b_z",
 881                                                         "uart_rx_b_z";
 882                                                 function = "uart_b";
 883                                         };
 884                                 };
 885
 886                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
 887                                         mux {
 888                                                 groups = "uart_cts_b_z",
 889                                                         "uart_rts_b_z";
 890                                                 function = "uart_b";
 891                                         };
 892                                 };
 893
 894                                 uart_ao_b_z_pins: uart_ao_b_z {
 895                                         mux {
 896                                                 groups = "uart_ao_tx_b_z",
 897                                                         "uart_ao_rx_b_z";
 898                                                 function = "uart_ao_b_z";
 899                                         };
 900                                 };
 901
 902                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
 903                                         mux {
 904                                                 groups = "uart_ao_cts_b_z",
 905                                                         "uart_ao_rts_b_z";
 906                                                 function = "uart_ao_b_z";
 907                                         };
 908                                 };
 909
 910                                 mclk_b_pins: mclk_b {
 911                                         mux {
 912                                                 groups = "mclk_b";
 913                                                 function = "mclk_b";
 914                                         };
 915                                 };
 916
 917                                 mclk_c_pins: mclk_c {
 918                                         mux {
 919                                                 groups = "mclk_c";
 920                                                 function = "mclk_c";
 921                                         };
 922                                 };
 923
 924                                 tdma_sclk_pins: tdma_sclk {
 925                                         mux {
 926                                                 groups = "tdma_sclk";
 927                                                 function = "tdma";
 928                                         };
 929                                 };
 930
 931                                 tdma_sclk_slv_pins: tdma_sclk_slv {
 932                                         mux {
 933                                                 groups = "tdma_sclk_slv";
 934                                                 function = "tdma";
 935                                         };
 936                                 };
 937
 938                                 tdma_fs_pins: tdma_fs {
 939                                         mux {
 940                                                 groups = "tdma_fs";
 941                                                 function = "tdma";
 942                                         };
 943                                 };
 944
 945                                 tdma_fs_slv_pins: tdma_fs_slv {
 946                                         mux {
 947                                                 groups = "tdma_fs_slv";
 948                                                 function = "tdma";
 949                                         };
 950                                 };
 951
 952                                 tdma_din0_pins: tdma_din0 {
 953                                         mux {
 954                                                 groups = "tdma_din0";
 955                                                 function = "tdma";
 956                                         };
 957                                 };
 958
 959                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
 960                                         mux {
 961                                                 groups = "tdma_dout0_x14";
 962                                                 function = "tdma";
 963                                         };
 964                                 };
 965
 966                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
 967                                         mux {
 968                                                 groups = "tdma_dout0_x15";
 969                                                 function = "tdma";
 970                                         };
 971                                 };
 972
 973                                 tdma_dout1_pins: tdma_dout1 {
 974                                         mux {
 975                                                 groups = "tdma_dout1";
 976                                                 function = "tdma";
 977                                         };
 978                                 };
 979
 980                                 tdma_din1_pins: tdma_din1 {
 981                                         mux {
 982                                                 groups = "tdma_din1";
 983                                                 function = "tdma";
 984                                         };
 985                                 };
 986
 987                                 tdmb_sclk_pins: tdmb_sclk {
 988                                         mux {
 989                                                 groups = "tdmb_sclk";
 990                                                 function = "tdmb";
 991                                         };
 992                                 };
 993
 994                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
 995                                         mux {
 996                                                 groups = "tdmb_sclk_slv";
 997                                                 function = "tdmb";
 998                                         };
 999                                 };
1000
1001                                 tdmb_fs_pins: tdmb_fs {
1002                                         mux {
1003                                                 groups = "tdmb_fs";
1004                                                 function = "tdmb";
1005                                         };
1006                                 };
1007
1008                                 tdmb_fs_slv_pins: tdmb_fs_slv {
1009                                         mux {
1010                                                 groups = "tdmb_fs_slv";
1011                                                 function = "tdmb";
1012                                         };
1013                                 };
1014
1015                                 tdmb_din0_pins: tdmb_din0 {
1016                                         mux {
1017                                                 groups = "tdmb_din0";
1018                                                 function = "tdmb";
1019                                         };
1020                                 };
1021
1022                                 tdmb_dout0_pins: tdmb_dout0 {
1023                                         mux {
1024                                                 groups = "tdmb_dout0";
1025                                                 function = "tdmb";
1026                                         };
1027                                 };
1028
1029                                 tdmb_din1_pins: tdmb_din1 {
1030                                         mux {
1031                                                 groups = "tdmb_din1";
1032                                                 function = "tdmb";
1033                                         };
1034                                 };
1035
1036                                 tdmb_dout1_pins: tdmb_dout1 {
1037                                         mux {
1038                                                 groups = "tdmb_dout1";
1039                                                 function = "tdmb";
1040                                         };
1041                                 };
1042
1043                                 tdmb_din2_pins: tdmb_din2 {
1044                                         mux {
1045                                                 groups = "tdmb_din2";
1046                                                 function = "tdmb";
1047                                         };
1048                                 };
1049
1050                                 tdmb_dout2_pins: tdmb_dout2 {
1051                                         mux {
1052                                                 groups = "tdmb_dout2";
1053                                                 function = "tdmb";
1054                                         };
1055                                 };
1056
1057                                 tdmb_din3_pins: tdmb_din3 {
1058                                         mux {
1059                                                 groups = "tdmb_din3";
1060                                                 function = "tdmb";
1061                                         };
1062                                 };
1063
1064                                 tdmb_dout3_pins: tdmb_dout3 {
1065                                         mux {
1066                                                 groups = "tdmb_dout3";
1067                                                 function = "tdmb";
1068                                         };
1069                                 };
1070
1071                                 tdmc_sclk_pins: tdmc_sclk {
1072                                         mux {
1073                                                 groups = "tdmc_sclk";
1074                                                 function = "tdmc";
1075                                         };
1076                                 };
1077
1078                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1079                                         mux {
1080                                                 groups = "tdmc_sclk_slv";
1081                                                 function = "tdmc";
1082                                         };
1083                                 };
1084
1085                                 tdmc_fs_pins: tdmc_fs {
1086                                         mux {
1087                                                 groups = "tdmc_fs";
1088                                                 function = "tdmc";
1089                                         };
1090                                 };
1091
1092                                 tdmc_fs_slv_pins: tdmc_fs_slv {
1093                                         mux {
1094                                                 groups = "tdmc_fs_slv";
1095                                                 function = "tdmc";
1096                                         };
1097                                 };
1098
1099                                 tdmc_din0_pins: tdmc_din0 {
1100                                         mux {
1101                                                 groups = "tdmc_din0";
1102                                                 function = "tdmc";
1103                                         };
1104                                 };
1105
1106                                 tdmc_dout0_pins: tdmc_dout0 {
1107                                         mux {
1108                                                 groups = "tdmc_dout0";
1109                                                 function = "tdmc";
1110                                         };
1111                                 };
1112
1113                                 tdmc_din1_pins: tdmc_din1 {
1114                                         mux {
1115                                                 groups = "tdmc_din1";
1116                                                 function = "tdmc";
1117                                         };
1118                                 };
1119
1120                                 tdmc_dout1_pins: tdmc_dout1 {
1121                                         mux {
1122                                                 groups = "tdmc_dout1";
1123                                                 function = "tdmc";
1124                                         };
1125                                 };
1126
1127                                 tdmc_din2_pins: tdmc_din2 {
1128                                         mux {
1129                                                 groups = "tdmc_din2";
1130                                                 function = "tdmc";
1131                                         };
1132                                 };
1133
1134                                 tdmc_dout2_pins: tdmc_dout2 {
1135                                         mux {
1136                                                 groups = "tdmc_dout2";
1137                                                 function = "tdmc";
1138                                         };
1139                                 };
1140
1141                                 tdmc_din3_pins: tdmc_din3 {
1142                                         mux {
1143                                                 groups = "tdmc_din3";
1144                                                 function = "tdmc";
1145                                         };
1146                                 };
1147
1148                                 tdmc_dout3_pins: tdmc_dout3 {
1149                                         mux {
1150                                                 groups = "tdmc_dout3";
1151                                                 function = "tdmc";
1152                                         };
1153                                 };
1154                         };
1155                 };
1156
1157                 sram: sram@fffc0000 {
1158                         compatible = "amlogic,meson-axg-sram", "mmio-sram";
1159                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1160                         #address-cells = <1>;
1161                         #size-cells = <1>;
1162                         ranges = <0 0x0 0xfffc0000 0x20000>;
1163
1164                         cpu_scp_lpri: scp-shmem@0 {
1165                                 compatible = "amlogic,meson-axg-scp-shmem";
1166                                 reg = <0x13000 0x400>;
1167                         };
1168
1169                         cpu_scp_hpri: scp-shmem@200 {
1170                                 compatible = "amlogic,meson-axg-scp-shmem";
1171                                 reg = <0x13400 0x400>;
1172                         };
1173                 };
1174
1175                 aobus: bus@ff800000 {
1176                         compatible = "simple-bus";
1177                         reg = <0x0 0xff800000 0x0 0x100000>;
1178                         #address-cells = <2>;
1179                         #size-cells = <2>;
1180                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1181
1182                         sysctrl_AO: sys-ctrl@0 {
1183                                 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1184                                 reg =  <0x0 0x0 0x0 0x100>;
1185
1186                                 clkc_AO: clock-controller {
1187                                         compatible = "amlogic,meson-axg-aoclkc";
1188                                         #clock-cells = <1>;
1189                                         #reset-cells = <1>;
1190                                 };
1191                         };
1192
1193                         pinctrl_aobus: pinctrl@14 {
1194                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1195                                 #address-cells = <2>;
1196                                 #size-cells = <2>;
1197                                 ranges;
1198
1199                                 gpio_ao: bank@14 {
1200                                         reg = <0x0 0x00014 0x0 0x8>,
1201                                                 <0x0 0x0002c 0x0 0x4>,
1202                                                 <0x0 0x00024 0x0 0x8>;
1203                                         reg-names = "mux", "pull", "gpio";
1204                                         gpio-controller;
1205                                         #gpio-cells = <2>;
1206                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1207                                 };
1208
1209                                 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1210                                         mux {
1211                                                 groups = "i2c_ao_sck_4";
1212                                                 function = "i2c_ao";
1213                                         };
1214                                 };
1215
1216                                 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1217                                         mux {
1218                                                 groups = "i2c_ao_sck_8";
1219                                                 function = "i2c_ao";
1220                                         };
1221                                 };
1222
1223                                 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1224                                         mux {
1225                                                 groups = "i2c_ao_sck_10";
1226                                                 function = "i2c_ao";
1227                                         };
1228                                 };
1229
1230                                 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1231                                         mux {
1232                                                 groups = "i2c_ao_sda_5";
1233                                                 function = "i2c_ao";
1234                                         };
1235                                 };
1236
1237                                 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1238                                         mux {
1239                                                 groups = "i2c_ao_sda_9";
1240                                                 function = "i2c_ao";
1241                                         };
1242                                 };
1243
1244                                 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1245                                         mux {
1246                                                 groups = "i2c_ao_sda_11";
1247                                                 function = "i2c_ao";
1248                                         };
1249                                 };
1250
1251                                 remote_input_ao_pins: remote_input_ao {
1252                                         mux {
1253                                                 groups = "remote_input_ao";
1254                                                 function = "remote_input_ao";
1255                                         };
1256                                 };
1257
1258                                 uart_ao_a_pins: uart_ao_a {
1259                                         mux {
1260                                                 groups = "uart_ao_tx_a",
1261                                                         "uart_ao_rx_a";
1262                                                 function = "uart_ao_a";
1263                                         };
1264                                 };
1265
1266                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1267                                         mux {
1268                                                 groups = "uart_ao_cts_a",
1269                                                         "uart_ao_rts_a";
1270                                                 function = "uart_ao_a";
1271                                         };
1272                                 };
1273
1274                                 uart_ao_b_pins: uart_ao_b {
1275                                         mux {
1276                                                 groups = "uart_ao_tx_b",
1277                                                         "uart_ao_rx_b";
1278                                                 function = "uart_ao_b";
1279                                         };
1280                                 };
1281
1282                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1283                                         mux {
1284                                                 groups = "uart_ao_cts_b",
1285                                                         "uart_ao_rts_b";
1286                                                 function = "uart_ao_b";
1287                                         };
1288                                 };
1289                         };
1290
1291                         sec_AO: ao-secure@140 {
1292                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1293                                 reg = <0x0 0x140 0x0 0x140>;
1294                                 amlogic,has-chip-id;
1295                         };
1296
1297                         pwm_AO_ab: pwm@7000 {
1298                                 compatible = "amlogic,meson-axg-ao-pwm";
1299                                 reg = <0x0 0x07000 0x0 0x20>;
1300                                 #pwm-cells = <3>;
1301                                 status = "disabled";
1302                         };
1303
1304                         pwm_AO_cd: pwm@2000 {
1305                                 compatible = "amlogic,meson-axg-ao-pwm";
1306                                 reg = <0x0 0x02000  0x0 0x20>;
1307                                 #pwm-cells = <3>;
1308                                 status = "disabled";
1309                         };
1310
1311                         i2c_AO: i2c@5000 {
1312                                 compatible = "amlogic,meson-axg-i2c";
1313                                 reg = <0x0 0x05000 0x0 0x20>;
1314                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1315                                 clocks = <&clkc CLKID_AO_I2C>;
1316                                 #address-cells = <1>;
1317                                 #size-cells = <0>;
1318                                 status = "disabled";
1319                         };
1320
1321                         uart_AO: serial@3000 {
1322                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1323                                 reg = <0x0 0x3000 0x0 0x18>;
1324                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1325                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1326                                 clock-names = "xtal", "pclk", "baud";
1327                                 status = "disabled";
1328                         };
1329
1330                         uart_AO_B: serial@4000 {
1331                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1332                                 reg = <0x0 0x4000 0x0 0x18>;
1333                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1334                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1335                                 clock-names = "xtal", "pclk", "baud";
1336                                 status = "disabled";
1337                         };
1338
1339                         ir: ir@8000 {
1340                                 compatible = "amlogic,meson-gxbb-ir";
1341                                 reg = <0x0 0x8000 0x0 0x20>;
1342                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1343                                 status = "disabled";
1344                         };
1345
1346                         saradc: adc@9000 {
1347                                 compatible = "amlogic,meson-axg-saradc",
1348                                         "amlogic,meson-saradc";
1349                                 reg = <0x0 0x9000 0x0 0x38>;
1350                                 #io-channel-cells = <1>;
1351                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1352                                 clocks = <&xtal>,
1353                                         <&clkc_AO CLKID_AO_SAR_ADC>,
1354                                         <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1355                                         <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1356                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1357                                 status = "disabled";
1358                         };
1359                 };
1360         };
1361 };