Merge tag 'amlogic-dt64-3' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
[muen/linux.git] / arch / arm64 / boot / dts / amlogic / meson-axg.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4  */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/axg-audio-clkc.h>
10 #include <dt-bindings/clock/axg-clkc.h>
11 #include <dt-bindings/clock/axg-aoclkc.h>
12 #include <dt-bindings/gpio/meson-axg-gpio.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
14
15 / {
16         compatible = "amlogic,meson-axg";
17
18         interrupt-parent = <&gic>;
19         #address-cells = <2>;
20         #size-cells = <2>;
21
22         reserved-memory {
23                 #address-cells = <2>;
24                 #size-cells = <2>;
25                 ranges;
26
27                 /* 16 MiB reserved for Hardware ROM Firmware */
28                 hwrom_reserved: hwrom@0 {
29                         reg = <0x0 0x0 0x0 0x1000000>;
30                         no-map;
31                 };
32
33                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
34                 secmon_reserved: secmon@5000000 {
35                         reg = <0x0 0x05000000 0x0 0x300000>;
36                         no-map;
37                 };
38         };
39
40         cpus {
41                 #address-cells = <0x2>;
42                 #size-cells = <0x0>;
43
44                 cpu0: cpu@0 {
45                         device_type = "cpu";
46                         compatible = "arm,cortex-a53", "arm,armv8";
47                         reg = <0x0 0x0>;
48                         enable-method = "psci";
49                         next-level-cache = <&l2>;
50                 };
51
52                 cpu1: cpu@1 {
53                         device_type = "cpu";
54                         compatible = "arm,cortex-a53", "arm,armv8";
55                         reg = <0x0 0x1>;
56                         enable-method = "psci";
57                         next-level-cache = <&l2>;
58                 };
59
60                 cpu2: cpu@2 {
61                         device_type = "cpu";
62                         compatible = "arm,cortex-a53", "arm,armv8";
63                         reg = <0x0 0x2>;
64                         enable-method = "psci";
65                         next-level-cache = <&l2>;
66                 };
67
68                 cpu3: cpu@3 {
69                         device_type = "cpu";
70                         compatible = "arm,cortex-a53", "arm,armv8";
71                         reg = <0x0 0x3>;
72                         enable-method = "psci";
73                         next-level-cache = <&l2>;
74                 };
75
76                 l2: l2-cache0 {
77                         compatible = "cache";
78                 };
79         };
80
81         arm-pmu {
82                 compatible = "arm,cortex-a53-pmu";
83                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
84                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
85                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88         };
89
90         psci {
91                 compatible = "arm,psci-1.0";
92                 method = "smc";
93         };
94
95         tdmif_a: audio-controller@0 {
96                 compatible = "amlogic,axg-tdm-iface";
97                 #sound-dai-cells = <0>;
98                 sound-name-prefix = "TDM_A";
99                 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
100                          <&clkc_audio AUD_CLKID_MST_A_SCLK>,
101                          <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
102                 clock-names = "mclk", "sclk", "lrclk";
103                 status = "disabled";
104         };
105
106         tdmif_b: audio-controller@1 {
107                 compatible = "amlogic,axg-tdm-iface";
108                 #sound-dai-cells = <0>;
109                 sound-name-prefix = "TDM_B";
110                 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
111                          <&clkc_audio AUD_CLKID_MST_B_SCLK>,
112                          <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
113                 clock-names = "mclk", "sclk", "lrclk";
114                 status = "disabled";
115         };
116
117         tdmif_c: audio-controller@2 {
118                 compatible = "amlogic,axg-tdm-iface";
119                 #sound-dai-cells = <0>;
120                 sound-name-prefix = "TDM_C";
121                 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
122                          <&clkc_audio AUD_CLKID_MST_C_SCLK>,
123                          <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
124                 clock-names = "mclk", "sclk", "lrclk";
125                 status = "disabled";
126         };
127
128         timer {
129                 compatible = "arm,armv8-timer";
130                 interrupts = <GIC_PPI 13
131                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
132                              <GIC_PPI 14
133                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
134                              <GIC_PPI 11
135                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
136                              <GIC_PPI 10
137                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
138         };
139
140         xtal: xtal-clk {
141                 compatible = "fixed-clock";
142                 clock-frequency = <24000000>;
143                 clock-output-names = "xtal";
144                 #clock-cells = <0>;
145         };
146
147         ao_alt_xtal: ao_alt_xtal-clk {
148                 compatible = "fixed-clock";
149                 clock-frequency = <32000000>;
150                 clock-output-names = "ao_alt_xtal";
151                 #clock-cells = <0>;
152         };
153
154         soc {
155                 compatible = "simple-bus";
156                 #address-cells = <2>;
157                 #size-cells = <2>;
158                 ranges;
159
160                 apb: apb@ffe00000 {
161                         compatible = "simple-bus";
162                         reg = <0x0 0xffe00000 0x0 0x200000>;
163                         #address-cells = <2>;
164                         #size-cells = <2>;
165                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
166
167                         sd_emmc_b: sd@5000 {
168                                 compatible = "amlogic,meson-axg-mmc";
169                                 reg = <0x0 0x5000 0x0 0x800>;
170                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
171                                 status = "disabled";
172                                 clocks = <&clkc CLKID_SD_EMMC_B>,
173                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
174                                         <&clkc CLKID_FCLK_DIV2>;
175                                 clock-names = "core", "clkin0", "clkin1";
176                                 resets = <&reset RESET_SD_EMMC_B>;
177                         };
178
179                         sd_emmc_c: mmc@7000 {
180                                 compatible = "amlogic,meson-axg-mmc";
181                                 reg = <0x0 0x7000 0x0 0x800>;
182                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
183                                 status = "disabled";
184                                 clocks = <&clkc CLKID_SD_EMMC_C>,
185                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
186                                         <&clkc CLKID_FCLK_DIV2>;
187                                 clock-names = "core", "clkin0", "clkin1";
188                                 resets = <&reset RESET_SD_EMMC_C>;
189                         };
190                 };
191
192                 audio: bus@ff642000 {
193                         compatible = "simple-bus";
194                         reg = <0x0 0xff642000 0x0 0x2000>;
195                         #address-cells = <2>;
196                         #size-cells = <2>;
197                         ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
198
199                         clkc_audio: clock-controller@0 {
200                                 compatible = "amlogic,axg-audio-clkc";
201                                 reg = <0x0 0x0 0x0 0xb4>;
202                                 #clock-cells = <1>;
203
204                                 clocks = <&clkc CLKID_AUDIO>,
205                                          <&clkc CLKID_MPLL0>,
206                                          <&clkc CLKID_MPLL1>,
207                                          <&clkc CLKID_MPLL2>,
208                                          <&clkc CLKID_MPLL3>,
209                                          <&clkc CLKID_HIFI_PLL>,
210                                          <&clkc CLKID_FCLK_DIV3>,
211                                          <&clkc CLKID_FCLK_DIV4>,
212                                          <&clkc CLKID_GP0_PLL>;
213                                 clock-names = "pclk",
214                                               "mst_in0",
215                                               "mst_in1",
216                                               "mst_in2",
217                                               "mst_in3",
218                                               "mst_in4",
219                                               "mst_in5",
220                                               "mst_in6",
221                                               "mst_in7";
222
223                                 resets = <&reset RESET_AUDIO>;
224                         };
225
226                         arb: reset-controller@280 {
227                                 compatible = "amlogic,meson-axg-audio-arb";
228                                 reg = <0x0 0x280 0x0 0x4>;
229                                 #reset-cells = <1>;
230                                 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
231                         };
232
233                         tdmin_a: audio-controller@300 {
234                                 compatible = "amlogic,axg-tdmin";
235                                 reg = <0x0 0x300 0x0 0x40>;
236                                 sound-name-prefix = "TDMIN_A";
237                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
238                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
239                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
240                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
241                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
242                                 clock-names = "pclk", "sclk", "sclk_sel",
243                                               "lrclk", "lrclk_sel";
244                                 status = "disabled";
245                         };
246
247                         tdmin_b: audio-controller@340 {
248                                 compatible = "amlogic,axg-tdmin";
249                                 reg = <0x0 0x340 0x0 0x40>;
250                                 sound-name-prefix = "TDMIN_B";
251                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
252                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
253                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
254                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
255                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
256                                 clock-names = "pclk", "sclk", "sclk_sel",
257                                               "lrclk", "lrclk_sel";
258                                 status = "disabled";
259                         };
260
261                         tdmin_c: audio-controller@380 {
262                                 compatible = "amlogic,axg-tdmin";
263                                 reg = <0x0 0x380 0x0 0x40>;
264                                 sound-name-prefix = "TDMIN_C";
265                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
266                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
267                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
268                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
269                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
270                                 clock-names = "pclk", "sclk", "sclk_sel",
271                                               "lrclk", "lrclk_sel";
272                                 status = "disabled";
273                         };
274
275                         tdmin_lb: audio-controller@3c0 {
276                                 compatible = "amlogic,axg-tdmin";
277                                 reg = <0x0 0x3c0 0x0 0x40>;
278                                 sound-name-prefix = "TDMIN_LB";
279                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
280                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
281                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
282                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
283                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
284                                 clock-names = "pclk", "sclk", "sclk_sel",
285                                               "lrclk", "lrclk_sel";
286                                 status = "disabled";
287                         };
288
289                         spdifout: audio-controller@480 {
290                                 compatible = "amlogic,axg-spdifout";
291                                 reg = <0x0 0x480 0x0 0x50>;
292                                 #sound-dai-cells = <0>;
293                                 sound-name-prefix = "SPDIFOUT";
294                                 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
295                                          <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
296                                 clock-names = "pclk", "mclk";
297                                 status = "disabled";
298                         };
299
300                         tdmout_a: audio-controller@500 {
301                                 compatible = "amlogic,axg-tdmout";
302                                 reg = <0x0 0x500 0x0 0x40>;
303                                 sound-name-prefix = "TDMOUT_A";
304                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
305                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
306                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
307                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
308                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
309                                 clock-names = "pclk", "sclk", "sclk_sel",
310                                               "lrclk", "lrclk_sel";
311                                 status = "disabled";
312                         };
313
314                         tdmout_b: audio-controller@540 {
315                                 compatible = "amlogic,axg-tdmout";
316                                 reg = <0x0 0x540 0x0 0x40>;
317                                 sound-name-prefix = "TDMOUT_B";
318                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
319                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
320                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
321                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
322                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
323                                 clock-names = "pclk", "sclk", "sclk_sel",
324                                               "lrclk", "lrclk_sel";
325                                 status = "disabled";
326                         };
327
328                         tdmout_c: audio-controller@580 {
329                                 compatible = "amlogic,axg-tdmout";
330                                 reg = <0x0 0x580 0x0 0x40>;
331                                 sound-name-prefix = "TDMOUT_C";
332                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
333                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
334                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
335                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
336                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
337                                 clock-names = "pclk", "sclk", "sclk_sel",
338                                               "lrclk", "lrclk_sel";
339                                 status = "disabled";
340                         };
341                 };
342
343                 cbus: bus@ffd00000 {
344                         compatible = "simple-bus";
345                         reg = <0x0 0xffd00000 0x0 0x25000>;
346                         #address-cells = <2>;
347                         #size-cells = <2>;
348                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
349
350                         gpio_intc: interrupt-controller@f080 {
351                                 compatible = "amlogic,meson-gpio-intc";
352                                 reg = <0x0 0xf080 0x0 0x10>;
353                                 interrupt-controller;
354                                 #interrupt-cells = <2>;
355                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
356                                 status = "disabled";
357                         };
358
359                         pwm_ab: pwm@1b000 {
360                                 compatible = "amlogic,meson-axg-ee-pwm";
361                                 reg = <0x0 0x1b000 0x0 0x20>;
362                                 #pwm-cells = <3>;
363                                 status = "disabled";
364                         };
365
366                         pwm_cd: pwm@1a000 {
367                                 compatible = "amlogic,meson-axg-ee-pwm";
368                                 reg = <0x0 0x1a000 0x0 0x20>;
369                                 #pwm-cells = <3>;
370                                 status = "disabled";
371                         };
372
373                         reset: reset-controller@1004 {
374                                 compatible = "amlogic,meson-axg-reset";
375                                 reg = <0x0 0x01004 0x0 0x9c>;
376                                 #reset-cells = <1>;
377                         };
378
379                         spicc0: spi@13000 {
380                                 compatible = "amlogic,meson-axg-spicc";
381                                 reg = <0x0 0x13000 0x0 0x3c>;
382                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
383                                 clocks = <&clkc CLKID_SPICC0>;
384                                 clock-names = "core";
385                                 #address-cells = <1>;
386                                 #size-cells = <0>;
387                                 status = "disabled";
388                         };
389
390                         spicc1: spi@15000 {
391                                 compatible = "amlogic,meson-axg-spicc";
392                                 reg = <0x0 0x15000 0x0 0x3c>;
393                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
394                                 clocks = <&clkc CLKID_SPICC1>;
395                                 clock-names = "core";
396                                 #address-cells = <1>;
397                                 #size-cells = <0>;
398                                 status = "disabled";
399                         };
400
401                         i2c0: i2c@1f000 {
402                                 compatible = "amlogic,meson-axg-i2c";
403                                 reg = <0x0 0x1f000 0x0 0x20>;
404                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
405                                 clocks = <&clkc CLKID_I2C>;
406                                 #address-cells = <1>;
407                                 #size-cells = <0>;
408                                 status = "disabled";
409                         };
410
411                         i2c1: i2c@1e000 {
412                                 compatible = "amlogic,meson-axg-i2c";
413                                 reg = <0x0 0x1e000 0x0 0x20>;
414                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
415                                 clocks = <&clkc CLKID_I2C>;
416                                 #address-cells = <1>;
417                                 #size-cells = <0>;
418                                 status = "disabled";
419                         };
420
421                         i2c2: i2c@1d000 {
422                                 compatible = "amlogic,meson-axg-i2c";
423                                 reg = <0x0 0x1d000 0x0 0x20>;
424                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
425                                 clocks = <&clkc CLKID_I2C>;
426                                 #address-cells = <1>;
427                                 #size-cells = <0>;
428                                 status = "disabled";
429                         };
430
431                         i2c3: i2c@1c000 {
432                                 compatible = "amlogic,meson-axg-i2c";
433                                 reg = <0x0 0x1c000 0x0 0x20>;
434                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
435                                 clocks = <&clkc CLKID_I2C>;
436                                 #address-cells = <1>;
437                                 #size-cells = <0>;
438                                 status = "disabled";
439                         };
440
441                         uart_A: serial@24000 {
442                                 compatible = "amlogic,meson-gx-uart";
443                                 reg = <0x0 0x24000 0x0 0x18>;
444                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
445                                 status = "disabled";
446                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
447                                 clock-names = "xtal", "pclk", "baud";
448                         };
449
450                         uart_B: serial@23000 {
451                                 compatible = "amlogic,meson-gx-uart";
452                                 reg = <0x0 0x23000 0x0 0x18>;
453                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
454                                 status = "disabled";
455                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
456                                 clock-names = "xtal", "pclk", "baud";
457                         };
458                 };
459
460                 ethmac: ethernet@ff3f0000 {
461                         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
462                         reg = <0x0 0xff3f0000 0x0 0x10000
463                                 0x0 0xff634540 0x0 0x8>;
464                         interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
465                         interrupt-names = "macirq";
466                         clocks = <&clkc CLKID_ETH>,
467                                  <&clkc CLKID_FCLK_DIV2>,
468                                  <&clkc CLKID_MPLL2>;
469                         clock-names = "stmmaceth", "clkin0", "clkin1";
470                         status = "disabled";
471                 };
472
473                 gic: interrupt-controller@ffc01000 {
474                         compatible = "arm,gic-400";
475                         reg = <0x0 0xffc01000 0 0x1000>,
476                               <0x0 0xffc02000 0 0x2000>,
477                               <0x0 0xffc04000 0 0x2000>,
478                               <0x0 0xffc06000 0 0x2000>;
479                         interrupt-controller;
480                         interrupts = <GIC_PPI 9
481                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
482                         #interrupt-cells = <3>;
483                         #address-cells = <0>;
484                 };
485
486                 hiubus: bus@ff63c000 {
487                         compatible = "simple-bus";
488                         reg = <0x0 0xff63c000 0x0 0x1c00>;
489                         #address-cells = <2>;
490                         #size-cells = <2>;
491                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
492
493                         sysctrl: system-controller@0 {
494                                 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
495                                 reg = <0 0 0 0x400>;
496
497                                 clkc: clock-controller {
498                                         compatible = "amlogic,axg-clkc";
499                                         #clock-cells = <1>;
500                                 };
501                         };
502                 };
503
504                 mailbox: mailbox@ff63dc00 {
505                         compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
506                         reg = <0 0xff63dc00 0 0x400>;
507                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
508                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
509                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
510                         #mbox-cells = <1>;
511                 };
512
513                 periphs: periphs@ff634000 {
514                         compatible = "simple-bus";
515                         reg = <0x0 0xff634000 0x0 0x2000>;
516                         #address-cells = <2>;
517                         #size-cells = <2>;
518                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
519
520                         hwrng: rng {
521                                 compatible = "amlogic,meson-rng";
522                                 reg = <0x0 0x18 0x0 0x4>;
523                                 clocks = <&clkc CLKID_RNG0>;
524                                 clock-names = "core";
525                         };
526
527                         pinctrl_periphs: pinctrl@480 {
528                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
529                                 #address-cells = <2>;
530                                 #size-cells = <2>;
531                                 ranges;
532
533                                 gpio: bank@480 {
534                                         reg = <0x0 0x00480 0x0 0x40>,
535                                                 <0x0 0x004e8 0x0 0x14>,
536                                                 <0x0 0x00520 0x0 0x14>,
537                                                 <0x0 0x00430 0x0 0x3c>;
538                                         reg-names = "mux", "pull", "pull-enable", "gpio";
539                                         gpio-controller;
540                                         #gpio-cells = <2>;
541                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
542                                 };
543
544                                 emmc_pins: emmc {
545                                         mux {
546                                                 groups = "emmc_nand_d0",
547                                                         "emmc_nand_d1",
548                                                         "emmc_nand_d2",
549                                                         "emmc_nand_d3",
550                                                         "emmc_nand_d4",
551                                                         "emmc_nand_d5",
552                                                         "emmc_nand_d6",
553                                                         "emmc_nand_d7",
554                                                         "emmc_clk",
555                                                         "emmc_cmd",
556                                                         "emmc_ds";
557                                                 function = "emmc";
558                                         };
559                                 };
560
561                                 emmc_clk_gate_pins: emmc_clk_gate {
562                                         mux {
563                                                 groups = "BOOT_8";
564                                                 function = "gpio_periphs";
565                                         };
566                                         cfg-pull-down {
567                                                 pins = "BOOT_8";
568                                                 bias-pull-down;
569                                         };
570                                 };
571
572                                 sdio_pins: sdio {
573                                         mux {
574                                                 groups = "sdio_d0",
575                                                         "sdio_d1",
576                                                         "sdio_d2",
577                                                         "sdio_d3",
578                                                         "sdio_cmd",
579                                                         "sdio_clk";
580                                                 function = "sdio";
581                                         };
582                                 };
583
584                                 sdio_clk_gate_pins: sdio_clk_gate {
585                                         mux {
586                                                 groups = "GPIOX_4";
587                                                 function = "gpio_periphs";
588                                         };
589                                         cfg-pull-down {
590                                                 pins = "GPIOX_4";
591                                                 bias-pull-down;
592                                         };
593                                 };
594
595                                 eth_rmii_x_pins: eth-x-rmii {
596                                         mux {
597                                                 groups = "eth_mdio_x",
598                                                        "eth_mdc_x",
599                                                        "eth_rgmii_rx_clk_x",
600                                                        "eth_rx_dv_x",
601                                                        "eth_rxd0_x",
602                                                        "eth_rxd1_x",
603                                                        "eth_txen_x",
604                                                        "eth_txd0_x",
605                                                        "eth_txd1_x";
606                                                 function = "eth";
607                                         };
608                                 };
609
610                                 eth_rmii_y_pins: eth-y-rmii {
611                                         mux {
612                                                 groups = "eth_mdio_y",
613                                                        "eth_mdc_y",
614                                                        "eth_rgmii_rx_clk_y",
615                                                        "eth_rx_dv_y",
616                                                        "eth_rxd0_y",
617                                                        "eth_rxd1_y",
618                                                        "eth_txen_y",
619                                                        "eth_txd0_y",
620                                                        "eth_txd1_y";
621                                                 function = "eth";
622                                         };
623                                 };
624
625                                 eth_rgmii_x_pins: eth-x-rgmii {
626                                         mux {
627                                                 groups = "eth_mdio_x",
628                                                        "eth_mdc_x",
629                                                        "eth_rgmii_rx_clk_x",
630                                                        "eth_rx_dv_x",
631                                                        "eth_rxd0_x",
632                                                        "eth_rxd1_x",
633                                                        "eth_rxd2_rgmii",
634                                                        "eth_rxd3_rgmii",
635                                                        "eth_rgmii_tx_clk",
636                                                        "eth_txen_x",
637                                                        "eth_txd0_x",
638                                                        "eth_txd1_x",
639                                                        "eth_txd2_rgmii",
640                                                        "eth_txd3_rgmii";
641                                                 function = "eth";
642                                         };
643                                 };
644
645                                 eth_rgmii_y_pins: eth-y-rgmii {
646                                         mux {
647                                                 groups = "eth_mdio_y",
648                                                        "eth_mdc_y",
649                                                        "eth_rgmii_rx_clk_y",
650                                                        "eth_rx_dv_y",
651                                                        "eth_rxd0_y",
652                                                        "eth_rxd1_y",
653                                                        "eth_rxd2_rgmii",
654                                                        "eth_rxd3_rgmii",
655                                                        "eth_rgmii_tx_clk",
656                                                        "eth_txen_y",
657                                                        "eth_txd0_y",
658                                                        "eth_txd1_y",
659                                                        "eth_txd2_rgmii",
660                                                        "eth_txd3_rgmii";
661                                                 function = "eth";
662                                         };
663                                 };
664
665                                 pdm_dclk_a14_pins: pdm_dclk_a14 {
666                                         mux {
667                                                 groups = "pdm_dclk_a14";
668                                                 function = "pdm";
669                                         };
670                                 };
671
672                                 pdm_dclk_a19_pins: pdm_dclk_a19 {
673                                         mux {
674                                                 groups = "pdm_dclk_a19";
675                                                 function = "pdm";
676                                         };
677                                 };
678
679                                 pdm_din0_pins: pdm_din0 {
680                                         mux {
681                                                 groups = "pdm_din0";
682                                                 function = "pdm";
683                                         };
684                                 };
685
686                                 pdm_din1_pins: pdm_din1 {
687                                         mux {
688                                                 groups = "pdm_din1";
689                                                 function = "pdm";
690                                         };
691                                 };
692
693                                 pdm_din2_pins: pdm_din2 {
694                                         mux {
695                                                 groups = "pdm_din2";
696                                                 function = "pdm";
697                                         };
698                                 };
699
700                                 pdm_din3_pins: pdm_din3 {
701                                         mux {
702                                                 groups = "pdm_din3";
703                                                 function = "pdm";
704                                         };
705                                 };
706
707                                 pwm_a_a_pins: pwm_a_a {
708                                         mux {
709                                                 groups = "pwm_a_a";
710                                                 function = "pwm_a";
711                                         };
712                                 };
713
714                                 pwm_a_x18_pins: pwm_a_x18 {
715                                         mux {
716                                                 groups = "pwm_a_x18";
717                                                 function = "pwm_a";
718                                         };
719                                 };
720
721                                 pwm_a_x20_pins: pwm_a_x20 {
722                                         mux {
723                                                 groups = "pwm_a_x20";
724                                                 function = "pwm_a";
725                                         };
726                                 };
727
728                                 pwm_a_z_pins: pwm_a_z {
729                                         mux {
730                                                 groups = "pwm_a_z";
731                                                 function = "pwm_a";
732                                         };
733                                 };
734
735                                 pwm_b_a_pins: pwm_b_a {
736                                         mux {
737                                                 groups = "pwm_b_a";
738                                                 function = "pwm_b";
739                                         };
740                                 };
741
742                                 pwm_b_x_pins: pwm_b_x {
743                                         mux {
744                                                 groups = "pwm_b_x";
745                                                 function = "pwm_b";
746                                         };
747                                 };
748
749                                 pwm_b_z_pins: pwm_b_z {
750                                         mux {
751                                                 groups = "pwm_b_z";
752                                                 function = "pwm_b";
753                                         };
754                                 };
755
756                                 pwm_c_a_pins: pwm_c_a {
757                                         mux {
758                                                 groups = "pwm_c_a";
759                                                 function = "pwm_c";
760                                         };
761                                 };
762
763                                 pwm_c_x10_pins: pwm_c_x10 {
764                                         mux {
765                                                 groups = "pwm_c_x10";
766                                                 function = "pwm_c";
767                                         };
768                                 };
769
770                                 pwm_c_x17_pins: pwm_c_x17 {
771                                         mux {
772                                                 groups = "pwm_c_x17";
773                                                 function = "pwm_c";
774                                         };
775                                 };
776
777                                 pwm_d_x11_pins: pwm_d_x11 {
778                                         mux {
779                                                 groups = "pwm_d_x11";
780                                                 function = "pwm_d";
781                                         };
782                                 };
783
784                                 pwm_d_x16_pins: pwm_d_x16 {
785                                         mux {
786                                                 groups = "pwm_d_x16";
787                                                 function = "pwm_d";
788                                         };
789                                 };
790
791                                 spdif_in_z_pins: spdif_in_z {
792                                         mux {
793                                                 groups = "spdif_in_z";
794                                                 function = "spdif_in";
795                                         };
796                                 };
797
798                                 spdif_in_a1_pins: spdif_in_a1 {
799                                         mux {
800                                                 groups = "spdif_in_a1";
801                                                 function = "spdif_in";
802                                         };
803                                 };
804
805                                 spdif_in_a7_pins: spdif_in_a7 {
806                                         mux {
807                                                 groups = "spdif_in_a7";
808                                                 function = "spdif_in";
809                                         };
810                                 };
811
812                                 spdif_in_a19_pins: spdif_in_a19 {
813                                         mux {
814                                                 groups = "spdif_in_a19";
815                                                 function = "spdif_in";
816                                         };
817                                 };
818
819                                 spdif_in_a20_pins: spdif_in_a20 {
820                                         mux {
821                                                 groups = "spdif_in_a20";
822                                                 function = "spdif_in";
823                                         };
824                                 };
825
826                                 spdif_out_z_pins: spdif_out_z {
827                                         mux {
828                                                 groups = "spdif_out_z";
829                                                 function = "spdif_out";
830                                         };
831                                 };
832
833                                 spdif_out_a1_pins: spdif_out_a1 {
834                                         mux {
835                                                 groups = "spdif_out_a1";
836                                                 function = "spdif_out";
837                                         };
838                                 };
839
840                                 spdif_out_a11_pins: spdif_out_a11 {
841                                         mux {
842                                                 groups = "spdif_out_a11";
843                                                 function = "spdif_out";
844                                         };
845                                 };
846
847                                 spdif_out_a19_pins: spdif_out_a19 {
848                                         mux {
849                                                 groups = "spdif_out_a19";
850                                                 function = "spdif_out";
851                                         };
852                                 };
853
854                                 spdif_out_a20_pins: spdif_out_a20 {
855                                         mux {
856                                                 groups = "spdif_out_a20";
857                                                 function = "spdif_out";
858                                         };
859                                 };
860
861                                 spi0_pins: spi0 {
862                                         mux {
863                                                 groups = "spi0_miso",
864                                                         "spi0_mosi",
865                                                         "spi0_clk";
866                                                 function = "spi0";
867                                         };
868                                 };
869
870                                 spi0_ss0_pins: spi0_ss0 {
871                                         mux {
872                                                 groups = "spi0_ss0";
873                                                 function = "spi0";
874                                         };
875                                 };
876
877                                 spi0_ss1_pins: spi0_ss1 {
878                                         mux {
879                                                 groups = "spi0_ss1";
880                                                 function = "spi0";
881                                         };
882                                 };
883
884                                 spi0_ss2_pins: spi0_ss2 {
885                                         mux {
886                                                 groups = "spi0_ss2";
887                                                 function = "spi0";
888                                         };
889                                 };
890
891
892                                 spi1_a_pins: spi1_a {
893                                         mux {
894                                                 groups = "spi1_miso_a",
895                                                         "spi1_mosi_a",
896                                                         "spi1_clk_a";
897                                                 function = "spi1";
898                                         };
899                                 };
900
901                                 spi1_ss0_a_pins: spi1_ss0_a {
902                                         mux {
903                                                 groups = "spi1_ss0_a";
904                                                 function = "spi1";
905                                         };
906                                 };
907
908                                 spi1_ss1_pins: spi1_ss1 {
909                                         mux {
910                                                 groups = "spi1_ss1";
911                                                 function = "spi1";
912                                         };
913                                 };
914
915                                 spi1_x_pins: spi1_x {
916                                         mux {
917                                                 groups = "spi1_miso_x",
918                                                         "spi1_mosi_x",
919                                                         "spi1_clk_x";
920                                                 function = "spi1";
921                                         };
922                                 };
923
924                                 spi1_ss0_x_pins: spi1_ss0_x {
925                                         mux {
926                                                 groups = "spi1_ss0_x";
927                                                 function = "spi1";
928                                         };
929                                 };
930
931                                 i2c0_pins: i2c0 {
932                                         mux {
933                                                 groups = "i2c0_sck",
934                                                         "i2c0_sda";
935                                                 function = "i2c0";
936                                         };
937                                 };
938
939                                 i2c1_z_pins: i2c1_z {
940                                         mux {
941                                                 groups = "i2c1_sck_z",
942                                                         "i2c1_sda_z";
943                                                 function = "i2c1";
944                                         };
945                                 };
946
947                                 i2c1_x_pins: i2c1_x {
948                                         mux {
949                                                 groups = "i2c1_sck_x",
950                                                         "i2c1_sda_x";
951                                                 function = "i2c1";
952                                         };
953                                 };
954
955                                 i2c2_x_pins: i2c2_x {
956                                         mux {
957                                                 groups = "i2c2_sck_x",
958                                                         "i2c2_sda_x";
959                                                 function = "i2c2";
960                                         };
961                                 };
962
963                                 i2c2_a_pins: i2c2_a {
964                                         mux {
965                                                 groups = "i2c2_sck_a",
966                                                         "i2c2_sda_a";
967                                                 function = "i2c2";
968                                         };
969                                 };
970
971                                 i2c3_a6_pins: i2c3_a6 {
972                                         mux {
973                                                 groups = "i2c3_sda_a6",
974                                                         "i2c3_sck_a7";
975                                                 function = "i2c3";
976                                         };
977                                 };
978
979                                 i2c3_a12_pins: i2c3_a12 {
980                                         mux {
981                                                 groups = "i2c3_sda_a12",
982                                                         "i2c3_sck_a13";
983                                                 function = "i2c3";
984                                         };
985                                 };
986
987                                 i2c3_a19_pins: i2c3_a19 {
988                                         mux {
989                                                 groups = "i2c3_sda_a19",
990                                                         "i2c3_sck_a20";
991                                                 function = "i2c3";
992                                         };
993                                 };
994
995                                 uart_a_pins: uart_a {
996                                         mux {
997                                                 groups = "uart_tx_a",
998                                                         "uart_rx_a";
999                                                 function = "uart_a";
1000                                         };
1001                                 };
1002
1003                                 uart_a_cts_rts_pins: uart_a_cts_rts {
1004                                         mux {
1005                                                 groups = "uart_cts_a",
1006                                                         "uart_rts_a";
1007                                                 function = "uart_a";
1008                                         };
1009                                 };
1010
1011                                 uart_b_x_pins: uart_b_x {
1012                                         mux {
1013                                                 groups = "uart_tx_b_x",
1014                                                         "uart_rx_b_x";
1015                                                 function = "uart_b";
1016                                         };
1017                                 };
1018
1019                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1020                                         mux {
1021                                                 groups = "uart_cts_b_x",
1022                                                         "uart_rts_b_x";
1023                                                 function = "uart_b";
1024                                         };
1025                                 };
1026
1027                                 uart_b_z_pins: uart_b_z {
1028                                         mux {
1029                                                 groups = "uart_tx_b_z",
1030                                                         "uart_rx_b_z";
1031                                                 function = "uart_b";
1032                                         };
1033                                 };
1034
1035                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1036                                         mux {
1037                                                 groups = "uart_cts_b_z",
1038                                                         "uart_rts_b_z";
1039                                                 function = "uart_b";
1040                                         };
1041                                 };
1042
1043                                 uart_ao_b_z_pins: uart_ao_b_z {
1044                                         mux {
1045                                                 groups = "uart_ao_tx_b_z",
1046                                                         "uart_ao_rx_b_z";
1047                                                 function = "uart_ao_b_z";
1048                                         };
1049                                 };
1050
1051                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1052                                         mux {
1053                                                 groups = "uart_ao_cts_b_z",
1054                                                         "uart_ao_rts_b_z";
1055                                                 function = "uart_ao_b_z";
1056                                         };
1057                                 };
1058
1059                                 mclk_b_pins: mclk_b {
1060                                         mux {
1061                                                 groups = "mclk_b";
1062                                                 function = "mclk_b";
1063                                         };
1064                                 };
1065
1066                                 mclk_c_pins: mclk_c {
1067                                         mux {
1068                                                 groups = "mclk_c";
1069                                                 function = "mclk_c";
1070                                         };
1071                                 };
1072
1073                                 tdma_sclk_pins: tdma_sclk {
1074                                         mux {
1075                                                 groups = "tdma_sclk";
1076                                                 function = "tdma";
1077                                         };
1078                                 };
1079
1080                                 tdma_sclk_slv_pins: tdma_sclk_slv {
1081                                         mux {
1082                                                 groups = "tdma_sclk_slv";
1083                                                 function = "tdma";
1084                                         };
1085                                 };
1086
1087                                 tdma_fs_pins: tdma_fs {
1088                                         mux {
1089                                                 groups = "tdma_fs";
1090                                                 function = "tdma";
1091                                         };
1092                                 };
1093
1094                                 tdma_fs_slv_pins: tdma_fs_slv {
1095                                         mux {
1096                                                 groups = "tdma_fs_slv";
1097                                                 function = "tdma";
1098                                         };
1099                                 };
1100
1101                                 tdma_din0_pins: tdma_din0 {
1102                                         mux {
1103                                                 groups = "tdma_din0";
1104                                                 function = "tdma";
1105                                         };
1106                                 };
1107
1108                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
1109                                         mux {
1110                                                 groups = "tdma_dout0_x14";
1111                                                 function = "tdma";
1112                                         };
1113                                 };
1114
1115                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
1116                                         mux {
1117                                                 groups = "tdma_dout0_x15";
1118                                                 function = "tdma";
1119                                         };
1120                                 };
1121
1122                                 tdma_dout1_pins: tdma_dout1 {
1123                                         mux {
1124                                                 groups = "tdma_dout1";
1125                                                 function = "tdma";
1126                                         };
1127                                 };
1128
1129                                 tdma_din1_pins: tdma_din1 {
1130                                         mux {
1131                                                 groups = "tdma_din1";
1132                                                 function = "tdma";
1133                                         };
1134                                 };
1135
1136                                 tdmb_sclk_pins: tdmb_sclk {
1137                                         mux {
1138                                                 groups = "tdmb_sclk";
1139                                                 function = "tdmb";
1140                                         };
1141                                 };
1142
1143                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1144                                         mux {
1145                                                 groups = "tdmb_sclk_slv";
1146                                                 function = "tdmb";
1147                                         };
1148                                 };
1149
1150                                 tdmb_fs_pins: tdmb_fs {
1151                                         mux {
1152                                                 groups = "tdmb_fs";
1153                                                 function = "tdmb";
1154                                         };
1155                                 };
1156
1157                                 tdmb_fs_slv_pins: tdmb_fs_slv {
1158                                         mux {
1159                                                 groups = "tdmb_fs_slv";
1160                                                 function = "tdmb";
1161                                         };
1162                                 };
1163
1164                                 tdmb_din0_pins: tdmb_din0 {
1165                                         mux {
1166                                                 groups = "tdmb_din0";
1167                                                 function = "tdmb";
1168                                         };
1169                                 };
1170
1171                                 tdmb_dout0_pins: tdmb_dout0 {
1172                                         mux {
1173                                                 groups = "tdmb_dout0";
1174                                                 function = "tdmb";
1175                                         };
1176                                 };
1177
1178                                 tdmb_din1_pins: tdmb_din1 {
1179                                         mux {
1180                                                 groups = "tdmb_din1";
1181                                                 function = "tdmb";
1182                                         };
1183                                 };
1184
1185                                 tdmb_dout1_pins: tdmb_dout1 {
1186                                         mux {
1187                                                 groups = "tdmb_dout1";
1188                                                 function = "tdmb";
1189                                         };
1190                                 };
1191
1192                                 tdmb_din2_pins: tdmb_din2 {
1193                                         mux {
1194                                                 groups = "tdmb_din2";
1195                                                 function = "tdmb";
1196                                         };
1197                                 };
1198
1199                                 tdmb_dout2_pins: tdmb_dout2 {
1200                                         mux {
1201                                                 groups = "tdmb_dout2";
1202                                                 function = "tdmb";
1203                                         };
1204                                 };
1205
1206                                 tdmb_din3_pins: tdmb_din3 {
1207                                         mux {
1208                                                 groups = "tdmb_din3";
1209                                                 function = "tdmb";
1210                                         };
1211                                 };
1212
1213                                 tdmb_dout3_pins: tdmb_dout3 {
1214                                         mux {
1215                                                 groups = "tdmb_dout3";
1216                                                 function = "tdmb";
1217                                         };
1218                                 };
1219
1220                                 tdmc_sclk_pins: tdmc_sclk {
1221                                         mux {
1222                                                 groups = "tdmc_sclk";
1223                                                 function = "tdmc";
1224                                         };
1225                                 };
1226
1227                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1228                                         mux {
1229                                                 groups = "tdmc_sclk_slv";
1230                                                 function = "tdmc";
1231                                         };
1232                                 };
1233
1234                                 tdmc_fs_pins: tdmc_fs {
1235                                         mux {
1236                                                 groups = "tdmc_fs";
1237                                                 function = "tdmc";
1238                                         };
1239                                 };
1240
1241                                 tdmc_fs_slv_pins: tdmc_fs_slv {
1242                                         mux {
1243                                                 groups = "tdmc_fs_slv";
1244                                                 function = "tdmc";
1245                                         };
1246                                 };
1247
1248                                 tdmc_din0_pins: tdmc_din0 {
1249                                         mux {
1250                                                 groups = "tdmc_din0";
1251                                                 function = "tdmc";
1252                                         };
1253                                 };
1254
1255                                 tdmc_dout0_pins: tdmc_dout0 {
1256                                         mux {
1257                                                 groups = "tdmc_dout0";
1258                                                 function = "tdmc";
1259                                         };
1260                                 };
1261
1262                                 tdmc_din1_pins: tdmc_din1 {
1263                                         mux {
1264                                                 groups = "tdmc_din1";
1265                                                 function = "tdmc";
1266                                         };
1267                                 };
1268
1269                                 tdmc_dout1_pins: tdmc_dout1 {
1270                                         mux {
1271                                                 groups = "tdmc_dout1";
1272                                                 function = "tdmc";
1273                                         };
1274                                 };
1275
1276                                 tdmc_din2_pins: tdmc_din2 {
1277                                         mux {
1278                                                 groups = "tdmc_din2";
1279                                                 function = "tdmc";
1280                                         };
1281                                 };
1282
1283                                 tdmc_dout2_pins: tdmc_dout2 {
1284                                         mux {
1285                                                 groups = "tdmc_dout2";
1286                                                 function = "tdmc";
1287                                         };
1288                                 };
1289
1290                                 tdmc_din3_pins: tdmc_din3 {
1291                                         mux {
1292                                                 groups = "tdmc_din3";
1293                                                 function = "tdmc";
1294                                         };
1295                                 };
1296
1297                                 tdmc_dout3_pins: tdmc_dout3 {
1298                                         mux {
1299                                                 groups = "tdmc_dout3";
1300                                                 function = "tdmc";
1301                                         };
1302                                 };
1303                         };
1304                 };
1305
1306                 sram: sram@fffc0000 {
1307                         compatible = "amlogic,meson-axg-sram", "mmio-sram";
1308                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1309                         #address-cells = <1>;
1310                         #size-cells = <1>;
1311                         ranges = <0 0x0 0xfffc0000 0x20000>;
1312
1313                         cpu_scp_lpri: scp-shmem@0 {
1314                                 compatible = "amlogic,meson-axg-scp-shmem";
1315                                 reg = <0x13000 0x400>;
1316                         };
1317
1318                         cpu_scp_hpri: scp-shmem@200 {
1319                                 compatible = "amlogic,meson-axg-scp-shmem";
1320                                 reg = <0x13400 0x400>;
1321                         };
1322                 };
1323
1324                 aobus: bus@ff800000 {
1325                         compatible = "simple-bus";
1326                         reg = <0x0 0xff800000 0x0 0x100000>;
1327                         #address-cells = <2>;
1328                         #size-cells = <2>;
1329                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1330
1331                         sysctrl_AO: sys-ctrl@0 {
1332                                 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1333                                 reg =  <0x0 0x0 0x0 0x100>;
1334
1335                                 clkc_AO: clock-controller {
1336                                         compatible = "amlogic,meson-axg-aoclkc";
1337                                         #clock-cells = <1>;
1338                                         #reset-cells = <1>;
1339                                 };
1340                         };
1341
1342                         pinctrl_aobus: pinctrl@14 {
1343                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1344                                 #address-cells = <2>;
1345                                 #size-cells = <2>;
1346                                 ranges;
1347
1348                                 gpio_ao: bank@14 {
1349                                         reg = <0x0 0x00014 0x0 0x8>,
1350                                                 <0x0 0x0002c 0x0 0x4>,
1351                                                 <0x0 0x00024 0x0 0x8>;
1352                                         reg-names = "mux", "pull", "gpio";
1353                                         gpio-controller;
1354                                         #gpio-cells = <2>;
1355                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1356                                 };
1357
1358                                 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1359                                         mux {
1360                                                 groups = "i2c_ao_sck_4";
1361                                                 function = "i2c_ao";
1362                                         };
1363                                 };
1364
1365                                 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1366                                         mux {
1367                                                 groups = "i2c_ao_sck_8";
1368                                                 function = "i2c_ao";
1369                                         };
1370                                 };
1371
1372                                 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1373                                         mux {
1374                                                 groups = "i2c_ao_sck_10";
1375                                                 function = "i2c_ao";
1376                                         };
1377                                 };
1378
1379                                 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1380                                         mux {
1381                                                 groups = "i2c_ao_sda_5";
1382                                                 function = "i2c_ao";
1383                                         };
1384                                 };
1385
1386                                 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1387                                         mux {
1388                                                 groups = "i2c_ao_sda_9";
1389                                                 function = "i2c_ao";
1390                                         };
1391                                 };
1392
1393                                 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1394                                         mux {
1395                                                 groups = "i2c_ao_sda_11";
1396                                                 function = "i2c_ao";
1397                                         };
1398                                 };
1399
1400                                 remote_input_ao_pins: remote_input_ao {
1401                                         mux {
1402                                                 groups = "remote_input_ao";
1403                                                 function = "remote_input_ao";
1404                                         };
1405                                 };
1406
1407                                 uart_ao_a_pins: uart_ao_a {
1408                                         mux {
1409                                                 groups = "uart_ao_tx_a",
1410                                                         "uart_ao_rx_a";
1411                                                 function = "uart_ao_a";
1412                                         };
1413                                 };
1414
1415                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1416                                         mux {
1417                                                 groups = "uart_ao_cts_a",
1418                                                         "uart_ao_rts_a";
1419                                                 function = "uart_ao_a";
1420                                         };
1421                                 };
1422
1423                                 uart_ao_b_pins: uart_ao_b {
1424                                         mux {
1425                                                 groups = "uart_ao_tx_b",
1426                                                         "uart_ao_rx_b";
1427                                                 function = "uart_ao_b";
1428                                         };
1429                                 };
1430
1431                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1432                                         mux {
1433                                                 groups = "uart_ao_cts_b",
1434                                                         "uart_ao_rts_b";
1435                                                 function = "uart_ao_b";
1436                                         };
1437                                 };
1438                         };
1439
1440                         sec_AO: ao-secure@140 {
1441                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1442                                 reg = <0x0 0x140 0x0 0x140>;
1443                                 amlogic,has-chip-id;
1444                         };
1445
1446                         pwm_AO_ab: pwm@7000 {
1447                                 compatible = "amlogic,meson-axg-ao-pwm";
1448                                 reg = <0x0 0x07000 0x0 0x20>;
1449                                 #pwm-cells = <3>;
1450                                 status = "disabled";
1451                         };
1452
1453                         pwm_AO_cd: pwm@2000 {
1454                                 compatible = "amlogic,meson-axg-ao-pwm";
1455                                 reg = <0x0 0x02000  0x0 0x20>;
1456                                 #pwm-cells = <3>;
1457                                 status = "disabled";
1458                         };
1459
1460                         i2c_AO: i2c@5000 {
1461                                 compatible = "amlogic,meson-axg-i2c";
1462                                 reg = <0x0 0x05000 0x0 0x20>;
1463                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1464                                 clocks = <&clkc CLKID_AO_I2C>;
1465                                 #address-cells = <1>;
1466                                 #size-cells = <0>;
1467                                 status = "disabled";
1468                         };
1469
1470                         uart_AO: serial@3000 {
1471                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1472                                 reg = <0x0 0x3000 0x0 0x18>;
1473                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1474                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1475                                 clock-names = "xtal", "pclk", "baud";
1476                                 status = "disabled";
1477                         };
1478
1479                         uart_AO_B: serial@4000 {
1480                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1481                                 reg = <0x0 0x4000 0x0 0x18>;
1482                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1483                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1484                                 clock-names = "xtal", "pclk", "baud";
1485                                 status = "disabled";
1486                         };
1487
1488                         ir: ir@8000 {
1489                                 compatible = "amlogic,meson-gxbb-ir";
1490                                 reg = <0x0 0x8000 0x0 0x20>;
1491                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1492                                 status = "disabled";
1493                         };
1494
1495                         saradc: adc@9000 {
1496                                 compatible = "amlogic,meson-axg-saradc",
1497                                         "amlogic,meson-saradc";
1498                                 reg = <0x0 0x9000 0x0 0x38>;
1499                                 #io-channel-cells = <1>;
1500                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1501                                 clocks = <&xtal>,
1502                                         <&clkc_AO CLKID_AO_SAR_ADC>,
1503                                         <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1504                                         <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1505                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1506                                 status = "disabled";
1507                         };
1508                 };
1509         };
1510 };