1cb8e7e0d0dabc554b73c82e664573c7a18aa067
[muen/linux.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2016 Andreas Färber
4  */
5
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
12
13 / {
14         compatible = "amlogic,meson-gxbb";
15
16         soc {
17                 usb0_phy: phy@c0000000 {
18                         compatible = "amlogic,meson-gxbb-usb2-phy";
19                         #phy-cells = <0>;
20                         reg = <0x0 0xc0000000 0x0 0x20>;
21                         resets = <&reset RESET_USB_OTG>;
22                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23                         clock-names = "usb_general", "usb";
24                         status = "disabled";
25                 };
26
27                 usb1_phy: phy@c0000020 {
28                         compatible = "amlogic,meson-gxbb-usb2-phy";
29                         #phy-cells = <0>;
30                         reg = <0x0 0xc0000020 0x0 0x20>;
31                         resets = <&reset RESET_USB_OTG>;
32                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33                         clock-names = "usb_general", "usb";
34                         status = "disabled";
35                 };
36
37                 usb0: usb@c9000000 {
38                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39                         reg = <0x0 0xc9000000 0x0 0x40000>;
40                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41                         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42                         clock-names = "otg";
43                         phys = <&usb0_phy>;
44                         phy-names = "usb2-phy";
45                         dr_mode = "host";
46                         status = "disabled";
47                 };
48
49                 usb1: usb@c9100000 {
50                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51                         reg = <0x0 0xc9100000 0x0 0x40000>;
52                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53                         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54                         clock-names = "otg";
55                         phys = <&usb1_phy>;
56                         phy-names = "usb2-phy";
57                         dr_mode = "host";
58                         status = "disabled";
59                 };
60         };
61 };
62
63 &aobus {
64         pinctrl_aobus: pinctrl@14 {
65                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66                 #address-cells = <2>;
67                 #size-cells = <2>;
68                 ranges;
69
70                 gpio_ao: bank@14 {
71                         reg = <0x0 0x00014 0x0 0x8>,
72                               <0x0 0x0002c 0x0 0x4>,
73                               <0x0 0x00024 0x0 0x8>;
74                         reg-names = "mux", "pull", "gpio";
75                         gpio-controller;
76                         #gpio-cells = <2>;
77                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
78                 };
79
80                 uart_ao_a_pins: uart_ao_a {
81                         mux {
82                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
83                                 function = "uart_ao";
84                         };
85                 };
86
87                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
88                         mux {
89                                 groups = "uart_cts_ao_a",
90                                        "uart_rts_ao_a";
91                                 function = "uart_ao";
92                         };
93                 };
94
95                 uart_ao_b_pins: uart_ao_b {
96                         mux {
97                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
98                                 function = "uart_ao_b";
99                         };
100                 };
101
102                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
103                         mux {
104                                 groups = "uart_cts_ao_b",
105                                        "uart_rts_ao_b";
106                                 function = "uart_ao_b";
107                         };
108                 };
109
110                 remote_input_ao_pins: remote_input_ao {
111                         mux {
112                                 groups = "remote_input_ao";
113                                 function = "remote_input_ao";
114                         };
115                 };
116
117                 i2c_ao_pins: i2c_ao {
118                         mux {
119                                 groups = "i2c_sck_ao",
120                                        "i2c_sda_ao";
121                                 function = "i2c_ao";
122                         };
123                 };
124
125                 pwm_ao_a_3_pins: pwm_ao_a_3 {
126                         mux {
127                                 groups = "pwm_ao_a_3";
128                                 function = "pwm_ao_a_3";
129                         };
130                 };
131
132                 pwm_ao_a_6_pins: pwm_ao_a_6 {
133                         mux {
134                                 groups = "pwm_ao_a_6";
135                                 function = "pwm_ao_a_6";
136                         };
137                 };
138
139                 pwm_ao_a_12_pins: pwm_ao_a_12 {
140                         mux {
141                                 groups = "pwm_ao_a_12";
142                                 function = "pwm_ao_a_12";
143                         };
144                 };
145
146                 pwm_ao_b_pins: pwm_ao_b {
147                         mux {
148                                 groups = "pwm_ao_b";
149                                 function = "pwm_ao_b";
150                         };
151                 };
152
153                 i2s_am_clk_pins: i2s_am_clk {
154                         mux {
155                                 groups = "i2s_am_clk";
156                                 function = "i2s_out_ao";
157                         };
158                 };
159
160                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
161                         mux {
162                                 groups = "i2s_out_ao_clk";
163                                 function = "i2s_out_ao";
164                         };
165                 };
166
167                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
168                         mux {
169                                 groups = "i2s_out_lr_clk";
170                                 function = "i2s_out_ao";
171                         };
172                 };
173
174                 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
175                         mux {
176                                 groups = "i2s_out_ch01_ao";
177                                 function = "i2s_out_ao";
178                         };
179                 };
180
181                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
182                         mux {
183                                 groups = "i2s_out_ch23_ao";
184                                 function = "i2s_out_ao";
185                         };
186                 };
187
188                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
189                         mux {
190                                 groups = "i2s_out_ch45_ao";
191                                 function = "i2s_out_ao";
192                         };
193                 };
194
195                 spdif_out_ao_6_pins: spdif_out_ao_6 {
196                         mux {
197                                 groups = "spdif_out_ao_6";
198                                 function = "spdif_out_ao";
199                         };
200                 };
201
202                 spdif_out_ao_13_pins: spdif_out_ao_13 {
203                         mux {
204                                 groups = "spdif_out_ao_13";
205                                 function = "spdif_out_ao";
206                         };
207                 };
208
209                 ao_cec_pins: ao_cec {
210                         mux {
211                                 groups = "ao_cec";
212                                 function = "cec_ao";
213                         };
214                 };
215
216                 ee_cec_pins: ee_cec {
217                         mux {
218                                 groups = "ee_cec";
219                                 function = "cec_ao";
220                         };
221                 };
222         };
223 };
224
225 &apb {
226         mali: gpu@c0000 {
227                 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
228                 reg = <0x0 0xc0000 0x0 0x40000>;
229                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
231                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
232                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
233                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
234                              <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
235                              <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
236                              <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
237                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
239                 interrupt-names = "gp", "gpmmu", "pp", "pmu",
240                         "pp0", "ppmmu0", "pp1", "ppmmu1",
241                         "pp2", "ppmmu2";
242                 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243                 clock-names = "bus", "core";
244
245                 /*
246                  * Mali clocking is provided by two identical clock paths
247                  * MALI_0 and MALI_1 muxed to a single clock by a glitch
248                  * free mux to safely change frequency while running.
249                  */
250                 assigned-clocks = <&clkc CLKID_GP0_PLL>,
251                                   <&clkc CLKID_MALI_0_SEL>,
252                                   <&clkc CLKID_MALI_0>,
253                                   <&clkc CLKID_MALI>; /* Glitch free mux */
254                 assigned-clock-parents = <0>, /* Do Nothing */
255                                          <&clkc CLKID_GP0_PLL>,
256                                          <0>, /* Do Nothing */
257                                          <&clkc CLKID_MALI_0>;
258                 assigned-clock-rates = <744000000>,
259                                        <0>, /* Do Nothing */
260                                        <744000000>,
261                                        <0>; /* Do Nothing */
262         };
263 };
264
265 &cbus {
266         spifc: spi@8c80 {
267                 compatible = "amlogic,meson-gxbb-spifc";
268                 reg = <0x0 0x08c80 0x0 0x80>;
269                 #address-cells = <1>;
270                 #size-cells = <0>;
271                 clocks = <&clkc CLKID_SPI>;
272                 status = "disabled";
273         };
274 };
275
276 &cec_AO {
277         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
278         clock-names = "core";
279 };
280
281 &clkc_AO {
282         compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
283 };
284
285 &efuse {
286         clocks = <&clkc CLKID_EFUSE>;
287 };
288
289 &ethmac {
290         clocks = <&clkc CLKID_ETH>,
291                  <&clkc CLKID_FCLK_DIV2>,
292                  <&clkc CLKID_MPLL2>;
293         clock-names = "stmmaceth", "clkin0", "clkin1";
294 };
295
296 &gpio_intc {
297         compatible = "amlogic,meson-gpio-intc",
298                      "amlogic,meson-gxbb-gpio-intc";
299         status = "okay";
300 };
301
302 &hdmi_tx {
303         compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
304         resets = <&reset RESET_HDMITX_CAPB3>,
305                  <&reset RESET_HDMI_SYSTEM_RESET>,
306                  <&reset RESET_HDMI_TX>;
307         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
308         clocks = <&clkc CLKID_HDMI_PCLK>,
309                  <&clkc CLKID_CLK81>,
310                  <&clkc CLKID_GCLK_VENCI_INT0>;
311         clock-names = "isfr", "iahb", "venci";
312 };
313
314 &sysctrl {
315         clkc: clock-controller {
316                 compatible = "amlogic,gxbb-clkc";
317                 #clock-cells = <1>;
318         };
319 };
320
321 &hwrng {
322         clocks = <&clkc CLKID_RNG0>;
323         clock-names = "core";
324 };
325
326 &i2c_A {
327         clocks = <&clkc CLKID_I2C>;
328 };
329
330 &i2c_AO {
331         clocks = <&clkc CLKID_AO_I2C>;
332 };
333
334 &i2c_B {
335         clocks = <&clkc CLKID_I2C>;
336 };
337
338 &i2c_C {
339         clocks = <&clkc CLKID_I2C>;
340 };
341
342 &periphs {
343         pinctrl_periphs: pinctrl@4b0 {
344                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
345                 #address-cells = <2>;
346                 #size-cells = <2>;
347                 ranges;
348
349                 gpio: bank@4b0 {
350                         reg = <0x0 0x004b0 0x0 0x28>,
351                               <0x0 0x004e8 0x0 0x14>,
352                               <0x0 0x00520 0x0 0x14>,
353                               <0x0 0x00430 0x0 0x40>;
354                         reg-names = "mux", "pull", "pull-enable", "gpio";
355                         gpio-controller;
356                         #gpio-cells = <2>;
357                         gpio-ranges = <&pinctrl_periphs 0 0 119>;
358                 };
359
360                 emmc_pins: emmc {
361                         mux {
362                                 groups = "emmc_nand_d07",
363                                        "emmc_cmd",
364                                        "emmc_clk";
365                                 function = "emmc";
366                         };
367                 };
368
369                 emmc_ds_pins: emmc-ds {
370                         mux {
371                                 groups = "emmc_ds";
372                                 function = "emmc";
373                         };
374                 };
375
376                 emmc_clk_gate_pins: emmc_clk_gate {
377                         mux {
378                                 groups = "BOOT_8";
379                                 function = "gpio_periphs";
380                                 bias-pull-down;
381                         };
382                 };
383
384                 nor_pins: nor {
385                         mux {
386                                 groups = "nor_d",
387                                        "nor_q",
388                                        "nor_c",
389                                        "nor_cs";
390                                 function = "nor";
391                         };
392                 };
393
394                 spi_pins: spi-pins {
395                         mux {
396                                 groups = "spi_miso",
397                                         "spi_mosi",
398                                         "spi_sclk";
399                                 function = "spi";
400                         };
401                 };
402
403                 spi_ss0_pins: spi-ss0 {
404                         mux {
405                                 groups = "spi_ss0";
406                                 function = "spi";
407                         };
408                 };
409
410                 sdcard_pins: sdcard {
411                         mux {
412                                 groups = "sdcard_d0",
413                                        "sdcard_d1",
414                                        "sdcard_d2",
415                                        "sdcard_d3",
416                                        "sdcard_cmd",
417                                        "sdcard_clk";
418                                 function = "sdcard";
419                         };
420                 };
421
422                 sdcard_clk_gate_pins: sdcard_clk_gate {
423                         mux {
424                                 groups = "CARD_2";
425                                 function = "gpio_periphs";
426                                 bias-pull-down;
427                         };
428                 };
429
430                 sdio_pins: sdio {
431                         mux {
432                                 groups = "sdio_d0",
433                                        "sdio_d1",
434                                        "sdio_d2",
435                                        "sdio_d3",
436                                        "sdio_cmd",
437                                        "sdio_clk";
438                                 function = "sdio";
439                         };
440                 };
441
442                 sdio_clk_gate_pins: sdio_clk_gate {
443                         mux {
444                                 groups = "GPIOX_4";
445                                 function = "gpio_periphs";
446                                 bias-pull-down;
447                         };
448                 };
449
450                 sdio_irq_pins: sdio_irq {
451                         mux {
452                                 groups = "sdio_irq";
453                                 function = "sdio";
454                         };
455                 };
456
457                 uart_a_pins: uart_a {
458                         mux {
459                                 groups = "uart_tx_a",
460                                        "uart_rx_a";
461                                 function = "uart_a";
462                         };
463                 };
464
465                 uart_a_cts_rts_pins: uart_a_cts_rts {
466                         mux {
467                                 groups = "uart_cts_a",
468                                        "uart_rts_a";
469                                 function = "uart_a";
470                         };
471                 };
472
473                 uart_b_pins: uart_b {
474                         mux {
475                                 groups = "uart_tx_b",
476                                        "uart_rx_b";
477                                 function = "uart_b";
478                         };
479                 };
480
481                 uart_b_cts_rts_pins: uart_b_cts_rts {
482                         mux {
483                                 groups = "uart_cts_b",
484                                        "uart_rts_b";
485                                 function = "uart_b";
486                         };
487                 };
488
489                 uart_c_pins: uart_c {
490                         mux {
491                                 groups = "uart_tx_c",
492                                        "uart_rx_c";
493                                 function = "uart_c";
494                         };
495                 };
496
497                 uart_c_cts_rts_pins: uart_c_cts_rts {
498                         mux {
499                                 groups = "uart_cts_c",
500                                        "uart_rts_c";
501                                 function = "uart_c";
502                         };
503                 };
504
505                 i2c_a_pins: i2c_a {
506                         mux {
507                                 groups = "i2c_sck_a",
508                                        "i2c_sda_a";
509                                 function = "i2c_a";
510                         };
511                 };
512
513                 i2c_b_pins: i2c_b {
514                         mux {
515                                 groups = "i2c_sck_b",
516                                        "i2c_sda_b";
517                                 function = "i2c_b";
518                         };
519                 };
520
521                 i2c_c_pins: i2c_c {
522                         mux {
523                                 groups = "i2c_sck_c",
524                                        "i2c_sda_c";
525                                 function = "i2c_c";
526                         };
527                 };
528
529                 eth_rgmii_pins: eth-rgmii {
530                         mux {
531                                 groups = "eth_mdio",
532                                        "eth_mdc",
533                                        "eth_clk_rx_clk",
534                                        "eth_rx_dv",
535                                        "eth_rxd0",
536                                        "eth_rxd1",
537                                        "eth_rxd2",
538                                        "eth_rxd3",
539                                        "eth_rgmii_tx_clk",
540                                        "eth_tx_en",
541                                        "eth_txd0",
542                                        "eth_txd1",
543                                        "eth_txd2",
544                                        "eth_txd3";
545                                 function = "eth";
546                         };
547                 };
548
549                 eth_rmii_pins: eth-rmii {
550                         mux {
551                                 groups = "eth_mdio",
552                                        "eth_mdc",
553                                        "eth_clk_rx_clk",
554                                        "eth_rx_dv",
555                                        "eth_rxd0",
556                                        "eth_rxd1",
557                                        "eth_tx_en",
558                                        "eth_txd0",
559                                        "eth_txd1";
560                                 function = "eth";
561                         };
562                 };
563
564                 pwm_a_x_pins: pwm_a_x {
565                         mux {
566                                 groups = "pwm_a_x";
567                                 function = "pwm_a_x";
568                         };
569                 };
570
571                 pwm_a_y_pins: pwm_a_y {
572                         mux {
573                                 groups = "pwm_a_y";
574                                 function = "pwm_a_y";
575                         };
576                 };
577
578                 pwm_b_pins: pwm_b {
579                         mux {
580                                 groups = "pwm_b";
581                                 function = "pwm_b";
582                         };
583                 };
584
585                 pwm_d_pins: pwm_d {
586                         mux {
587                                 groups = "pwm_d";
588                                 function = "pwm_d";
589                         };
590                 };
591
592                 pwm_e_pins: pwm_e {
593                         mux {
594                                 groups = "pwm_e";
595                                 function = "pwm_e";
596                         };
597                 };
598
599                 pwm_f_x_pins: pwm_f_x {
600                         mux {
601                                 groups = "pwm_f_x";
602                                 function = "pwm_f_x";
603                         };
604                 };
605
606                 pwm_f_y_pins: pwm_f_y {
607                         mux {
608                                 groups = "pwm_f_y";
609                                 function = "pwm_f_y";
610                         };
611                 };
612
613                 hdmi_hpd_pins: hdmi_hpd {
614                         mux {
615                                 groups = "hdmi_hpd";
616                                 function = "hdmi_hpd";
617                         };
618                 };
619
620                 hdmi_i2c_pins: hdmi_i2c {
621                         mux {
622                                 groups = "hdmi_sda", "hdmi_scl";
623                                 function = "hdmi_i2c";
624                         };
625                 };
626
627                 i2sout_ch23_y_pins: i2sout_ch23_y {
628                         mux {
629                                 groups = "i2sout_ch23_y";
630                                 function = "i2s_out";
631                         };
632                 };
633
634                 i2sout_ch45_y_pins: i2sout_ch45_y {
635                         mux {
636                                 groups = "i2sout_ch45_y";
637                                 function = "i2s_out";
638                         };
639                 };
640
641                 i2sout_ch67_y_pins: i2sout_ch67_y {
642                         mux {
643                                 groups = "i2sout_ch67_y";
644                                 function = "i2s_out";
645                         };
646                 };
647
648                 spdif_out_y_pins: spdif_out_y {
649                         mux {
650                                 groups = "spdif_out_y";
651                                 function = "spdif_out";
652                         };
653                 };
654         };
655 };
656
657 &pwrc_vpu {
658         resets = <&reset RESET_VIU>,
659                  <&reset RESET_VENC>,
660                  <&reset RESET_VCBUS>,
661                  <&reset RESET_BT656>,
662                  <&reset RESET_DVIN_RESET>,
663                  <&reset RESET_RDMA>,
664                  <&reset RESET_VENCI>,
665                  <&reset RESET_VENCP>,
666                  <&reset RESET_VDAC>,
667                  <&reset RESET_VDI6>,
668                  <&reset RESET_VENCL>,
669                  <&reset RESET_VID_LOCK>;
670         clocks = <&clkc CLKID_VPU>,
671                  <&clkc CLKID_VAPB>;
672         clock-names = "vpu", "vapb";
673         /*
674          * VPU clocking is provided by two identical clock paths
675          * VPU_0 and VPU_1 muxed to a single clock by a glitch
676          * free mux to safely change frequency while running.
677          * Same for VAPB but with a final gate after the glitch free mux.
678          */
679         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
680                           <&clkc CLKID_VPU_0>,
681                           <&clkc CLKID_VPU>, /* Glitch free mux */
682                           <&clkc CLKID_VAPB_0_SEL>,
683                           <&clkc CLKID_VAPB_0>,
684                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
685         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
686                                  <0>, /* Do Nothing */
687                                  <&clkc CLKID_VPU_0>,
688                                  <&clkc CLKID_FCLK_DIV4>,
689                                  <0>, /* Do Nothing */
690                                  <&clkc CLKID_VAPB_0>;
691         assigned-clock-rates = <0>, /* Do Nothing */
692                                <666666666>,
693                                <0>, /* Do Nothing */
694                                <0>, /* Do Nothing */
695                                <250000000>,
696                                <0>; /* Do Nothing */
697 };
698
699 &saradc {
700         compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
701         clocks = <&xtal>,
702                  <&clkc CLKID_SAR_ADC>,
703                  <&clkc CLKID_SAR_ADC_CLK>,
704                  <&clkc CLKID_SAR_ADC_SEL>;
705         clock-names = "clkin", "core", "adc_clk", "adc_sel";
706 };
707
708 &sd_emmc_a {
709         clocks = <&clkc CLKID_SD_EMMC_A>,
710                  <&clkc CLKID_SD_EMMC_A_CLK0>,
711                  <&clkc CLKID_FCLK_DIV2>;
712         clock-names = "core", "clkin0", "clkin1";
713         resets = <&reset RESET_SD_EMMC_A>;
714 };
715
716 &sd_emmc_b {
717         clocks = <&clkc CLKID_SD_EMMC_B>,
718                  <&clkc CLKID_SD_EMMC_B_CLK0>,
719                  <&clkc CLKID_FCLK_DIV2>;
720         clock-names = "core", "clkin0", "clkin1";
721         resets = <&reset RESET_SD_EMMC_B>;
722 };
723
724 &sd_emmc_c {
725         clocks = <&clkc CLKID_SD_EMMC_C>,
726                  <&clkc CLKID_SD_EMMC_C_CLK0>,
727                  <&clkc CLKID_FCLK_DIV2>;
728         clock-names = "core", "clkin0", "clkin1";
729         resets = <&reset RESET_SD_EMMC_C>;
730 };
731
732 &spicc {
733         clocks = <&clkc CLKID_SPICC>;
734         clock-names = "core";
735         resets = <&reset RESET_PERIPHS_SPICC>;
736         num-cs = <1>;
737 };
738
739 &spifc {
740         clocks = <&clkc CLKID_SPI>;
741 };
742
743 &uart_A {
744         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
745         clock-names = "xtal", "pclk", "baud";
746 };
747
748 &uart_AO {
749         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
750         clock-names = "xtal", "pclk", "baud";
751 };
752
753 &uart_AO_B {
754         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
755         clock-names = "xtal", "pclk", "baud";
756 };
757
758 &uart_B {
759         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
760         clock-names = "xtal", "pclk", "baud";
761 };
762
763 &uart_C {
764         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
765         clock-names = "xtal", "pclk", "baud";
766 };
767
768 &vpu {
769         compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
770         power-domains = <&pwrc_vpu>;
771 };