524f533e41d4825b027feb77aba6a6df5463f178
[muen/linux.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2016 Andreas Färber
4  */
5
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
12
13 / {
14         compatible = "amlogic,meson-gxbb";
15
16         soc {
17                 usb0_phy: phy@c0000000 {
18                         compatible = "amlogic,meson-gxbb-usb2-phy";
19                         #phy-cells = <0>;
20                         reg = <0x0 0xc0000000 0x0 0x20>;
21                         resets = <&reset RESET_USB_OTG>;
22                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23                         clock-names = "usb_general", "usb";
24                         status = "disabled";
25                 };
26
27                 usb1_phy: phy@c0000020 {
28                         compatible = "amlogic,meson-gxbb-usb2-phy";
29                         #phy-cells = <0>;
30                         reg = <0x0 0xc0000020 0x0 0x20>;
31                         resets = <&reset RESET_USB_OTG>;
32                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33                         clock-names = "usb_general", "usb";
34                         status = "disabled";
35                 };
36
37                 usb0: usb@c9000000 {
38                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39                         reg = <0x0 0xc9000000 0x0 0x40000>;
40                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41                         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42                         clock-names = "otg";
43                         phys = <&usb0_phy>;
44                         phy-names = "usb2-phy";
45                         dr_mode = "host";
46                         status = "disabled";
47                 };
48
49                 usb1: usb@c9100000 {
50                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51                         reg = <0x0 0xc9100000 0x0 0x40000>;
52                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53                         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54                         clock-names = "otg";
55                         phys = <&usb1_phy>;
56                         phy-names = "usb2-phy";
57                         dr_mode = "host";
58                         status = "disabled";
59                 };
60         };
61 };
62
63 &aobus {
64         pinctrl_aobus: pinctrl@14 {
65                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66                 #address-cells = <2>;
67                 #size-cells = <2>;
68                 ranges;
69
70                 gpio_ao: bank@14 {
71                         reg = <0x0 0x00014 0x0 0x8>,
72                               <0x0 0x0002c 0x0 0x4>,
73                               <0x0 0x00024 0x0 0x8>;
74                         reg-names = "mux", "pull", "gpio";
75                         gpio-controller;
76                         #gpio-cells = <2>;
77                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
78                 };
79
80                 uart_ao_a_pins: uart_ao_a {
81                         mux {
82                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
83                                 function = "uart_ao";
84                         };
85                 };
86
87                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
88                         mux {
89                                 groups = "uart_cts_ao_a",
90                                        "uart_rts_ao_a";
91                                 function = "uart_ao";
92                         };
93                 };
94
95                 uart_ao_b_pins: uart_ao_b {
96                         mux {
97                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
98                                 function = "uart_ao_b";
99                         };
100                 };
101
102                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
103                         mux {
104                                 groups = "uart_cts_ao_b",
105                                        "uart_rts_ao_b";
106                                 function = "uart_ao_b";
107                         };
108                 };
109
110                 remote_input_ao_pins: remote_input_ao {
111                         mux {
112                                 groups = "remote_input_ao";
113                                 function = "remote_input_ao";
114                         };
115                 };
116
117                 i2c_ao_pins: i2c_ao {
118                         mux {
119                                 groups = "i2c_sck_ao",
120                                        "i2c_sda_ao";
121                                 function = "i2c_ao";
122                         };
123                 };
124
125                 pwm_ao_a_3_pins: pwm_ao_a_3 {
126                         mux {
127                                 groups = "pwm_ao_a_3";
128                                 function = "pwm_ao_a_3";
129                         };
130                 };
131
132                 pwm_ao_a_6_pins: pwm_ao_a_6 {
133                         mux {
134                                 groups = "pwm_ao_a_6";
135                                 function = "pwm_ao_a_6";
136                         };
137                 };
138
139                 pwm_ao_a_12_pins: pwm_ao_a_12 {
140                         mux {
141                                 groups = "pwm_ao_a_12";
142                                 function = "pwm_ao_a_12";
143                         };
144                 };
145
146                 pwm_ao_b_pins: pwm_ao_b {
147                         mux {
148                                 groups = "pwm_ao_b";
149                                 function = "pwm_ao_b";
150                         };
151                 };
152
153                 i2s_am_clk_pins: i2s_am_clk {
154                         mux {
155                                 groups = "i2s_am_clk";
156                                 function = "i2s_out_ao";
157                         };
158                 };
159
160                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
161                         mux {
162                                 groups = "i2s_out_ao_clk";
163                                 function = "i2s_out_ao";
164                         };
165                 };
166
167                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
168                         mux {
169                                 groups = "i2s_out_lr_clk";
170                                 function = "i2s_out_ao";
171                         };
172                 };
173
174                 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
175                         mux {
176                                 groups = "i2s_out_ch01_ao";
177                                 function = "i2s_out_ao";
178                         };
179                 };
180
181                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
182                         mux {
183                                 groups = "i2s_out_ch23_ao";
184                                 function = "i2s_out_ao";
185                         };
186                 };
187
188                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
189                         mux {
190                                 groups = "i2s_out_ch45_ao";
191                                 function = "i2s_out_ao";
192                         };
193                 };
194
195                 spdif_out_ao_6_pins: spdif_out_ao_6 {
196                         mux {
197                                 groups = "spdif_out_ao_6";
198                                 function = "spdif_out_ao";
199                         };
200                 };
201
202                 spdif_out_ao_13_pins: spdif_out_ao_13 {
203                         mux {
204                                 groups = "spdif_out_ao_13";
205                                 function = "spdif_out_ao";
206                         };
207                 };
208
209                 ao_cec_pins: ao_cec {
210                         mux {
211                                 groups = "ao_cec";
212                                 function = "cec_ao";
213                         };
214                 };
215
216                 ee_cec_pins: ee_cec {
217                         mux {
218                                 groups = "ee_cec";
219                                 function = "cec_ao";
220                         };
221                 };
222         };
223 };
224
225 &apb {
226         mali: gpu@c0000 {
227                 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
228                 reg = <0x0 0xc0000 0x0 0x40000>;
229                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
231                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
232                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
233                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
234                              <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
235                              <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
236                              <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
237                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
239                 interrupt-names = "gp", "gpmmu", "pp", "pmu",
240                         "pp0", "ppmmu0", "pp1", "ppmmu1",
241                         "pp2", "ppmmu2";
242                 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243                 clock-names = "bus", "core";
244
245                 /*
246                  * Mali clocking is provided by two identical clock paths
247                  * MALI_0 and MALI_1 muxed to a single clock by a glitch
248                  * free mux to safely change frequency while running.
249                  */
250                 assigned-clocks = <&clkc CLKID_GP0_PLL>,
251                                   <&clkc CLKID_MALI_0_SEL>,
252                                   <&clkc CLKID_MALI_0>,
253                                   <&clkc CLKID_MALI>; /* Glitch free mux */
254                 assigned-clock-parents = <0>, /* Do Nothing */
255                                          <&clkc CLKID_GP0_PLL>,
256                                          <0>, /* Do Nothing */
257                                          <&clkc CLKID_MALI_0>;
258                 assigned-clock-rates = <744000000>,
259                                        <0>, /* Do Nothing */
260                                        <744000000>,
261                                        <0>; /* Do Nothing */
262         };
263 };
264
265 &cbus {
266         spifc: spi@8c80 {
267                 compatible = "amlogic,meson-gxbb-spifc";
268                 reg = <0x0 0x08c80 0x0 0x80>;
269                 #address-cells = <1>;
270                 #size-cells = <0>;
271                 clocks = <&clkc CLKID_SPI>;
272                 status = "disabled";
273         };
274 };
275
276 &cec_AO {
277         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
278         clock-names = "core";
279 };
280
281 &clkc_AO {
282         compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
283 };
284
285 &efuse {
286         clocks = <&clkc CLKID_EFUSE>;
287 };
288
289 &ethmac {
290         clocks = <&clkc CLKID_ETH>,
291                  <&clkc CLKID_FCLK_DIV2>,
292                  <&clkc CLKID_MPLL2>;
293         clock-names = "stmmaceth", "clkin0", "clkin1";
294 };
295
296 &gpio_intc {
297         compatible = "amlogic,meson-gpio-intc",
298                      "amlogic,meson-gxbb-gpio-intc";
299         status = "okay";
300 };
301
302 &hdmi_tx {
303         compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
304         resets = <&reset RESET_HDMITX_CAPB3>,
305                  <&reset RESET_HDMI_SYSTEM_RESET>,
306                  <&reset RESET_HDMI_TX>;
307         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
308         clocks = <&clkc CLKID_HDMI_PCLK>,
309                  <&clkc CLKID_CLK81>,
310                  <&clkc CLKID_GCLK_VENCI_INT0>;
311         clock-names = "isfr", "iahb", "venci";
312 };
313
314 &sysctrl {
315         clkc: clock-controller {
316                 compatible = "amlogic,gxbb-clkc";
317                 #clock-cells = <1>;
318         };
319 };
320
321 &hwrng {
322         clocks = <&clkc CLKID_RNG0>;
323         clock-names = "core";
324 };
325
326 &i2c_A {
327         clocks = <&clkc CLKID_I2C>;
328 };
329
330 &i2c_AO {
331         clocks = <&clkc CLKID_AO_I2C>;
332 };
333
334 &i2c_B {
335         clocks = <&clkc CLKID_I2C>;
336 };
337
338 &i2c_C {
339         clocks = <&clkc CLKID_I2C>;
340 };
341
342 &periphs {
343         pinctrl_periphs: pinctrl@4b0 {
344                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
345                 #address-cells = <2>;
346                 #size-cells = <2>;
347                 ranges;
348
349                 gpio: bank@4b0 {
350                         reg = <0x0 0x004b0 0x0 0x28>,
351                               <0x0 0x004e8 0x0 0x14>,
352                               <0x0 0x00520 0x0 0x14>,
353                               <0x0 0x00430 0x0 0x40>;
354                         reg-names = "mux", "pull", "pull-enable", "gpio";
355                         gpio-controller;
356                         #gpio-cells = <2>;
357                         gpio-ranges = <&pinctrl_periphs 0 0 119>;
358                 };
359
360                 emmc_pins: emmc {
361                         mux {
362                                 groups = "emmc_nand_d07",
363                                        "emmc_cmd",
364                                        "emmc_clk";
365                                 function = "emmc";
366                         };
367                 };
368
369                 emmc_ds_pins: emmc-ds {
370                         mux {
371                                 groups = "emmc_ds";
372                                 function = "emmc";
373                         };
374                 };
375
376                 emmc_clk_gate_pins: emmc_clk_gate {
377                         mux {
378                                 groups = "BOOT_8";
379                                 function = "gpio_periphs";
380                         };
381                         cfg-pull-down {
382                                 pins = "BOOT_8";
383                                 bias-pull-down;
384                         };
385                 };
386
387                 nor_pins: nor {
388                         mux {
389                                 groups = "nor_d",
390                                        "nor_q",
391                                        "nor_c",
392                                        "nor_cs";
393                                 function = "nor";
394                         };
395                 };
396
397                 spi_pins: spi-pins {
398                         mux {
399                                 groups = "spi_miso",
400                                         "spi_mosi",
401                                         "spi_sclk";
402                                 function = "spi";
403                         };
404                 };
405
406                 spi_ss0_pins: spi-ss0 {
407                         mux {
408                                 groups = "spi_ss0";
409                                 function = "spi";
410                         };
411                 };
412
413                 sdcard_pins: sdcard {
414                         mux {
415                                 groups = "sdcard_d0",
416                                        "sdcard_d1",
417                                        "sdcard_d2",
418                                        "sdcard_d3",
419                                        "sdcard_cmd",
420                                        "sdcard_clk";
421                                 function = "sdcard";
422                         };
423                 };
424
425                 sdcard_clk_gate_pins: sdcard_clk_gate {
426                         mux {
427                                 groups = "CARD_2";
428                                 function = "gpio_periphs";
429                         };
430                         cfg-pull-down {
431                                 pins = "CARD_2";
432                                 bias-pull-down;
433                         };
434                 };
435
436                 sdio_pins: sdio {
437                         mux {
438                                 groups = "sdio_d0",
439                                        "sdio_d1",
440                                        "sdio_d2",
441                                        "sdio_d3",
442                                        "sdio_cmd",
443                                        "sdio_clk";
444                                 function = "sdio";
445                         };
446                 };
447
448                 sdio_clk_gate_pins: sdio_clk_gate {
449                         mux {
450                                 groups = "GPIOX_4";
451                                 function = "gpio_periphs";
452                         };
453                         cfg-pull-down {
454                                 pins = "GPIOX_4";
455                                 bias-pull-down;
456                         };
457                 };
458
459                 sdio_irq_pins: sdio_irq {
460                         mux {
461                                 groups = "sdio_irq";
462                                 function = "sdio";
463                         };
464                 };
465
466                 uart_a_pins: uart_a {
467                         mux {
468                                 groups = "uart_tx_a",
469                                        "uart_rx_a";
470                                 function = "uart_a";
471                         };
472                 };
473
474                 uart_a_cts_rts_pins: uart_a_cts_rts {
475                         mux {
476                                 groups = "uart_cts_a",
477                                        "uart_rts_a";
478                                 function = "uart_a";
479                         };
480                 };
481
482                 uart_b_pins: uart_b {
483                         mux {
484                                 groups = "uart_tx_b",
485                                        "uart_rx_b";
486                                 function = "uart_b";
487                         };
488                 };
489
490                 uart_b_cts_rts_pins: uart_b_cts_rts {
491                         mux {
492                                 groups = "uart_cts_b",
493                                        "uart_rts_b";
494                                 function = "uart_b";
495                         };
496                 };
497
498                 uart_c_pins: uart_c {
499                         mux {
500                                 groups = "uart_tx_c",
501                                        "uart_rx_c";
502                                 function = "uart_c";
503                         };
504                 };
505
506                 uart_c_cts_rts_pins: uart_c_cts_rts {
507                         mux {
508                                 groups = "uart_cts_c",
509                                        "uart_rts_c";
510                                 function = "uart_c";
511                         };
512                 };
513
514                 i2c_a_pins: i2c_a {
515                         mux {
516                                 groups = "i2c_sck_a",
517                                        "i2c_sda_a";
518                                 function = "i2c_a";
519                         };
520                 };
521
522                 i2c_b_pins: i2c_b {
523                         mux {
524                                 groups = "i2c_sck_b",
525                                        "i2c_sda_b";
526                                 function = "i2c_b";
527                         };
528                 };
529
530                 i2c_c_pins: i2c_c {
531                         mux {
532                                 groups = "i2c_sck_c",
533                                        "i2c_sda_c";
534                                 function = "i2c_c";
535                         };
536                 };
537
538                 eth_rgmii_pins: eth-rgmii {
539                         mux {
540                                 groups = "eth_mdio",
541                                        "eth_mdc",
542                                        "eth_clk_rx_clk",
543                                        "eth_rx_dv",
544                                        "eth_rxd0",
545                                        "eth_rxd1",
546                                        "eth_rxd2",
547                                        "eth_rxd3",
548                                        "eth_rgmii_tx_clk",
549                                        "eth_tx_en",
550                                        "eth_txd0",
551                                        "eth_txd1",
552                                        "eth_txd2",
553                                        "eth_txd3";
554                                 function = "eth";
555                         };
556                 };
557
558                 eth_rmii_pins: eth-rmii {
559                         mux {
560                                 groups = "eth_mdio",
561                                        "eth_mdc",
562                                        "eth_clk_rx_clk",
563                                        "eth_rx_dv",
564                                        "eth_rxd0",
565                                        "eth_rxd1",
566                                        "eth_tx_en",
567                                        "eth_txd0",
568                                        "eth_txd1";
569                                 function = "eth";
570                         };
571                 };
572
573                 pwm_a_x_pins: pwm_a_x {
574                         mux {
575                                 groups = "pwm_a_x";
576                                 function = "pwm_a_x";
577                         };
578                 };
579
580                 pwm_a_y_pins: pwm_a_y {
581                         mux {
582                                 groups = "pwm_a_y";
583                                 function = "pwm_a_y";
584                         };
585                 };
586
587                 pwm_b_pins: pwm_b {
588                         mux {
589                                 groups = "pwm_b";
590                                 function = "pwm_b";
591                         };
592                 };
593
594                 pwm_d_pins: pwm_d {
595                         mux {
596                                 groups = "pwm_d";
597                                 function = "pwm_d";
598                         };
599                 };
600
601                 pwm_e_pins: pwm_e {
602                         mux {
603                                 groups = "pwm_e";
604                                 function = "pwm_e";
605                         };
606                 };
607
608                 pwm_f_x_pins: pwm_f_x {
609                         mux {
610                                 groups = "pwm_f_x";
611                                 function = "pwm_f_x";
612                         };
613                 };
614
615                 pwm_f_y_pins: pwm_f_y {
616                         mux {
617                                 groups = "pwm_f_y";
618                                 function = "pwm_f_y";
619                         };
620                 };
621
622                 hdmi_hpd_pins: hdmi_hpd {
623                         mux {
624                                 groups = "hdmi_hpd";
625                                 function = "hdmi_hpd";
626                         };
627                 };
628
629                 hdmi_i2c_pins: hdmi_i2c {
630                         mux {
631                                 groups = "hdmi_sda", "hdmi_scl";
632                                 function = "hdmi_i2c";
633                         };
634                 };
635
636                 i2sout_ch23_y_pins: i2sout_ch23_y {
637                         mux {
638                                 groups = "i2sout_ch23_y";
639                                 function = "i2s_out";
640                         };
641                 };
642
643                 i2sout_ch45_y_pins: i2sout_ch45_y {
644                         mux {
645                                 groups = "i2sout_ch45_y";
646                                 function = "i2s_out";
647                         };
648                 };
649
650                 i2sout_ch67_y_pins: i2sout_ch67_y {
651                         mux {
652                                 groups = "i2sout_ch67_y";
653                                 function = "i2s_out";
654                         };
655                 };
656
657                 spdif_out_y_pins: spdif_out_y {
658                         mux {
659                                 groups = "spdif_out_y";
660                                 function = "spdif_out";
661                         };
662                 };
663         };
664 };
665
666 &pwrc_vpu {
667         resets = <&reset RESET_VIU>,
668                  <&reset RESET_VENC>,
669                  <&reset RESET_VCBUS>,
670                  <&reset RESET_BT656>,
671                  <&reset RESET_DVIN_RESET>,
672                  <&reset RESET_RDMA>,
673                  <&reset RESET_VENCI>,
674                  <&reset RESET_VENCP>,
675                  <&reset RESET_VDAC>,
676                  <&reset RESET_VDI6>,
677                  <&reset RESET_VENCL>,
678                  <&reset RESET_VID_LOCK>;
679         clocks = <&clkc CLKID_VPU>,
680                  <&clkc CLKID_VAPB>;
681         clock-names = "vpu", "vapb";
682         /*
683          * VPU clocking is provided by two identical clock paths
684          * VPU_0 and VPU_1 muxed to a single clock by a glitch
685          * free mux to safely change frequency while running.
686          * Same for VAPB but with a final gate after the glitch free mux.
687          */
688         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
689                           <&clkc CLKID_VPU_0>,
690                           <&clkc CLKID_VPU>, /* Glitch free mux */
691                           <&clkc CLKID_VAPB_0_SEL>,
692                           <&clkc CLKID_VAPB_0>,
693                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
694         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
695                                  <0>, /* Do Nothing */
696                                  <&clkc CLKID_VPU_0>,
697                                  <&clkc CLKID_FCLK_DIV4>,
698                                  <0>, /* Do Nothing */
699                                  <&clkc CLKID_VAPB_0>;
700         assigned-clock-rates = <0>, /* Do Nothing */
701                                <666666666>,
702                                <0>, /* Do Nothing */
703                                <0>, /* Do Nothing */
704                                <250000000>,
705                                <0>; /* Do Nothing */
706 };
707
708 &saradc {
709         compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
710         clocks = <&xtal>,
711                  <&clkc CLKID_SAR_ADC>,
712                  <&clkc CLKID_SAR_ADC_CLK>,
713                  <&clkc CLKID_SAR_ADC_SEL>;
714         clock-names = "clkin", "core", "adc_clk", "adc_sel";
715 };
716
717 &sd_emmc_a {
718         clocks = <&clkc CLKID_SD_EMMC_A>,
719                  <&clkc CLKID_SD_EMMC_A_CLK0>,
720                  <&clkc CLKID_FCLK_DIV2>;
721         clock-names = "core", "clkin0", "clkin1";
722         resets = <&reset RESET_SD_EMMC_A>;
723 };
724
725 &sd_emmc_b {
726         clocks = <&clkc CLKID_SD_EMMC_B>,
727                  <&clkc CLKID_SD_EMMC_B_CLK0>,
728                  <&clkc CLKID_FCLK_DIV2>;
729         clock-names = "core", "clkin0", "clkin1";
730         resets = <&reset RESET_SD_EMMC_B>;
731 };
732
733 &sd_emmc_c {
734         clocks = <&clkc CLKID_SD_EMMC_C>,
735                  <&clkc CLKID_SD_EMMC_C_CLK0>,
736                  <&clkc CLKID_FCLK_DIV2>;
737         clock-names = "core", "clkin0", "clkin1";
738         resets = <&reset RESET_SD_EMMC_C>;
739 };
740
741 &spicc {
742         clocks = <&clkc CLKID_SPICC>;
743         clock-names = "core";
744         resets = <&reset RESET_PERIPHS_SPICC>;
745         num-cs = <1>;
746 };
747
748 &spifc {
749         clocks = <&clkc CLKID_SPI>;
750 };
751
752 &uart_A {
753         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
754         clock-names = "xtal", "pclk", "baud";
755 };
756
757 &uart_AO {
758         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
759         clock-names = "xtal", "pclk", "baud";
760 };
761
762 &uart_AO_B {
763         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
764         clock-names = "xtal", "pclk", "baud";
765 };
766
767 &uart_B {
768         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
769         clock-names = "xtal", "pclk", "baud";
770 };
771
772 &uart_C {
773         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
774         clock-names = "xtal", "pclk", "baud";
775 };
776
777 &vpu {
778         compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
779         power-domains = <&pwrc_vpu>;
780 };