arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
[muen/linux.git] / arch / arm64 / boot / dts / amlogic / meson-gxl.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2016 Endless Computers, Inc.
4  * Author: Carlo Caione <carlo@endlessm.com>
5  */
6
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13 / {
14         compatible = "amlogic,meson-gxl";
15
16         soc {
17                 usb0: usb@c9000000 {
18                         status = "disabled";
19                         compatible = "amlogic,meson-gxl-dwc3";
20                         #address-cells = <2>;
21                         #size-cells = <2>;
22                         ranges;
23
24                         clocks = <&clkc CLKID_USB>;
25                         clock-names = "usb_general";
26                         resets = <&reset RESET_USB_OTG>;
27                         reset-names = "usb_otg";
28
29                         dwc3: dwc3@c9000000 {
30                                 compatible = "snps,dwc3";
31                                 reg = <0x0 0xc9000000 0x0 0x100000>;
32                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
33                                 dr_mode = "host";
34                                 maximum-speed = "high-speed";
35                                 snps,dis_u2_susphy_quirk;
36                                 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
37                         };
38                 };
39         };
40 };
41
42 &apb {
43         usb2_phy0: phy@78000 {
44                 compatible = "amlogic,meson-gxl-usb2-phy";
45                 #phy-cells = <0>;
46                 reg = <0x0 0x78000 0x0 0x20>;
47                 clocks = <&clkc CLKID_USB>;
48                 clock-names = "phy";
49                 resets = <&reset RESET_USB_OTG>;
50                 reset-names = "phy";
51                 status = "okay";
52         };
53
54         usb2_phy1: phy@78020 {
55                 compatible = "amlogic,meson-gxl-usb2-phy";
56                 #phy-cells = <0>;
57                 reg = <0x0 0x78020 0x0 0x20>;
58                 clocks = <&clkc CLKID_USB>;
59                 clock-names = "phy";
60                 resets = <&reset RESET_USB_OTG>;
61                 reset-names = "phy";
62                 status = "okay";
63         };
64
65         usb3_phy: phy@78080 {
66                 compatible = "amlogic,meson-gxl-usb3-phy";
67                 #phy-cells = <0>;
68                 reg = <0x0 0x78080 0x0 0x20>;
69                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70                 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
71                 clock-names = "phy", "peripheral";
72                 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
73                 reset-names = "phy", "peripheral";
74                 status = "okay";
75         };
76 };
77
78 &efuse {
79         clocks = <&clkc CLKID_EFUSE>;
80 };
81
82 &ethmac {
83         reg = <0x0 0xc9410000 0x0 0x10000
84                0x0 0xc8834540 0x0 0x4>;
85
86         clocks = <&clkc CLKID_ETH>,
87                  <&clkc CLKID_FCLK_DIV2>,
88                  <&clkc CLKID_MPLL2>;
89         clock-names = "stmmaceth", "clkin0", "clkin1";
90
91         mdio0: mdio {
92                 #address-cells = <1>;
93                 #size-cells = <0>;
94                 compatible = "snps,dwmac-mdio";
95         };
96 };
97
98 &aobus {
99         pinctrl_aobus: pinctrl@14 {
100                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
101                 #address-cells = <2>;
102                 #size-cells = <2>;
103                 ranges;
104
105                 gpio_ao: bank@14 {
106                         reg = <0x0 0x00014 0x0 0x8>,
107                               <0x0 0x0002c 0x0 0x4>,
108                               <0x0 0x00024 0x0 0x8>;
109                         reg-names = "mux", "pull", "gpio";
110                         gpio-controller;
111                         #gpio-cells = <2>;
112                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
113                 };
114
115                 uart_ao_a_pins: uart_ao_a {
116                         mux {
117                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
118                                 function = "uart_ao";
119                         };
120                 };
121
122                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
123                         mux {
124                                 groups = "uart_cts_ao_a",
125                                        "uart_rts_ao_a";
126                                 function = "uart_ao";
127                         };
128                 };
129
130                 uart_ao_b_pins: uart_ao_b {
131                         mux {
132                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
133                                 function = "uart_ao_b";
134                         };
135                 };
136
137                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
138                         mux {
139                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
140                                 function = "uart_ao_b";
141                         };
142                 };
143
144                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
145                         mux {
146                                 groups = "uart_cts_ao_b",
147                                        "uart_rts_ao_b";
148                                 function = "uart_ao_b";
149                         };
150                 };
151
152                 remote_input_ao_pins: remote_input_ao {
153                         mux {
154                                 groups = "remote_input_ao";
155                                 function = "remote_input_ao";
156                         };
157                 };
158
159                 i2c_ao_pins: i2c_ao {
160                         mux {
161                                 groups = "i2c_sck_ao",
162                                        "i2c_sda_ao";
163                                 function = "i2c_ao";
164                         };
165                 };
166
167                 pwm_ao_a_3_pins: pwm_ao_a_3 {
168                         mux {
169                                 groups = "pwm_ao_a_3";
170                                 function = "pwm_ao_a";
171                         };
172                 };
173
174                 pwm_ao_a_8_pins: pwm_ao_a_8 {
175                         mux {
176                                 groups = "pwm_ao_a_8";
177                                 function = "pwm_ao_a";
178                         };
179                 };
180
181                 pwm_ao_b_pins: pwm_ao_b {
182                         mux {
183                                 groups = "pwm_ao_b";
184                                 function = "pwm_ao_b";
185                         };
186                 };
187
188                 pwm_ao_b_6_pins: pwm_ao_b_6 {
189                         mux {
190                                 groups = "pwm_ao_b_6";
191                                 function = "pwm_ao_b";
192                         };
193                 };
194
195                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
196                         mux {
197                                 groups = "i2s_out_ch23_ao";
198                                 function = "i2s_out_ao";
199                         };
200                 };
201
202                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
203                         mux {
204                                 groups = "i2s_out_ch45_ao";
205                                 function = "i2s_out_ao";
206                         };
207                 };
208
209                 spdif_out_ao_6_pins: spdif_out_ao_6 {
210                         mux {
211                                 groups = "spdif_out_ao_6";
212                                 function = "spdif_out_ao";
213                         };
214                 };
215
216                 spdif_out_ao_9_pins: spdif_out_ao_9 {
217                         mux {
218                                 groups = "spdif_out_ao_9";
219                                 function = "spdif_out_ao";
220                         };
221                 };
222
223                 ao_cec_pins: ao_cec {
224                         mux {
225                                 groups = "ao_cec";
226                                 function = "cec_ao";
227                         };
228                 };
229
230                 ee_cec_pins: ee_cec {
231                         mux {
232                                 groups = "ee_cec";
233                                 function = "cec_ao";
234                         };
235                 };
236         };
237 };
238
239 &cec_AO {
240         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
241         clock-names = "core";
242 };
243
244 &clkc_AO {
245         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
246 };
247
248 &gpio_intc {
249         compatible = "amlogic,meson-gpio-intc",
250                      "amlogic,meson-gxl-gpio-intc";
251         status = "okay";
252 };
253
254 &hdmi_tx {
255         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
256         resets = <&reset RESET_HDMITX_CAPB3>,
257                  <&reset RESET_HDMI_SYSTEM_RESET>,
258                  <&reset RESET_HDMI_TX>;
259         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
260         clocks = <&clkc CLKID_HDMI_PCLK>,
261                  <&clkc CLKID_CLK81>,
262                  <&clkc CLKID_GCLK_VENCI_INT0>;
263         clock-names = "isfr", "iahb", "venci";
264 };
265
266 &sysctrl {
267         clkc: clock-controller {
268                 compatible = "amlogic,gxl-clkc";
269                 #clock-cells = <1>;
270         };
271 };
272
273 &i2c_A {
274         clocks = <&clkc CLKID_I2C>;
275 };
276
277 &i2c_AO {
278         clocks = <&clkc CLKID_AO_I2C>;
279 };
280
281 &i2c_B {
282         clocks = <&clkc CLKID_I2C>;
283 };
284
285 &i2c_C {
286         clocks = <&clkc CLKID_I2C>;
287 };
288
289 &periphs {
290         pinctrl_periphs: pinctrl@4b0 {
291                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
292                 #address-cells = <2>;
293                 #size-cells = <2>;
294                 ranges;
295
296                 gpio: bank@4b0 {
297                         reg = <0x0 0x004b0 0x0 0x28>,
298                               <0x0 0x004e8 0x0 0x14>,
299                               <0x0 0x00520 0x0 0x14>,
300                               <0x0 0x00430 0x0 0x40>;
301                         reg-names = "mux", "pull", "pull-enable", "gpio";
302                         gpio-controller;
303                         #gpio-cells = <2>;
304                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
305                 };
306
307                 emmc_pins: emmc {
308                         mux {
309                                 groups = "emmc_nand_d07",
310                                        "emmc_cmd",
311                                        "emmc_clk";
312                                 function = "emmc";
313                         };
314                 };
315
316                 emmc_ds_pins: emmc-ds {
317                         mux {
318                                 groups = "emmc_ds";
319                                 function = "emmc";
320                         };
321                 };
322
323                 emmc_clk_gate_pins: emmc_clk_gate {
324                         mux {
325                                 groups = "BOOT_8";
326                                 function = "gpio_periphs";
327                                 bias-pull-down;
328                         };
329                 };
330
331                 nor_pins: nor {
332                         mux {
333                                 groups = "nor_d",
334                                        "nor_q",
335                                        "nor_c",
336                                        "nor_cs";
337                                 function = "nor";
338                         };
339                 };
340
341                 spi_pins: spi-pins {
342                         mux {
343                                 groups = "spi_miso",
344                                         "spi_mosi",
345                                         "spi_sclk";
346                                 function = "spi";
347                         };
348                 };
349
350                 spi_ss0_pins: spi-ss0 {
351                         mux {
352                                 groups = "spi_ss0";
353                                 function = "spi";
354                         };
355                 };
356
357                 sdcard_pins: sdcard {
358                         mux {
359                                 groups = "sdcard_d0",
360                                        "sdcard_d1",
361                                        "sdcard_d2",
362                                        "sdcard_d3",
363                                        "sdcard_cmd",
364                                        "sdcard_clk";
365                                 function = "sdcard";
366                         };
367                 };
368
369                 sdcard_clk_gate_pins: sdcard_clk_gate {
370                         mux {
371                                 groups = "CARD_2";
372                                 function = "gpio_periphs";
373                                 bias-pull-down;
374                         };
375                 };
376
377                 sdio_pins: sdio {
378                         mux {
379                                 groups = "sdio_d0",
380                                        "sdio_d1",
381                                        "sdio_d2",
382                                        "sdio_d3",
383                                        "sdio_cmd",
384                                        "sdio_clk";
385                                 function = "sdio";
386                         };
387                 };
388
389                 sdio_clk_gate_pins: sdio_clk_gate {
390                         mux {
391                                 groups = "GPIOX_4";
392                                 function = "gpio_periphs";
393                                 bias-pull-down;
394                         };
395                 };
396
397                 sdio_irq_pins: sdio_irq {
398                         mux {
399                                 groups = "sdio_irq";
400                                 function = "sdio";
401                         };
402                 };
403
404                 uart_a_pins: uart_a {
405                         mux {
406                                 groups = "uart_tx_a",
407                                        "uart_rx_a";
408                                 function = "uart_a";
409                         };
410                 };
411
412                 uart_a_cts_rts_pins: uart_a_cts_rts {
413                         mux {
414                                 groups = "uart_cts_a",
415                                        "uart_rts_a";
416                                 function = "uart_a";
417                         };
418                 };
419
420                 uart_b_pins: uart_b {
421                         mux {
422                                 groups = "uart_tx_b",
423                                        "uart_rx_b";
424                                 function = "uart_b";
425                         };
426                 };
427
428                 uart_b_cts_rts_pins: uart_b_cts_rts {
429                         mux {
430                                 groups = "uart_cts_b",
431                                        "uart_rts_b";
432                                 function = "uart_b";
433                         };
434                 };
435
436                 uart_c_pins: uart_c {
437                         mux {
438                                 groups = "uart_tx_c",
439                                        "uart_rx_c";
440                                 function = "uart_c";
441                         };
442                 };
443
444                 uart_c_cts_rts_pins: uart_c_cts_rts {
445                         mux {
446                                 groups = "uart_cts_c",
447                                        "uart_rts_c";
448                                 function = "uart_c";
449                         };
450                 };
451
452                 i2c_a_pins: i2c_a {
453                         mux {
454                                 groups = "i2c_sck_a",
455                                      "i2c_sda_a";
456                                 function = "i2c_a";
457                         };
458                 };
459
460                 i2c_b_pins: i2c_b {
461                         mux {
462                                 groups = "i2c_sck_b",
463                                       "i2c_sda_b";
464                                 function = "i2c_b";
465                         };
466                 };
467
468                 i2c_c_pins: i2c_c {
469                         mux {
470                                 groups = "i2c_sck_c",
471                                       "i2c_sda_c";
472                                 function = "i2c_c";
473                         };
474                 };
475
476                 eth_pins: eth_c {
477                         mux {
478                                 groups = "eth_mdio",
479                                        "eth_mdc",
480                                        "eth_clk_rx_clk",
481                                        "eth_rx_dv",
482                                        "eth_rxd0",
483                                        "eth_rxd1",
484                                        "eth_rxd2",
485                                        "eth_rxd3",
486                                        "eth_rgmii_tx_clk",
487                                        "eth_tx_en",
488                                        "eth_txd0",
489                                        "eth_txd1",
490                                        "eth_txd2",
491                                        "eth_txd3";
492                                 function = "eth";
493                         };
494                 };
495
496                 eth_link_led_pins: eth_link_led {
497                         mux {
498                                 groups = "eth_link_led";
499                                 function = "eth_led";
500                         };
501                 };
502
503                 eth_act_led_pins: eth_act_led {
504                         mux {
505                                 groups = "eth_act_led";
506                                 function = "eth_led";
507                         };
508                 };
509                 
510                 pwm_a_pins: pwm_a {
511                         mux {
512                                 groups = "pwm_a";
513                                 function = "pwm_a";
514                         };
515                 };
516
517                 pwm_b_pins: pwm_b {
518                         mux {
519                                 groups = "pwm_b";
520                                 function = "pwm_b";
521                         };
522                 };
523
524                 pwm_c_pins: pwm_c {
525                         mux {
526                                 groups = "pwm_c";
527                                 function = "pwm_c";
528                         };
529                 };
530
531                 pwm_d_pins: pwm_d {
532                         mux {
533                                 groups = "pwm_d";
534                                 function = "pwm_d";
535                         };
536                 };
537
538                 pwm_e_pins: pwm_e {
539                         mux {
540                                 groups = "pwm_e";
541                                 function = "pwm_e";
542                         };
543                 };
544
545                 pwm_f_clk_pins: pwm_f_clk {
546                         mux {
547                                 groups = "pwm_f_clk";
548                                 function = "pwm_f";
549                         };
550                 };
551
552                 pwm_f_x_pins: pwm_f_x {
553                         mux {
554                                 groups = "pwm_f_x";
555                                 function = "pwm_f";
556                         };
557                 };
558
559                 hdmi_hpd_pins: hdmi_hpd {
560                         mux {
561                                 groups = "hdmi_hpd";
562                                 function = "hdmi_hpd";
563                         };
564                 };
565
566                 hdmi_i2c_pins: hdmi_i2c {
567                         mux {
568                                 groups = "hdmi_sda", "hdmi_scl";
569                                 function = "hdmi_i2c";
570                         };
571                 };
572
573                 i2s_am_clk_pins: i2s_am_clk {
574                         mux {
575                                 groups = "i2s_am_clk";
576                                 function = "i2s_out";
577                         };
578                 };
579
580                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
581                         mux {
582                                 groups = "i2s_out_ao_clk";
583                                 function = "i2s_out";
584                         };
585                 };
586
587                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
588                         mux {
589                                 groups = "i2s_out_lr_clk";
590                                 function = "i2s_out";
591                         };
592                 };
593
594                 i2s_out_ch01_pins: i2s_out_ch01 {
595                         mux {
596                                 groups = "i2s_out_ch01";
597                                 function = "i2s_out";
598                         };
599                 };
600                 i2sout_ch23_z_pins: i2sout_ch23_z {
601                         mux {
602                                 groups = "i2sout_ch23_z";
603                                 function = "i2s_out";
604                         };
605                 };
606
607                 i2sout_ch45_z_pins: i2sout_ch45_z {
608                         mux {
609                                 groups = "i2sout_ch45_z";
610                                 function = "i2s_out";
611                         };
612                 };
613
614                 i2sout_ch67_z_pins: i2sout_ch67_z {
615                         mux {
616                                 groups = "i2sout_ch67_z";
617                                 function = "i2s_out";
618                         };
619                 };
620
621                 spdif_out_h_pins: spdif_out_ao_h {
622                         mux {
623                                 groups = "spdif_out_h";
624                                 function = "spdif_out";
625                         };
626                 };
627         };
628
629         eth-phy-mux {
630                 compatible = "mdio-mux-mmioreg", "mdio-mux";
631                 #address-cells = <1>;
632                 #size-cells = <0>;
633                 reg = <0x0 0x55c 0x0 0x4>;
634                 mux-mask = <0xffffffff>;
635                 mdio-parent-bus = <&mdio0>;
636
637                 internal_mdio: mdio@e40908ff {
638                         reg = <0xe40908ff>;
639                         #address-cells = <1>;
640                         #size-cells = <0>;
641
642                         internal_phy: ethernet-phy@8 {
643                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
644                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
645                                 reg = <8>;
646                                 max-speed = <100>;
647                         };
648                 };
649
650                 external_mdio: mdio@2009087f {
651                         reg = <0x2009087f>;
652                         #address-cells = <1>;
653                         #size-cells = <0>;
654                 };
655         };
656 };
657
658 &pwrc_vpu {
659         resets = <&reset RESET_VIU>,
660                  <&reset RESET_VENC>,
661                  <&reset RESET_VCBUS>,
662                  <&reset RESET_BT656>,
663                  <&reset RESET_DVIN_RESET>,
664                  <&reset RESET_RDMA>,
665                  <&reset RESET_VENCI>,
666                  <&reset RESET_VENCP>,
667                  <&reset RESET_VDAC>,
668                  <&reset RESET_VDI6>,
669                  <&reset RESET_VENCL>,
670                  <&reset RESET_VID_LOCK>;
671         clocks = <&clkc CLKID_VPU>,
672                  <&clkc CLKID_VAPB>;
673         clock-names = "vpu", "vapb";
674         /*
675          * VPU clocking is provided by two identical clock paths
676          * VPU_0 and VPU_1 muxed to a single clock by a glitch
677          * free mux to safely change frequency while running.
678          * Same for VAPB but with a final gate after the glitch free mux.
679          */
680         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
681                           <&clkc CLKID_VPU_0>,
682                           <&clkc CLKID_VPU>, /* Glitch free mux */
683                           <&clkc CLKID_VAPB_0_SEL>,
684                           <&clkc CLKID_VAPB_0>,
685                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
686         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
687                                  <0>, /* Do Nothing */
688                                  <&clkc CLKID_VPU_0>,
689                                  <&clkc CLKID_FCLK_DIV4>,
690                                  <0>, /* Do Nothing */
691                                  <&clkc CLKID_VAPB_0>;
692         assigned-clock-rates = <0>, /* Do Nothing */
693                                <666666666>,
694                                <0>, /* Do Nothing */
695                                <0>, /* Do Nothing */
696                                <250000000>,
697                                <0>; /* Do Nothing */
698 };
699
700 &saradc {
701         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
702         clocks = <&xtal>,
703                  <&clkc CLKID_SAR_ADC>,
704                  <&clkc CLKID_SAR_ADC_CLK>,
705                  <&clkc CLKID_SAR_ADC_SEL>;
706         clock-names = "clkin", "core", "adc_clk", "adc_sel";
707 };
708
709 &sd_emmc_a {
710         clocks = <&clkc CLKID_SD_EMMC_A>,
711                  <&clkc CLKID_SD_EMMC_A_CLK0>,
712                  <&clkc CLKID_FCLK_DIV2>;
713         clock-names = "core", "clkin0", "clkin1";
714         resets = <&reset RESET_SD_EMMC_A>;
715 };
716
717 &sd_emmc_b {
718         clocks = <&clkc CLKID_SD_EMMC_B>,
719                  <&clkc CLKID_SD_EMMC_B_CLK0>,
720                  <&clkc CLKID_FCLK_DIV2>;
721         clock-names = "core", "clkin0", "clkin1";
722         resets = <&reset RESET_SD_EMMC_B>;
723 };
724
725 &sd_emmc_c {
726         clocks = <&clkc CLKID_SD_EMMC_C>,
727                  <&clkc CLKID_SD_EMMC_C_CLK0>,
728                  <&clkc CLKID_FCLK_DIV2>;
729         clock-names = "core", "clkin0", "clkin1";
730         resets = <&reset RESET_SD_EMMC_C>;
731 };
732
733 &spicc {
734         clocks = <&clkc CLKID_SPICC>;
735         clock-names = "core";
736         resets = <&reset RESET_PERIPHS_SPICC>;
737         num-cs = <1>;
738 };
739
740 &spifc {
741         clocks = <&clkc CLKID_SPI>;
742 };
743
744 &uart_A {
745         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
746         clock-names = "xtal", "pclk", "baud";
747 };
748
749 &uart_AO {
750         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
751         clock-names = "xtal", "pclk", "baud";
752 };
753
754 &uart_AO_B {
755         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
756         clock-names = "xtal", "pclk", "baud";
757 };
758
759 &uart_B {
760         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
761         clock-names = "xtal", "pclk", "baud";
762 };
763
764 &uart_C {
765         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
766         clock-names = "xtal", "pclk", "baud";
767 };
768
769 &vpu {
770         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
771         power-domains = <&pwrc_vpu>;
772 };