arm64: dts: Fix various entry-method properties to reflect documentation
[muen/linux.git] / arch / arm64 / boot / dts / arm / juno.dts
1 /*
2  * ARM Ltd. Juno Platform
3  *
4  * Copyright (c) 2013-2014 ARM Ltd.
5  *
6  * This file is licensed under a dual GPLv2 or BSD license.
7  */
8
9 /dts-v1/;
10
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13
14 / {
15         model = "ARM Juno development board (r0)";
16         compatible = "arm,juno", "arm,vexpress";
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
20
21         aliases {
22                 serial0 = &soc_uart0;
23         };
24
25         chosen {
26                 stdout-path = "serial0:115200n8";
27         };
28
29         psci {
30                 compatible = "arm,psci-0.2";
31                 method = "smc";
32         };
33
34         cpus {
35                 #address-cells = <2>;
36                 #size-cells = <0>;
37
38                 cpu-map {
39                         cluster0 {
40                                 core0 {
41                                         cpu = <&A57_0>;
42                                 };
43                                 core1 {
44                                         cpu = <&A57_1>;
45                                 };
46                         };
47
48                         cluster1 {
49                                 core0 {
50                                         cpu = <&A53_0>;
51                                 };
52                                 core1 {
53                                         cpu = <&A53_1>;
54                                 };
55                                 core2 {
56                                         cpu = <&A53_2>;
57                                 };
58                                 core3 {
59                                         cpu = <&A53_3>;
60                                 };
61                         };
62                 };
63
64                 idle-states {
65                         entry-method = "psci";
66
67                         CPU_SLEEP_0: cpu-sleep-0 {
68                                 compatible = "arm,idle-state";
69                                 arm,psci-suspend-param = <0x0010000>;
70                                 local-timer-stop;
71                                 entry-latency-us = <300>;
72                                 exit-latency-us = <1200>;
73                                 min-residency-us = <2000>;
74                         };
75
76                         CLUSTER_SLEEP_0: cluster-sleep-0 {
77                                 compatible = "arm,idle-state";
78                                 arm,psci-suspend-param = <0x1010000>;
79                                 local-timer-stop;
80                                 entry-latency-us = <400>;
81                                 exit-latency-us = <1200>;
82                                 min-residency-us = <2500>;
83                         };
84                 };
85
86                 A57_0: cpu@0 {
87                         compatible = "arm,cortex-a57","arm,armv8";
88                         reg = <0x0 0x0>;
89                         device_type = "cpu";
90                         enable-method = "psci";
91                         i-cache-size = <0xc000>;
92                         i-cache-line-size = <64>;
93                         i-cache-sets = <256>;
94                         d-cache-size = <0x8000>;
95                         d-cache-line-size = <64>;
96                         d-cache-sets = <256>;
97                         next-level-cache = <&A57_L2>;
98                         clocks = <&scpi_dvfs 0>;
99                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
100                         capacity-dmips-mhz = <1024>;
101                 };
102
103                 A57_1: cpu@1 {
104                         compatible = "arm,cortex-a57","arm,armv8";
105                         reg = <0x0 0x1>;
106                         device_type = "cpu";
107                         enable-method = "psci";
108                         i-cache-size = <0xc000>;
109                         i-cache-line-size = <64>;
110                         i-cache-sets = <256>;
111                         d-cache-size = <0x8000>;
112                         d-cache-line-size = <64>;
113                         d-cache-sets = <256>;
114                         next-level-cache = <&A57_L2>;
115                         clocks = <&scpi_dvfs 0>;
116                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
117                         capacity-dmips-mhz = <1024>;
118                 };
119
120                 A53_0: cpu@100 {
121                         compatible = "arm,cortex-a53","arm,armv8";
122                         reg = <0x0 0x100>;
123                         device_type = "cpu";
124                         enable-method = "psci";
125                         i-cache-size = <0x8000>;
126                         i-cache-line-size = <64>;
127                         i-cache-sets = <256>;
128                         d-cache-size = <0x8000>;
129                         d-cache-line-size = <64>;
130                         d-cache-sets = <128>;
131                         next-level-cache = <&A53_L2>;
132                         clocks = <&scpi_dvfs 1>;
133                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
134                         capacity-dmips-mhz = <578>;
135                 };
136
137                 A53_1: cpu@101 {
138                         compatible = "arm,cortex-a53","arm,armv8";
139                         reg = <0x0 0x101>;
140                         device_type = "cpu";
141                         enable-method = "psci";
142                         i-cache-size = <0x8000>;
143                         i-cache-line-size = <64>;
144                         i-cache-sets = <256>;
145                         d-cache-size = <0x8000>;
146                         d-cache-line-size = <64>;
147                         d-cache-sets = <128>;
148                         next-level-cache = <&A53_L2>;
149                         clocks = <&scpi_dvfs 1>;
150                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
151                         capacity-dmips-mhz = <578>;
152                 };
153
154                 A53_2: cpu@102 {
155                         compatible = "arm,cortex-a53","arm,armv8";
156                         reg = <0x0 0x102>;
157                         device_type = "cpu";
158                         enable-method = "psci";
159                         i-cache-size = <0x8000>;
160                         i-cache-line-size = <64>;
161                         i-cache-sets = <256>;
162                         d-cache-size = <0x8000>;
163                         d-cache-line-size = <64>;
164                         d-cache-sets = <128>;
165                         next-level-cache = <&A53_L2>;
166                         clocks = <&scpi_dvfs 1>;
167                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
168                         capacity-dmips-mhz = <578>;
169                 };
170
171                 A53_3: cpu@103 {
172                         compatible = "arm,cortex-a53","arm,armv8";
173                         reg = <0x0 0x103>;
174                         device_type = "cpu";
175                         enable-method = "psci";
176                         i-cache-size = <0x8000>;
177                         i-cache-line-size = <64>;
178                         i-cache-sets = <256>;
179                         d-cache-size = <0x8000>;
180                         d-cache-line-size = <64>;
181                         d-cache-sets = <128>;
182                         next-level-cache = <&A53_L2>;
183                         clocks = <&scpi_dvfs 1>;
184                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
185                         capacity-dmips-mhz = <578>;
186                 };
187
188                 A57_L2: l2-cache0 {
189                         compatible = "cache";
190                         cache-size = <0x200000>;
191                         cache-line-size = <64>;
192                         cache-sets = <2048>;
193                 };
194
195                 A53_L2: l2-cache1 {
196                         compatible = "cache";
197                         cache-size = <0x100000>;
198                         cache-line-size = <64>;
199                         cache-sets = <1024>;
200                 };
201         };
202
203         pmu-a57 {
204                 compatible = "arm,cortex-a57-pmu";
205                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
206                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
207                 interrupt-affinity = <&A57_0>,
208                                      <&A57_1>;
209         };
210
211         pmu-a53 {
212                 compatible = "arm,cortex-a53-pmu";
213                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
214                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
215                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
216                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
217                 interrupt-affinity = <&A53_0>,
218                                      <&A53_1>,
219                                      <&A53_2>,
220                                      <&A53_3>;
221         };
222 };
223
224 &etm0 {
225         cpu = <&A57_0>;
226 };
227
228 &etm1 {
229         cpu = <&A57_1>;
230 };
231
232 &etm2 {
233         cpu = <&A53_0>;
234 };
235
236 &etm3 {
237         cpu = <&A53_1>;
238 };
239
240 &etm4 {
241         cpu = <&A53_2>;
242 };
243
244 &etm5 {
245         cpu = <&A53_3>;
246 };
247
248 &etf0_out_port {
249         remote-endpoint = <&replicator_in_port0>;
250 };
251
252 &replicator_in_port0 {
253         remote-endpoint = <&etf0_out_port>;
254 };
255
256 &stm_out_port {
257         remote-endpoint = <&main_funnel_in_port2>;
258 };
259
260 &main_funnel {
261         ports {
262                 port@3 {
263                         reg = <2>;
264                         main_funnel_in_port2: endpoint {
265                                 slave-mode;
266                                 remote-endpoint = <&stm_out_port>;
267                         };
268                 };
269         };
270 };
271
272 &cpu_debug0 {
273         cpu = <&A57_0>;
274 };
275
276 &cpu_debug1 {
277         cpu = <&A57_1>;
278 };
279
280 &cpu_debug2 {
281         cpu = <&A53_0>;
282 };
283
284 &cpu_debug3 {
285         cpu = <&A53_1>;
286 };
287
288 &cpu_debug4 {
289         cpu = <&A53_2>;
290 };
291
292 &cpu_debug5 {
293         cpu = <&A53_3>;
294 };