Merge branch 'parisc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller...
[muen/linux.git] / arch / arm64 / boot / dts / freescale / fsl-ls208xa.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4  *
5  * Copyright 2016 Freescale Semiconductor, Inc.
6  * Copyright 2017 NXP
7  *
8  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9  *
10  */
11
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14
15 / {
16         compatible = "fsl,ls2080a";
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
20
21         aliases {
22                 crypto = &crypto;
23                 serial0 = &serial0;
24                 serial1 = &serial1;
25         };
26
27         cpu: cpus {
28                 #address-cells = <1>;
29                 #size-cells = <0>;
30         };
31
32         memory@80000000 {
33                 device_type = "memory";
34                 reg = <0x00000000 0x80000000 0 0x80000000>;
35                       /* DRAM space - 1, size : 2 GB DRAM */
36         };
37
38         sysclk: sysclk {
39                 compatible = "fixed-clock";
40                 #clock-cells = <0>;
41                 clock-frequency = <100000000>;
42                 clock-output-names = "sysclk";
43         };
44
45         gic: interrupt-controller@6000000 {
46                 compatible = "arm,gic-v3";
47                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
48                         <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
49                         <0x0 0x0c0c0000 0 0x2000>, /* GICC */
50                         <0x0 0x0c0d0000 0 0x1000>, /* GICH */
51                         <0x0 0x0c0e0000 0 0x20000>; /* GICV */
52                 #interrupt-cells = <3>;
53                 #address-cells = <2>;
54                 #size-cells = <2>;
55                 ranges;
56                 interrupt-controller;
57                 interrupts = <1 9 0x4>;
58
59                 its: gic-its@6020000 {
60                         compatible = "arm,gic-v3-its";
61                         msi-controller;
62                         reg = <0x0 0x6020000 0 0x20000>;
63                 };
64         };
65
66         rstcr: syscon@1e60000 {
67                 compatible = "fsl,ls2080a-rstcr", "syscon";
68                 reg = <0x0 0x1e60000 0x0 0x4>;
69         };
70
71         reboot {
72                 compatible ="syscon-reboot";
73                 regmap = <&rstcr>;
74                 offset = <0x0>;
75                 mask = <0x2>;
76         };
77
78         thermal-zones {
79                 cpu_thermal: cpu-thermal {
80                         polling-delay-passive = <1000>;
81                         polling-delay = <5000>;
82
83                         thermal-sensors = <&tmu 4>;
84
85                         trips {
86                                 cpu_alert: cpu-alert {
87                                         temperature = <75000>;
88                                         hysteresis = <2000>;
89                                         type = "passive";
90                                 };
91                                 cpu_crit: cpu-crit {
92                                         temperature = <85000>;
93                                         hysteresis = <2000>;
94                                         type = "critical";
95                                 };
96                         };
97
98                         cooling-maps {
99                                 map0 {
100                                         trip = <&cpu_alert>;
101                                         cooling-device =
102                                                 <&cpu0 THERMAL_NO_LIMIT
103                                                 THERMAL_NO_LIMIT>;
104                                 };
105                                 map1 {
106                                         trip = <&cpu_alert>;
107                                         cooling-device =
108                                                 <&cpu2 THERMAL_NO_LIMIT
109                                                 THERMAL_NO_LIMIT>;
110                                 };
111                                 map2 {
112                                         trip = <&cpu_alert>;
113                                         cooling-device =
114                                                 <&cpu4 THERMAL_NO_LIMIT
115                                                 THERMAL_NO_LIMIT>;
116                                 };
117                                 map3 {
118                                         trip = <&cpu_alert>;
119                                         cooling-device =
120                                                 <&cpu6 THERMAL_NO_LIMIT
121                                                 THERMAL_NO_LIMIT>;
122                                 };
123                         };
124                 };
125         };
126
127         timer {
128                 compatible = "arm,armv8-timer";
129                 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
130                              <1 14 4>, /* Physical Non-Secure PPI, active-low */
131                              <1 11 4>, /* Virtual PPI, active-low */
132                              <1 10 4>; /* Hypervisor PPI, active-low */
133                 fsl,erratum-a008585;
134         };
135
136         pmu {
137                 compatible = "arm,armv8-pmuv3";
138                 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
139         };
140
141         psci {
142                 compatible = "arm,psci-0.2";
143                 method = "smc";
144         };
145
146         soc {
147                 compatible = "simple-bus";
148                 #address-cells = <2>;
149                 #size-cells = <2>;
150                 ranges;
151                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
152
153                 clockgen: clocking@1300000 {
154                         compatible = "fsl,ls2080a-clockgen";
155                         reg = <0 0x1300000 0 0xa0000>;
156                         #clock-cells = <2>;
157                         clocks = <&sysclk>;
158                 };
159
160                 dcfg: dcfg@1e00000 {
161                         compatible = "fsl,ls2080a-dcfg", "syscon";
162                         reg = <0x0 0x1e00000 0x0 0x10000>;
163                         little-endian;
164                 };
165
166                 tmu: tmu@1f80000 {
167                         compatible = "fsl,qoriq-tmu";
168                         reg = <0x0 0x1f80000 0x0 0x10000>;
169                         interrupts = <0 23 0x4>;
170                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
171                         fsl,tmu-calibration = <0x00000000 0x00000026
172                                                0x00000001 0x0000002d
173                                                0x00000002 0x00000032
174                                                0x00000003 0x00000039
175                                                0x00000004 0x0000003f
176                                                0x00000005 0x00000046
177                                                0x00000006 0x0000004d
178                                                0x00000007 0x00000054
179                                                0x00000008 0x0000005a
180                                                0x00000009 0x00000061
181                                                0x0000000a 0x0000006a
182                                                0x0000000b 0x00000071
183
184                                                0x00010000 0x00000025
185                                                0x00010001 0x0000002c
186                                                0x00010002 0x00000035
187                                                0x00010003 0x0000003d
188                                                0x00010004 0x00000045
189                                                0x00010005 0x0000004e
190                                                0x00010006 0x00000057
191                                                0x00010007 0x00000061
192                                                0x00010008 0x0000006b
193                                                0x00010009 0x00000076
194
195                                                0x00020000 0x00000029
196                                                0x00020001 0x00000033
197                                                0x00020002 0x0000003d
198                                                0x00020003 0x00000049
199                                                0x00020004 0x00000056
200                                                0x00020005 0x00000061
201                                                0x00020006 0x0000006d
202
203                                                0x00030000 0x00000021
204                                                0x00030001 0x0000002a
205                                                0x00030002 0x0000003c
206                                                0x00030003 0x0000004e>;
207                         little-endian;
208                         #thermal-sensor-cells = <1>;
209                 };
210
211                 serial0: serial@21c0500 {
212                         compatible = "fsl,ns16550", "ns16550a";
213                         reg = <0x0 0x21c0500 0x0 0x100>;
214                         clocks = <&clockgen 4 3>;
215                         interrupts = <0 32 0x4>; /* Level high type */
216                 };
217
218                 serial1: serial@21c0600 {
219                         compatible = "fsl,ns16550", "ns16550a";
220                         reg = <0x0 0x21c0600 0x0 0x100>;
221                         clocks = <&clockgen 4 3>;
222                         interrupts = <0 32 0x4>; /* Level high type */
223                 };
224
225                 cluster1_core0_watchdog: wdt@c000000 {
226                         compatible = "arm,sp805-wdt", "arm,primecell";
227                         reg = <0x0 0xc000000 0x0 0x1000>;
228                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
229                         clock-names = "apb_pclk", "wdog_clk";
230                 };
231
232                 cluster1_core1_watchdog: wdt@c010000 {
233                         compatible = "arm,sp805-wdt", "arm,primecell";
234                         reg = <0x0 0xc010000 0x0 0x1000>;
235                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
236                         clock-names = "apb_pclk", "wdog_clk";
237                 };
238
239                 cluster2_core0_watchdog: wdt@c100000 {
240                         compatible = "arm,sp805-wdt", "arm,primecell";
241                         reg = <0x0 0xc100000 0x0 0x1000>;
242                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
243                         clock-names = "apb_pclk", "wdog_clk";
244                 };
245
246                 cluster2_core1_watchdog: wdt@c110000 {
247                         compatible = "arm,sp805-wdt", "arm,primecell";
248                         reg = <0x0 0xc110000 0x0 0x1000>;
249                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
250                         clock-names = "apb_pclk", "wdog_clk";
251                 };
252
253                 cluster3_core0_watchdog: wdt@c200000 {
254                         compatible = "arm,sp805-wdt", "arm,primecell";
255                         reg = <0x0 0xc200000 0x0 0x1000>;
256                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
257                         clock-names = "apb_pclk", "wdog_clk";
258                 };
259
260                 cluster3_core1_watchdog: wdt@c210000 {
261                         compatible = "arm,sp805-wdt", "arm,primecell";
262                         reg = <0x0 0xc210000 0x0 0x1000>;
263                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
264                         clock-names = "apb_pclk", "wdog_clk";
265                 };
266
267                 cluster4_core0_watchdog: wdt@c300000 {
268                         compatible = "arm,sp805-wdt", "arm,primecell";
269                         reg = <0x0 0xc300000 0x0 0x1000>;
270                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
271                         clock-names = "apb_pclk", "wdog_clk";
272                 };
273
274                 cluster4_core1_watchdog: wdt@c310000 {
275                         compatible = "arm,sp805-wdt", "arm,primecell";
276                         reg = <0x0 0xc310000 0x0 0x1000>;
277                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
278                         clock-names = "apb_pclk", "wdog_clk";
279                 };
280
281                 crypto: crypto@8000000 {
282                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
283                         fsl,sec-era = <8>;
284                         #address-cells = <1>;
285                         #size-cells = <1>;
286                         ranges = <0x0 0x00 0x8000000 0x100000>;
287                         reg = <0x00 0x8000000 0x0 0x100000>;
288                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
289                         dma-coherent;
290
291                         sec_jr0: jr@10000 {
292                                 compatible = "fsl,sec-v5.0-job-ring",
293                                              "fsl,sec-v4.0-job-ring";
294                                 reg        = <0x10000 0x10000>;
295                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
296                         };
297
298                         sec_jr1: jr@20000 {
299                                 compatible = "fsl,sec-v5.0-job-ring",
300                                              "fsl,sec-v4.0-job-ring";
301                                 reg        = <0x20000 0x10000>;
302                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
303                         };
304
305                         sec_jr2: jr@30000 {
306                                 compatible = "fsl,sec-v5.0-job-ring",
307                                              "fsl,sec-v4.0-job-ring";
308                                 reg        = <0x30000 0x10000>;
309                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
310                         };
311
312                         sec_jr3: jr@40000 {
313                                 compatible = "fsl,sec-v5.0-job-ring",
314                                              "fsl,sec-v4.0-job-ring";
315                                 reg        = <0x40000 0x10000>;
316                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
317                         };
318                 };
319
320                 fsl_mc: fsl-mc@80c000000 {
321                         compatible = "fsl,qoriq-mc";
322                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
323                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
324                         msi-parent = <&its>;
325                         iommu-map = <0 &smmu 0 0>;      /* This is fixed-up by u-boot */
326                         dma-coherent;
327                         #address-cells = <3>;
328                         #size-cells = <1>;
329
330                         /*
331                          * Region type 0x0 - MC portals
332                          * Region type 0x1 - QBMAN portals
333                          */
334                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
335                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
336
337                         /*
338                          * Define the maximum number of MACs present on the SoC.
339                          */
340                         dpmacs {
341                                 #address-cells = <1>;
342                                 #size-cells = <0>;
343
344                                 dpmac1: dpmac@1 {
345                                         compatible = "fsl,qoriq-mc-dpmac";
346                                         reg = <0x1>;
347                                 };
348
349                                 dpmac2: dpmac@2 {
350                                         compatible = "fsl,qoriq-mc-dpmac";
351                                         reg = <0x2>;
352                                 };
353
354                                 dpmac3: dpmac@3 {
355                                         compatible = "fsl,qoriq-mc-dpmac";
356                                         reg = <0x3>;
357                                 };
358
359                                 dpmac4: dpmac@4 {
360                                         compatible = "fsl,qoriq-mc-dpmac";
361                                         reg = <0x4>;
362                                 };
363
364                                 dpmac5: dpmac@5 {
365                                         compatible = "fsl,qoriq-mc-dpmac";
366                                         reg = <0x5>;
367                                 };
368
369                                 dpmac6: dpmac@6 {
370                                         compatible = "fsl,qoriq-mc-dpmac";
371                                         reg = <0x6>;
372                                 };
373
374                                 dpmac7: dpmac@7 {
375                                         compatible = "fsl,qoriq-mc-dpmac";
376                                         reg = <0x7>;
377                                 };
378
379                                 dpmac8: dpmac@8 {
380                                         compatible = "fsl,qoriq-mc-dpmac";
381                                         reg = <0x8>;
382                                 };
383
384                                 dpmac9: dpmac@9 {
385                                         compatible = "fsl,qoriq-mc-dpmac";
386                                         reg = <0x9>;
387                                 };
388
389                                 dpmac10: dpmac@a {
390                                         compatible = "fsl,qoriq-mc-dpmac";
391                                         reg = <0xa>;
392                                 };
393
394                                 dpmac11: dpmac@b {
395                                         compatible = "fsl,qoriq-mc-dpmac";
396                                         reg = <0xb>;
397                                 };
398
399                                 dpmac12: dpmac@c {
400                                         compatible = "fsl,qoriq-mc-dpmac";
401                                         reg = <0xc>;
402                                 };
403
404                                 dpmac13: dpmac@d {
405                                         compatible = "fsl,qoriq-mc-dpmac";
406                                         reg = <0xd>;
407                                 };
408
409                                 dpmac14: dpmac@e {
410                                         compatible = "fsl,qoriq-mc-dpmac";
411                                         reg = <0xe>;
412                                 };
413
414                                 dpmac15: dpmac@f {
415                                         compatible = "fsl,qoriq-mc-dpmac";
416                                         reg = <0xf>;
417                                 };
418
419                                 dpmac16: dpmac@10 {
420                                         compatible = "fsl,qoriq-mc-dpmac";
421                                         reg = <0x10>;
422                                 };
423                         };
424                 };
425
426                 smmu: iommu@5000000 {
427                         compatible = "arm,mmu-500";
428                         reg = <0 0x5000000 0 0x800000>;
429                         #global-interrupts = <12>;
430                         #iommu-cells = <1>;
431                         stream-match-mask = <0x7C00>;
432                         dma-coherent;
433                         interrupts = <0 13 4>, /* global secure fault */
434                                      <0 14 4>, /* combined secure interrupt */
435                                      <0 15 4>, /* global non-secure fault */
436                                      <0 16 4>, /* combined non-secure interrupt */
437                                 /* performance counter interrupts 0-7 */
438                                      <0 211 4>, <0 212 4>,
439                                      <0 213 4>, <0 214 4>,
440                                      <0 215 4>, <0 216 4>,
441                                      <0 217 4>, <0 218 4>,
442                                 /* per context interrupt, 64 interrupts */
443                                      <0 146 4>, <0 147 4>,
444                                      <0 148 4>, <0 149 4>,
445                                      <0 150 4>, <0 151 4>,
446                                      <0 152 4>, <0 153 4>,
447                                      <0 154 4>, <0 155 4>,
448                                      <0 156 4>, <0 157 4>,
449                                      <0 158 4>, <0 159 4>,
450                                      <0 160 4>, <0 161 4>,
451                                      <0 162 4>, <0 163 4>,
452                                      <0 164 4>, <0 165 4>,
453                                      <0 166 4>, <0 167 4>,
454                                      <0 168 4>, <0 169 4>,
455                                      <0 170 4>, <0 171 4>,
456                                      <0 172 4>, <0 173 4>,
457                                      <0 174 4>, <0 175 4>,
458                                      <0 176 4>, <0 177 4>,
459                                      <0 178 4>, <0 179 4>,
460                                      <0 180 4>, <0 181 4>,
461                                      <0 182 4>, <0 183 4>,
462                                      <0 184 4>, <0 185 4>,
463                                      <0 186 4>, <0 187 4>,
464                                      <0 188 4>, <0 189 4>,
465                                      <0 190 4>, <0 191 4>,
466                                      <0 192 4>, <0 193 4>,
467                                      <0 194 4>, <0 195 4>,
468                                      <0 196 4>, <0 197 4>,
469                                      <0 198 4>, <0 199 4>,
470                                      <0 200 4>, <0 201 4>,
471                                      <0 202 4>, <0 203 4>,
472                                      <0 204 4>, <0 205 4>,
473                                      <0 206 4>, <0 207 4>,
474                                      <0 208 4>, <0 209 4>;
475                 };
476
477                 dspi: dspi@2100000 {
478                         status = "disabled";
479                         compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
480                         #address-cells = <1>;
481                         #size-cells = <0>;
482                         reg = <0x0 0x2100000 0x0 0x10000>;
483                         interrupts = <0 26 0x4>; /* Level high type */
484                         clocks = <&clockgen 4 3>;
485                         clock-names = "dspi";
486                         spi-num-chipselects = <5>;
487                         bus-num = <0>;
488                 };
489
490                 esdhc: esdhc@2140000 {
491                         status = "disabled";
492                         compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
493                         reg = <0x0 0x2140000 0x0 0x10000>;
494                         interrupts = <0 28 0x4>; /* Level high type */
495                         clocks = <&clockgen 4 1>;
496                         voltage-ranges = <1800 1800 3300 3300>;
497                         sdhci,auto-cmd12;
498                         little-endian;
499                         bus-width = <4>;
500                 };
501
502                 gpio0: gpio@2300000 {
503                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
504                         reg = <0x0 0x2300000 0x0 0x10000>;
505                         interrupts = <0 36 0x4>; /* Level high type */
506                         gpio-controller;
507                         little-endian;
508                         #gpio-cells = <2>;
509                         interrupt-controller;
510                         #interrupt-cells = <2>;
511                 };
512
513                 gpio1: gpio@2310000 {
514                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
515                         reg = <0x0 0x2310000 0x0 0x10000>;
516                         interrupts = <0 36 0x4>; /* Level high type */
517                         gpio-controller;
518                         little-endian;
519                         #gpio-cells = <2>;
520                         interrupt-controller;
521                         #interrupt-cells = <2>;
522                 };
523
524                 gpio2: gpio@2320000 {
525                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
526                         reg = <0x0 0x2320000 0x0 0x10000>;
527                         interrupts = <0 37 0x4>; /* Level high type */
528                         gpio-controller;
529                         little-endian;
530                         #gpio-cells = <2>;
531                         interrupt-controller;
532                         #interrupt-cells = <2>;
533                 };
534
535                 gpio3: gpio@2330000 {
536                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
537                         reg = <0x0 0x2330000 0x0 0x10000>;
538                         interrupts = <0 37 0x4>; /* Level high type */
539                         gpio-controller;
540                         little-endian;
541                         #gpio-cells = <2>;
542                         interrupt-controller;
543                         #interrupt-cells = <2>;
544                 };
545
546                 i2c0: i2c@2000000 {
547                         status = "disabled";
548                         compatible = "fsl,vf610-i2c";
549                         #address-cells = <1>;
550                         #size-cells = <0>;
551                         reg = <0x0 0x2000000 0x0 0x10000>;
552                         interrupts = <0 34 0x4>; /* Level high type */
553                         clock-names = "i2c";
554                         clocks = <&clockgen 4 3>;
555                 };
556
557                 i2c1: i2c@2010000 {
558                         status = "disabled";
559                         compatible = "fsl,vf610-i2c";
560                         #address-cells = <1>;
561                         #size-cells = <0>;
562                         reg = <0x0 0x2010000 0x0 0x10000>;
563                         interrupts = <0 34 0x4>; /* Level high type */
564                         clock-names = "i2c";
565                         clocks = <&clockgen 4 3>;
566                 };
567
568                 i2c2: i2c@2020000 {
569                         status = "disabled";
570                         compatible = "fsl,vf610-i2c";
571                         #address-cells = <1>;
572                         #size-cells = <0>;
573                         reg = <0x0 0x2020000 0x0 0x10000>;
574                         interrupts = <0 35 0x4>; /* Level high type */
575                         clock-names = "i2c";
576                         clocks = <&clockgen 4 3>;
577                 };
578
579                 i2c3: i2c@2030000 {
580                         status = "disabled";
581                         compatible = "fsl,vf610-i2c";
582                         #address-cells = <1>;
583                         #size-cells = <0>;
584                         reg = <0x0 0x2030000 0x0 0x10000>;
585                         interrupts = <0 35 0x4>; /* Level high type */
586                         clock-names = "i2c";
587                         clocks = <&clockgen 4 3>;
588                 };
589
590                 ifc: ifc@2240000 {
591                         compatible = "fsl,ifc", "simple-bus";
592                         reg = <0x0 0x2240000 0x0 0x20000>;
593                         interrupts = <0 21 0x4>; /* Level high type */
594                         little-endian;
595                         #address-cells = <2>;
596                         #size-cells = <1>;
597
598                         ranges = <0 0 0x5 0x80000000 0x08000000
599                                   2 0 0x5 0x30000000 0x00010000
600                                   3 0 0x5 0x20000000 0x00010000>;
601                 };
602
603                 qspi: quadspi@20c0000 {
604                         status = "disabled";
605                         compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
606                         #address-cells = <1>;
607                         #size-cells = <0>;
608                         reg = <0x0 0x20c0000 0x0 0x10000>,
609                               <0x0 0x20000000 0x0 0x10000000>;
610                         reg-names = "QuadSPI", "QuadSPI-memory";
611                         interrupts = <0 25 0x4>; /* Level high type */
612                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
613                         clock-names = "qspi_en", "qspi";
614                 };
615
616                 pcie1: pcie@3400000 {
617                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
618                                      "snps,dw-pcie";
619                         reg-names = "regs", "config";
620                         interrupts = <0 108 0x4>; /* Level high type */
621                         interrupt-names = "intr";
622                         #address-cells = <3>;
623                         #size-cells = <2>;
624                         device_type = "pci";
625                         dma-coherent;
626                         num-lanes = <4>;
627                         bus-range = <0x0 0xff>;
628                         msi-parent = <&its>;
629                         #interrupt-cells = <1>;
630                         interrupt-map-mask = <0 0 0 7>;
631                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
632                                         <0000 0 0 2 &gic 0 0 0 110 4>,
633                                         <0000 0 0 3 &gic 0 0 0 111 4>,
634                                         <0000 0 0 4 &gic 0 0 0 112 4>;
635                 };
636
637                 pcie2: pcie@3500000 {
638                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
639                                      "snps,dw-pcie";
640                         reg-names = "regs", "config";
641                         interrupts = <0 113 0x4>; /* Level high type */
642                         interrupt-names = "intr";
643                         #address-cells = <3>;
644                         #size-cells = <2>;
645                         device_type = "pci";
646                         dma-coherent;
647                         num-lanes = <4>;
648                         bus-range = <0x0 0xff>;
649                         msi-parent = <&its>;
650                         #interrupt-cells = <1>;
651                         interrupt-map-mask = <0 0 0 7>;
652                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
653                                         <0000 0 0 2 &gic 0 0 0 115 4>,
654                                         <0000 0 0 3 &gic 0 0 0 116 4>,
655                                         <0000 0 0 4 &gic 0 0 0 117 4>;
656                 };
657
658                 pcie3: pcie@3600000 {
659                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
660                                      "snps,dw-pcie";
661                         reg-names = "regs", "config";
662                         interrupts = <0 118 0x4>; /* Level high type */
663                         interrupt-names = "intr";
664                         #address-cells = <3>;
665                         #size-cells = <2>;
666                         device_type = "pci";
667                         dma-coherent;
668                         num-lanes = <8>;
669                         bus-range = <0x0 0xff>;
670                         msi-parent = <&its>;
671                         #interrupt-cells = <1>;
672                         interrupt-map-mask = <0 0 0 7>;
673                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
674                                         <0000 0 0 2 &gic 0 0 0 120 4>,
675                                         <0000 0 0 3 &gic 0 0 0 121 4>,
676                                         <0000 0 0 4 &gic 0 0 0 122 4>;
677                 };
678
679                 pcie4: pcie@3700000 {
680                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
681                                      "snps,dw-pcie";
682                         reg-names = "regs", "config";
683                         interrupts = <0 123 0x4>; /* Level high type */
684                         interrupt-names = "intr";
685                         #address-cells = <3>;
686                         #size-cells = <2>;
687                         device_type = "pci";
688                         dma-coherent;
689                         num-lanes = <4>;
690                         bus-range = <0x0 0xff>;
691                         msi-parent = <&its>;
692                         #interrupt-cells = <1>;
693                         interrupt-map-mask = <0 0 0 7>;
694                         interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
695                                         <0000 0 0 2 &gic 0 0 0 125 4>,
696                                         <0000 0 0 3 &gic 0 0 0 126 4>,
697                                         <0000 0 0 4 &gic 0 0 0 127 4>;
698                 };
699
700                 sata0: sata@3200000 {
701                         status = "disabled";
702                         compatible = "fsl,ls2080a-ahci";
703                         reg = <0x0 0x3200000 0x0 0x10000>;
704                         interrupts = <0 133 0x4>; /* Level high type */
705                         clocks = <&clockgen 4 3>;
706                         dma-coherent;
707                 };
708
709                 sata1: sata@3210000 {
710                         status = "disabled";
711                         compatible = "fsl,ls2080a-ahci";
712                         reg = <0x0 0x3210000 0x0 0x10000>;
713                         interrupts = <0 136 0x4>; /* Level high type */
714                         clocks = <&clockgen 4 3>;
715                         dma-coherent;
716                 };
717
718                 usb0: usb3@3100000 {
719                         status = "disabled";
720                         compatible = "snps,dwc3";
721                         reg = <0x0 0x3100000 0x0 0x10000>;
722                         interrupts = <0 80 0x4>; /* Level high type */
723                         dr_mode = "host";
724                         snps,quirk-frame-length-adjustment = <0x20>;
725                         snps,dis_rxdet_inp3_quirk;
726                 };
727
728                 usb1: usb3@3110000 {
729                         status = "disabled";
730                         compatible = "snps,dwc3";
731                         reg = <0x0 0x3110000 0x0 0x10000>;
732                         interrupts = <0 81 0x4>; /* Level high type */
733                         dr_mode = "host";
734                         snps,quirk-frame-length-adjustment = <0x20>;
735                         snps,dis_rxdet_inp3_quirk;
736                 };
737
738                 ccn@4000000 {
739                         compatible = "arm,ccn-504";
740                         reg = <0x0 0x04000000 0x0 0x01000000>;
741                         interrupts = <0 12 4>;
742                 };
743         };
744
745         ddr1: memory-controller@1080000 {
746                 compatible = "fsl,qoriq-memory-controller";
747                 reg = <0x0 0x1080000 0x0 0x1000>;
748                 interrupts = <0 17 0x4>;
749                 little-endian;
750         };
751
752         ddr2: memory-controller@1090000 {
753                 compatible = "fsl,qoriq-memory-controller";
754                 reg = <0x0 0x1090000 0x0 0x1000>;
755                 interrupts = <0 18 0x4>;
756                 little-endian;
757         };
758
759         firmware {
760                 optee {
761                         compatible = "linaro,optee-tz";
762                         method = "smc";
763                 };
764         };
765 };