Merge tag 'socfpga_updates_for_v4.20_part3' of git://git.kernel.org/pub/scm/linux...
[muen/linux.git] / arch / arm64 / boot / dts / freescale / fsl-ls208xa.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4  *
5  * Copyright 2016 Freescale Semiconductor, Inc.
6  * Copyright 2017 NXP
7  *
8  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9  *
10  */
11
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14
15 / {
16         compatible = "fsl,ls2080a";
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
20
21         aliases {
22                 crypto = &crypto;
23                 serial0 = &serial0;
24                 serial1 = &serial1;
25                 serial2 = &serial2;
26                 serial3 = &serial3;
27         };
28
29         cpu: cpus {
30                 #address-cells = <1>;
31                 #size-cells = <0>;
32         };
33
34         memory@80000000 {
35                 device_type = "memory";
36                 reg = <0x00000000 0x80000000 0 0x80000000>;
37                       /* DRAM space - 1, size : 2 GB DRAM */
38         };
39
40         sysclk: sysclk {
41                 compatible = "fixed-clock";
42                 #clock-cells = <0>;
43                 clock-frequency = <100000000>;
44                 clock-output-names = "sysclk";
45         };
46
47         gic: interrupt-controller@6000000 {
48                 compatible = "arm,gic-v3";
49                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
50                         <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
51                         <0x0 0x0c0c0000 0 0x2000>, /* GICC */
52                         <0x0 0x0c0d0000 0 0x1000>, /* GICH */
53                         <0x0 0x0c0e0000 0 0x20000>; /* GICV */
54                 #interrupt-cells = <3>;
55                 #address-cells = <2>;
56                 #size-cells = <2>;
57                 ranges;
58                 interrupt-controller;
59                 interrupts = <1 9 0x4>;
60
61                 its: gic-its@6020000 {
62                         compatible = "arm,gic-v3-its";
63                         msi-controller;
64                         reg = <0x0 0x6020000 0 0x20000>;
65                 };
66         };
67
68         rstcr: syscon@1e60000 {
69                 compatible = "fsl,ls2080a-rstcr", "syscon";
70                 reg = <0x0 0x1e60000 0x0 0x4>;
71         };
72
73         reboot {
74                 compatible ="syscon-reboot";
75                 regmap = <&rstcr>;
76                 offset = <0x0>;
77                 mask = <0x2>;
78         };
79
80         thermal-zones {
81                 cpu_thermal: cpu-thermal {
82                         polling-delay-passive = <1000>;
83                         polling-delay = <5000>;
84
85                         thermal-sensors = <&tmu 4>;
86
87                         trips {
88                                 cpu_alert: cpu-alert {
89                                         temperature = <75000>;
90                                         hysteresis = <2000>;
91                                         type = "passive";
92                                 };
93                                 cpu_crit: cpu-crit {
94                                         temperature = <85000>;
95                                         hysteresis = <2000>;
96                                         type = "critical";
97                                 };
98                         };
99
100                         cooling-maps {
101                                 map0 {
102                                         trip = <&cpu_alert>;
103                                         cooling-device =
104                                                 <&cpu0 THERMAL_NO_LIMIT
105                                                 THERMAL_NO_LIMIT>;
106                                 };
107                                 map1 {
108                                         trip = <&cpu_alert>;
109                                         cooling-device =
110                                                 <&cpu2 THERMAL_NO_LIMIT
111                                                 THERMAL_NO_LIMIT>;
112                                 };
113                                 map2 {
114                                         trip = <&cpu_alert>;
115                                         cooling-device =
116                                                 <&cpu4 THERMAL_NO_LIMIT
117                                                 THERMAL_NO_LIMIT>;
118                                 };
119                                 map3 {
120                                         trip = <&cpu_alert>;
121                                         cooling-device =
122                                                 <&cpu6 THERMAL_NO_LIMIT
123                                                 THERMAL_NO_LIMIT>;
124                                 };
125                         };
126                 };
127         };
128
129         timer {
130                 compatible = "arm,armv8-timer";
131                 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
132                              <1 14 4>, /* Physical Non-Secure PPI, active-low */
133                              <1 11 4>, /* Virtual PPI, active-low */
134                              <1 10 4>; /* Hypervisor PPI, active-low */
135                 fsl,erratum-a008585;
136         };
137
138         pmu {
139                 compatible = "arm,armv8-pmuv3";
140                 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
141         };
142
143         psci {
144                 compatible = "arm,psci-0.2";
145                 method = "smc";
146         };
147
148         soc {
149                 compatible = "simple-bus";
150                 #address-cells = <2>;
151                 #size-cells = <2>;
152                 ranges;
153
154                 clockgen: clocking@1300000 {
155                         compatible = "fsl,ls2080a-clockgen";
156                         reg = <0 0x1300000 0 0xa0000>;
157                         #clock-cells = <2>;
158                         clocks = <&sysclk>;
159                 };
160
161                 dcfg: dcfg@1e00000 {
162                         compatible = "fsl,ls2080a-dcfg", "syscon";
163                         reg = <0x0 0x1e00000 0x0 0x10000>;
164                         little-endian;
165                 };
166
167                 tmu: tmu@1f80000 {
168                         compatible = "fsl,qoriq-tmu";
169                         reg = <0x0 0x1f80000 0x0 0x10000>;
170                         interrupts = <0 23 0x4>;
171                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
172                         fsl,tmu-calibration = <0x00000000 0x00000026
173                                                0x00000001 0x0000002d
174                                                0x00000002 0x00000032
175                                                0x00000003 0x00000039
176                                                0x00000004 0x0000003f
177                                                0x00000005 0x00000046
178                                                0x00000006 0x0000004d
179                                                0x00000007 0x00000054
180                                                0x00000008 0x0000005a
181                                                0x00000009 0x00000061
182                                                0x0000000a 0x0000006a
183                                                0x0000000b 0x00000071
184
185                                                0x00010000 0x00000025
186                                                0x00010001 0x0000002c
187                                                0x00010002 0x00000035
188                                                0x00010003 0x0000003d
189                                                0x00010004 0x00000045
190                                                0x00010005 0x0000004e
191                                                0x00010006 0x00000057
192                                                0x00010007 0x00000061
193                                                0x00010008 0x0000006b
194                                                0x00010009 0x00000076
195
196                                                0x00020000 0x00000029
197                                                0x00020001 0x00000033
198                                                0x00020002 0x0000003d
199                                                0x00020003 0x00000049
200                                                0x00020004 0x00000056
201                                                0x00020005 0x00000061
202                                                0x00020006 0x0000006d
203
204                                                0x00030000 0x00000021
205                                                0x00030001 0x0000002a
206                                                0x00030002 0x0000003c
207                                                0x00030003 0x0000004e>;
208                         little-endian;
209                         #thermal-sensor-cells = <1>;
210                 };
211
212                 serial0: serial@21c0500 {
213                         compatible = "fsl,ns16550", "ns16550a";
214                         reg = <0x0 0x21c0500 0x0 0x100>;
215                         clocks = <&clockgen 4 3>;
216                         interrupts = <0 32 0x4>; /* Level high type */
217                 };
218
219                 serial1: serial@21c0600 {
220                         compatible = "fsl,ns16550", "ns16550a";
221                         reg = <0x0 0x21c0600 0x0 0x100>;
222                         clocks = <&clockgen 4 3>;
223                         interrupts = <0 32 0x4>; /* Level high type */
224                 };
225
226                 serial2: serial@21d0500 {
227                         compatible = "fsl,ns16550", "ns16550a";
228                         reg = <0x0 0x21d0500 0x0 0x100>;
229                         clocks = <&clockgen 4 3>;
230                         interrupts = <0 33 0x4>; /* Level high type */
231                 };
232
233                 serial3: serial@21d0600 {
234                         compatible = "fsl,ns16550", "ns16550a";
235                         reg = <0x0 0x21d0600 0x0 0x100>;
236                         clocks = <&clockgen 4 3>;
237                         interrupts = <0 33 0x4>; /* Level high type */
238                 };
239
240                 cluster1_core0_watchdog: wdt@c000000 {
241                         compatible = "arm,sp805-wdt", "arm,primecell";
242                         reg = <0x0 0xc000000 0x0 0x1000>;
243                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
244                         clock-names = "apb_pclk", "wdog_clk";
245                 };
246
247                 cluster1_core1_watchdog: wdt@c010000 {
248                         compatible = "arm,sp805-wdt", "arm,primecell";
249                         reg = <0x0 0xc010000 0x0 0x1000>;
250                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
251                         clock-names = "apb_pclk", "wdog_clk";
252                 };
253
254                 cluster2_core0_watchdog: wdt@c100000 {
255                         compatible = "arm,sp805-wdt", "arm,primecell";
256                         reg = <0x0 0xc100000 0x0 0x1000>;
257                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
258                         clock-names = "apb_pclk", "wdog_clk";
259                 };
260
261                 cluster2_core1_watchdog: wdt@c110000 {
262                         compatible = "arm,sp805-wdt", "arm,primecell";
263                         reg = <0x0 0xc110000 0x0 0x1000>;
264                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
265                         clock-names = "apb_pclk", "wdog_clk";
266                 };
267
268                 cluster3_core0_watchdog: wdt@c200000 {
269                         compatible = "arm,sp805-wdt", "arm,primecell";
270                         reg = <0x0 0xc200000 0x0 0x1000>;
271                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
272                         clock-names = "apb_pclk", "wdog_clk";
273                 };
274
275                 cluster3_core1_watchdog: wdt@c210000 {
276                         compatible = "arm,sp805-wdt", "arm,primecell";
277                         reg = <0x0 0xc210000 0x0 0x1000>;
278                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
279                         clock-names = "apb_pclk", "wdog_clk";
280                 };
281
282                 cluster4_core0_watchdog: wdt@c300000 {
283                         compatible = "arm,sp805-wdt", "arm,primecell";
284                         reg = <0x0 0xc300000 0x0 0x1000>;
285                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
286                         clock-names = "apb_pclk", "wdog_clk";
287                 };
288
289                 cluster4_core1_watchdog: wdt@c310000 {
290                         compatible = "arm,sp805-wdt", "arm,primecell";
291                         reg = <0x0 0xc310000 0x0 0x1000>;
292                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
293                         clock-names = "apb_pclk", "wdog_clk";
294                 };
295
296                 crypto: crypto@8000000 {
297                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
298                         fsl,sec-era = <8>;
299                         #address-cells = <1>;
300                         #size-cells = <1>;
301                         ranges = <0x0 0x00 0x8000000 0x100000>;
302                         reg = <0x00 0x8000000 0x0 0x100000>;
303                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
304                         dma-coherent;
305
306                         sec_jr0: jr@10000 {
307                                 compatible = "fsl,sec-v5.0-job-ring",
308                                              "fsl,sec-v4.0-job-ring";
309                                 reg        = <0x10000 0x10000>;
310                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
311                         };
312
313                         sec_jr1: jr@20000 {
314                                 compatible = "fsl,sec-v5.0-job-ring",
315                                              "fsl,sec-v4.0-job-ring";
316                                 reg        = <0x20000 0x10000>;
317                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
318                         };
319
320                         sec_jr2: jr@30000 {
321                                 compatible = "fsl,sec-v5.0-job-ring",
322                                              "fsl,sec-v4.0-job-ring";
323                                 reg        = <0x30000 0x10000>;
324                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
325                         };
326
327                         sec_jr3: jr@40000 {
328                                 compatible = "fsl,sec-v5.0-job-ring",
329                                              "fsl,sec-v4.0-job-ring";
330                                 reg        = <0x40000 0x10000>;
331                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
332                         };
333                 };
334
335                 fsl_mc: fsl-mc@80c000000 {
336                         compatible = "fsl,qoriq-mc";
337                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
338                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
339                         msi-parent = <&its>;
340                         #address-cells = <3>;
341                         #size-cells = <1>;
342
343                         /*
344                          * Region type 0x0 - MC portals
345                          * Region type 0x1 - QBMAN portals
346                          */
347                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
348                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
349
350                         /*
351                          * Define the maximum number of MACs present on the SoC.
352                          */
353                         dpmacs {
354                                 #address-cells = <1>;
355                                 #size-cells = <0>;
356
357                                 dpmac1: dpmac@1 {
358                                         compatible = "fsl,qoriq-mc-dpmac";
359                                         reg = <0x1>;
360                                 };
361
362                                 dpmac2: dpmac@2 {
363                                         compatible = "fsl,qoriq-mc-dpmac";
364                                         reg = <0x2>;
365                                 };
366
367                                 dpmac3: dpmac@3 {
368                                         compatible = "fsl,qoriq-mc-dpmac";
369                                         reg = <0x3>;
370                                 };
371
372                                 dpmac4: dpmac@4 {
373                                         compatible = "fsl,qoriq-mc-dpmac";
374                                         reg = <0x4>;
375                                 };
376
377                                 dpmac5: dpmac@5 {
378                                         compatible = "fsl,qoriq-mc-dpmac";
379                                         reg = <0x5>;
380                                 };
381
382                                 dpmac6: dpmac@6 {
383                                         compatible = "fsl,qoriq-mc-dpmac";
384                                         reg = <0x6>;
385                                 };
386
387                                 dpmac7: dpmac@7 {
388                                         compatible = "fsl,qoriq-mc-dpmac";
389                                         reg = <0x7>;
390                                 };
391
392                                 dpmac8: dpmac@8 {
393                                         compatible = "fsl,qoriq-mc-dpmac";
394                                         reg = <0x8>;
395                                 };
396
397                                 dpmac9: dpmac@9 {
398                                         compatible = "fsl,qoriq-mc-dpmac";
399                                         reg = <0x9>;
400                                 };
401
402                                 dpmac10: dpmac@a {
403                                         compatible = "fsl,qoriq-mc-dpmac";
404                                         reg = <0xa>;
405                                 };
406
407                                 dpmac11: dpmac@b {
408                                         compatible = "fsl,qoriq-mc-dpmac";
409                                         reg = <0xb>;
410                                 };
411
412                                 dpmac12: dpmac@c {
413                                         compatible = "fsl,qoriq-mc-dpmac";
414                                         reg = <0xc>;
415                                 };
416
417                                 dpmac13: dpmac@d {
418                                         compatible = "fsl,qoriq-mc-dpmac";
419                                         reg = <0xd>;
420                                 };
421
422                                 dpmac14: dpmac@e {
423                                         compatible = "fsl,qoriq-mc-dpmac";
424                                         reg = <0xe>;
425                                 };
426
427                                 dpmac15: dpmac@f {
428                                         compatible = "fsl,qoriq-mc-dpmac";
429                                         reg = <0xf>;
430                                 };
431
432                                 dpmac16: dpmac@10 {
433                                         compatible = "fsl,qoriq-mc-dpmac";
434                                         reg = <0x10>;
435                                 };
436                         };
437                 };
438
439                 smmu: iommu@5000000 {
440                         compatible = "arm,mmu-500";
441                         reg = <0 0x5000000 0 0x800000>;
442                         #global-interrupts = <12>;
443                         interrupts = <0 13 4>, /* global secure fault */
444                                      <0 14 4>, /* combined secure interrupt */
445                                      <0 15 4>, /* global non-secure fault */
446                                      <0 16 4>, /* combined non-secure interrupt */
447                                 /* performance counter interrupts 0-7 */
448                                      <0 211 4>, <0 212 4>,
449                                      <0 213 4>, <0 214 4>,
450                                      <0 215 4>, <0 216 4>,
451                                      <0 217 4>, <0 218 4>,
452                                 /* per context interrupt, 64 interrupts */
453                                      <0 146 4>, <0 147 4>,
454                                      <0 148 4>, <0 149 4>,
455                                      <0 150 4>, <0 151 4>,
456                                      <0 152 4>, <0 153 4>,
457                                      <0 154 4>, <0 155 4>,
458                                      <0 156 4>, <0 157 4>,
459                                      <0 158 4>, <0 159 4>,
460                                      <0 160 4>, <0 161 4>,
461                                      <0 162 4>, <0 163 4>,
462                                      <0 164 4>, <0 165 4>,
463                                      <0 166 4>, <0 167 4>,
464                                      <0 168 4>, <0 169 4>,
465                                      <0 170 4>, <0 171 4>,
466                                      <0 172 4>, <0 173 4>,
467                                      <0 174 4>, <0 175 4>,
468                                      <0 176 4>, <0 177 4>,
469                                      <0 178 4>, <0 179 4>,
470                                      <0 180 4>, <0 181 4>,
471                                      <0 182 4>, <0 183 4>,
472                                      <0 184 4>, <0 185 4>,
473                                      <0 186 4>, <0 187 4>,
474                                      <0 188 4>, <0 189 4>,
475                                      <0 190 4>, <0 191 4>,
476                                      <0 192 4>, <0 193 4>,
477                                      <0 194 4>, <0 195 4>,
478                                      <0 196 4>, <0 197 4>,
479                                      <0 198 4>, <0 199 4>,
480                                      <0 200 4>, <0 201 4>,
481                                      <0 202 4>, <0 203 4>,
482                                      <0 204 4>, <0 205 4>,
483                                      <0 206 4>, <0 207 4>,
484                                      <0 208 4>, <0 209 4>;
485                         mmu-masters = <&fsl_mc 0x300 0>;
486                 };
487
488                 dspi: spi@2100000 {
489                         status = "disabled";
490                         compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
491                         #address-cells = <1>;
492                         #size-cells = <0>;
493                         reg = <0x0 0x2100000 0x0 0x10000>;
494                         interrupts = <0 26 0x4>; /* Level high type */
495                         clocks = <&clockgen 4 3>;
496                         clock-names = "dspi";
497                         spi-num-chipselects = <5>;
498                         bus-num = <0>;
499                 };
500
501                 esdhc: esdhc@2140000 {
502                         status = "disabled";
503                         compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
504                         reg = <0x0 0x2140000 0x0 0x10000>;
505                         interrupts = <0 28 0x4>; /* Level high type */
506                         clocks = <&clockgen 4 1>;
507                         voltage-ranges = <1800 1800 3300 3300>;
508                         sdhci,auto-cmd12;
509                         little-endian;
510                         bus-width = <4>;
511                 };
512
513                 gpio0: gpio@2300000 {
514                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
515                         reg = <0x0 0x2300000 0x0 0x10000>;
516                         interrupts = <0 36 0x4>; /* Level high type */
517                         gpio-controller;
518                         little-endian;
519                         #gpio-cells = <2>;
520                         interrupt-controller;
521                         #interrupt-cells = <2>;
522                 };
523
524                 gpio1: gpio@2310000 {
525                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
526                         reg = <0x0 0x2310000 0x0 0x10000>;
527                         interrupts = <0 36 0x4>; /* Level high type */
528                         gpio-controller;
529                         little-endian;
530                         #gpio-cells = <2>;
531                         interrupt-controller;
532                         #interrupt-cells = <2>;
533                 };
534
535                 gpio2: gpio@2320000 {
536                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
537                         reg = <0x0 0x2320000 0x0 0x10000>;
538                         interrupts = <0 37 0x4>; /* Level high type */
539                         gpio-controller;
540                         little-endian;
541                         #gpio-cells = <2>;
542                         interrupt-controller;
543                         #interrupt-cells = <2>;
544                 };
545
546                 gpio3: gpio@2330000 {
547                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
548                         reg = <0x0 0x2330000 0x0 0x10000>;
549                         interrupts = <0 37 0x4>; /* Level high type */
550                         gpio-controller;
551                         little-endian;
552                         #gpio-cells = <2>;
553                         interrupt-controller;
554                         #interrupt-cells = <2>;
555                 };
556
557                 i2c0: i2c@2000000 {
558                         status = "disabled";
559                         compatible = "fsl,vf610-i2c";
560                         #address-cells = <1>;
561                         #size-cells = <0>;
562                         reg = <0x0 0x2000000 0x0 0x10000>;
563                         interrupts = <0 34 0x4>; /* Level high type */
564                         clock-names = "i2c";
565                         clocks = <&clockgen 4 3>;
566                 };
567
568                 i2c1: i2c@2010000 {
569                         status = "disabled";
570                         compatible = "fsl,vf610-i2c";
571                         #address-cells = <1>;
572                         #size-cells = <0>;
573                         reg = <0x0 0x2010000 0x0 0x10000>;
574                         interrupts = <0 34 0x4>; /* Level high type */
575                         clock-names = "i2c";
576                         clocks = <&clockgen 4 3>;
577                 };
578
579                 i2c2: i2c@2020000 {
580                         status = "disabled";
581                         compatible = "fsl,vf610-i2c";
582                         #address-cells = <1>;
583                         #size-cells = <0>;
584                         reg = <0x0 0x2020000 0x0 0x10000>;
585                         interrupts = <0 35 0x4>; /* Level high type */
586                         clock-names = "i2c";
587                         clocks = <&clockgen 4 3>;
588                 };
589
590                 i2c3: i2c@2030000 {
591                         status = "disabled";
592                         compatible = "fsl,vf610-i2c";
593                         #address-cells = <1>;
594                         #size-cells = <0>;
595                         reg = <0x0 0x2030000 0x0 0x10000>;
596                         interrupts = <0 35 0x4>; /* Level high type */
597                         clock-names = "i2c";
598                         clocks = <&clockgen 4 3>;
599                 };
600
601                 ifc: ifc@2240000 {
602                         compatible = "fsl,ifc", "simple-bus";
603                         reg = <0x0 0x2240000 0x0 0x20000>;
604                         interrupts = <0 21 0x4>; /* Level high type */
605                         little-endian;
606                         #address-cells = <2>;
607                         #size-cells = <1>;
608
609                         ranges = <0 0 0x5 0x80000000 0x08000000
610                                   2 0 0x5 0x30000000 0x00010000
611                                   3 0 0x5 0x20000000 0x00010000>;
612                 };
613
614                 qspi: spi@20c0000 {
615                         status = "disabled";
616                         compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
617                         #address-cells = <1>;
618                         #size-cells = <0>;
619                         reg = <0x0 0x20c0000 0x0 0x10000>,
620                               <0x0 0x20000000 0x0 0x10000000>;
621                         reg-names = "QuadSPI", "QuadSPI-memory";
622                         interrupts = <0 25 0x4>; /* Level high type */
623                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
624                         clock-names = "qspi_en", "qspi";
625                 };
626
627                 pcie1: pcie@3400000 {
628                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
629                                      "snps,dw-pcie";
630                         reg-names = "regs", "config";
631                         interrupts = <0 108 0x4>; /* Level high type */
632                         interrupt-names = "intr";
633                         #address-cells = <3>;
634                         #size-cells = <2>;
635                         device_type = "pci";
636                         dma-coherent;
637                         num-lanes = <4>;
638                         bus-range = <0x0 0xff>;
639                         msi-parent = <&its>;
640                         #interrupt-cells = <1>;
641                         interrupt-map-mask = <0 0 0 7>;
642                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
643                                         <0000 0 0 2 &gic 0 0 0 110 4>,
644                                         <0000 0 0 3 &gic 0 0 0 111 4>,
645                                         <0000 0 0 4 &gic 0 0 0 112 4>;
646                 };
647
648                 pcie2: pcie@3500000 {
649                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
650                                      "snps,dw-pcie";
651                         reg-names = "regs", "config";
652                         interrupts = <0 113 0x4>; /* Level high type */
653                         interrupt-names = "intr";
654                         #address-cells = <3>;
655                         #size-cells = <2>;
656                         device_type = "pci";
657                         dma-coherent;
658                         num-lanes = <4>;
659                         bus-range = <0x0 0xff>;
660                         msi-parent = <&its>;
661                         #interrupt-cells = <1>;
662                         interrupt-map-mask = <0 0 0 7>;
663                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
664                                         <0000 0 0 2 &gic 0 0 0 115 4>,
665                                         <0000 0 0 3 &gic 0 0 0 116 4>,
666                                         <0000 0 0 4 &gic 0 0 0 117 4>;
667                 };
668
669                 pcie3: pcie@3600000 {
670                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
671                                      "snps,dw-pcie";
672                         reg-names = "regs", "config";
673                         interrupts = <0 118 0x4>; /* Level high type */
674                         interrupt-names = "intr";
675                         #address-cells = <3>;
676                         #size-cells = <2>;
677                         device_type = "pci";
678                         dma-coherent;
679                         num-lanes = <8>;
680                         bus-range = <0x0 0xff>;
681                         msi-parent = <&its>;
682                         #interrupt-cells = <1>;
683                         interrupt-map-mask = <0 0 0 7>;
684                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
685                                         <0000 0 0 2 &gic 0 0 0 120 4>,
686                                         <0000 0 0 3 &gic 0 0 0 121 4>,
687                                         <0000 0 0 4 &gic 0 0 0 122 4>;
688                 };
689
690                 pcie4: pcie@3700000 {
691                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
692                                      "snps,dw-pcie";
693                         reg-names = "regs", "config";
694                         interrupts = <0 123 0x4>; /* Level high type */
695                         interrupt-names = "intr";
696                         #address-cells = <3>;
697                         #size-cells = <2>;
698                         device_type = "pci";
699                         dma-coherent;
700                         num-lanes = <4>;
701                         bus-range = <0x0 0xff>;
702                         msi-parent = <&its>;
703                         #interrupt-cells = <1>;
704                         interrupt-map-mask = <0 0 0 7>;
705                         interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
706                                         <0000 0 0 2 &gic 0 0 0 125 4>,
707                                         <0000 0 0 3 &gic 0 0 0 126 4>,
708                                         <0000 0 0 4 &gic 0 0 0 127 4>;
709                 };
710
711                 sata0: sata@3200000 {
712                         status = "disabled";
713                         compatible = "fsl,ls2080a-ahci";
714                         reg = <0x0 0x3200000 0x0 0x10000>;
715                         interrupts = <0 133 0x4>; /* Level high type */
716                         clocks = <&clockgen 4 3>;
717                         dma-coherent;
718                 };
719
720                 sata1: sata@3210000 {
721                         status = "disabled";
722                         compatible = "fsl,ls2080a-ahci";
723                         reg = <0x0 0x3210000 0x0 0x10000>;
724                         interrupts = <0 136 0x4>; /* Level high type */
725                         clocks = <&clockgen 4 3>;
726                         dma-coherent;
727                 };
728
729                 usb0: usb3@3100000 {
730                         status = "disabled";
731                         compatible = "snps,dwc3";
732                         reg = <0x0 0x3100000 0x0 0x10000>;
733                         interrupts = <0 80 0x4>; /* Level high type */
734                         dr_mode = "host";
735                         snps,quirk-frame-length-adjustment = <0x20>;
736                         snps,dis_rxdet_inp3_quirk;
737                 };
738
739                 usb1: usb3@3110000 {
740                         status = "disabled";
741                         compatible = "snps,dwc3";
742                         reg = <0x0 0x3110000 0x0 0x10000>;
743                         interrupts = <0 81 0x4>; /* Level high type */
744                         dr_mode = "host";
745                         snps,quirk-frame-length-adjustment = <0x20>;
746                         snps,dis_rxdet_inp3_quirk;
747                 };
748
749                 ccn@4000000 {
750                         compatible = "arm,ccn-504";
751                         reg = <0x0 0x04000000 0x0 0x01000000>;
752                         interrupts = <0 12 4>;
753                 };
754         };
755
756         ddr1: memory-controller@1080000 {
757                 compatible = "fsl,qoriq-memory-controller";
758                 reg = <0x0 0x1080000 0x0 0x1000>;
759                 interrupts = <0 17 0x4>;
760                 little-endian;
761         };
762
763         ddr2: memory-controller@1090000 {
764                 compatible = "fsl,qoriq-memory-controller";
765                 reg = <0x0 0x1090000 0x0 0x1000>;
766                 interrupts = <0 18 0x4>;
767                 little-endian;
768         };
769
770         firmware {
771                 optee {
772                         compatible = "linaro,optee-tz";
773                         method = "smc";
774                 };
775         };
776 };