arm64: dts: imx8mq-evk: enable watchdog
[muen/linux.git] / arch / arm64 / boot / dts / freescale / imx8mq-evk.dts
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Copyright 2017 NXP
4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5  */
6
7 /dts-v1/;
8
9 #include "imx8mq.dtsi"
10
11 / {
12         model = "NXP i.MX8MQ EVK";
13         compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15         chosen {
16                 stdout-path = &uart1;
17         };
18
19         memory@40000000 {
20                 device_type = "memory";
21                 reg = <0x00000000 0x40000000 0 0xc0000000>;
22         };
23
24         reg_usdhc2_vmmc: regulator-vsd-3v3 {
25                 pinctrl-names = "default";
26                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
27                 compatible = "regulator-fixed";
28                 regulator-name = "VSD_3V3";
29                 regulator-min-microvolt = <3300000>;
30                 regulator-max-microvolt = <3300000>;
31                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32                 enable-active-high;
33         };
34 };
35
36 &fec1 {
37         pinctrl-names = "default";
38         pinctrl-0 = <&pinctrl_fec1>;
39         phy-mode = "rgmii-id";
40         status = "okay";
41 };
42
43 &i2c1 {
44         clock-frequency = <100000>;
45         pinctrl-names = "default";
46         pinctrl-0 = <&pinctrl_i2c1>;
47         status = "okay";
48
49         pmic@8 {
50                 compatible = "fsl,pfuze100";
51                 reg = <0x8>;
52
53                 regulators {
54                         sw1a_reg: sw1ab {
55                                 regulator-min-microvolt = <825000>;
56                                 regulator-max-microvolt = <1100000>;
57                         };
58
59                         sw1c_reg: sw1c {
60                                 regulator-min-microvolt = <825000>;
61                                 regulator-max-microvolt = <1100000>;
62                         };
63
64                         sw2_reg: sw2 {
65                                 regulator-min-microvolt = <1100000>;
66                                 regulator-max-microvolt = <1100000>;
67                                 regulator-always-on;
68                         };
69
70                         sw3a_reg: sw3ab {
71                                 regulator-min-microvolt = <825000>;
72                                 regulator-max-microvolt = <1100000>;
73                                 regulator-always-on;
74                         };
75
76                         sw4_reg: sw4 {
77                                 regulator-min-microvolt = <1800000>;
78                                 regulator-max-microvolt = <1800000>;
79                                 regulator-always-on;
80                         };
81
82                         swbst_reg: swbst {
83                                 regulator-min-microvolt = <5000000>;
84                                 regulator-max-microvolt = <5150000>;
85                         };
86
87                         snvs_reg: vsnvs {
88                                 regulator-min-microvolt = <1000000>;
89                                 regulator-max-microvolt = <3000000>;
90                                 regulator-always-on;
91                         };
92
93                         vref_reg: vrefddr {
94                                 regulator-always-on;
95                         };
96
97                         vgen1_reg: vgen1 {
98                                 regulator-min-microvolt = <800000>;
99                                 regulator-max-microvolt = <1550000>;
100                         };
101
102                         vgen2_reg: vgen2 {
103                                 regulator-min-microvolt = <850000>;
104                                 regulator-max-microvolt = <975000>;
105                                 regulator-always-on;
106                         };
107
108                         vgen3_reg: vgen3 {
109                                 regulator-min-microvolt = <1675000>;
110                                 regulator-max-microvolt = <1975000>;
111                                 regulator-always-on;
112                         };
113
114                         vgen4_reg: vgen4 {
115                                 regulator-min-microvolt = <1625000>;
116                                 regulator-max-microvolt = <1875000>;
117                                 regulator-always-on;
118                         };
119
120                         vgen5_reg: vgen5 {
121                                 regulator-min-microvolt = <3075000>;
122                                 regulator-max-microvolt = <3625000>;
123                                 regulator-always-on;
124                         };
125
126                         vgen6_reg: vgen6 {
127                                 regulator-min-microvolt = <1800000>;
128                                 regulator-max-microvolt = <3300000>;
129                         };
130                 };
131         };
132 };
133
134 &uart1 {
135         pinctrl-names = "default";
136         pinctrl-0 = <&pinctrl_uart1>;
137         status = "okay";
138 };
139
140 &usdhc1 {
141         pinctrl-names = "default", "state_100mhz", "state_200mhz";
142         pinctrl-0 = <&pinctrl_usdhc1>;
143         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
144         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
145         vqmmc-supply = <&sw4_reg>;
146         bus-width = <8>;
147         non-removable;
148         no-sd;
149         no-sdio;
150         status = "okay";
151 };
152
153 &usdhc2 {
154         pinctrl-names = "default", "state_100mhz", "state_200mhz";
155         pinctrl-0 = <&pinctrl_usdhc2>;
156         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
157         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
158         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
159         vmmc-supply = <&reg_usdhc2_vmmc>;
160         status = "okay";
161 };
162
163 &wdog1 {
164         pinctrl-names = "default";
165         pinctrl-0 = <&pinctrl_wdog>;
166         fsl,ext-reset-output;
167         status = "okay";
168 };
169
170 &iomuxc {
171         pinctrl_fec1: fec1grp {
172                 fsl,pins = <
173                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
174                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
175                         MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
176                         MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
177                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
178                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
179                         MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
180                         MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
181                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
182                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
183                         MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
184                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
185                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
186                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
187                         MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
188                 >;
189         };
190
191         pinctrl_i2c1: i2c1grp {
192                 fsl,pins = <
193                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
194                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
195                 >;
196         };
197
198         pinctrl_reg_usdhc2: regusdhc2grpgpio {
199                 fsl,pins = <
200                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
201                 >;
202         };
203
204         pinctrl_uart1: uart1grp {
205                 fsl,pins = <
206                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
207                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
208                 >;
209         };
210
211         pinctrl_usdhc1: usdhc1grp {
212                 fsl,pins = <
213                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
214                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
215                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
216                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
217                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
218                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
219                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
220                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
221                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
222                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
223                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
224                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
225                 >;
226         };
227
228         pinctrl_usdhc1_100mhz: usdhc1-100grp {
229                 fsl,pins = <
230                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x85
231                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc5
232                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc5
233                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc5
234                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc5
235                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc5
236                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc5
237                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc5
238                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc5
239                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc5
240                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x85
241                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
242                 >;
243         };
244
245         pinctrl_usdhc1_200mhz: usdhc1-200grp {
246                 fsl,pins = <
247                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x87
248                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc7
249                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc7
250                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc7
251                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc7
252                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc7
253                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc7
254                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc7
255                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc7
256                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc7
257                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x87
258                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
259                 >;
260         };
261
262         pinctrl_usdhc2: usdhc2grp {
263                 fsl,pins = <
264                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
265                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
266                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
267                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
268                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
269                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
270                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
271                 >;
272         };
273
274         pinctrl_usdhc2_100mhz: usdhc2-100grp {
275                 fsl,pins = <
276                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
277                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
278                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
279                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
280                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
281                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
282                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
283                 >;
284         };
285
286         pinctrl_usdhc2_200mhz: usdhc2-200grp {
287                 fsl,pins = <
288                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
289                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
290                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
291                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
292                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
293                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
294                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
295                 >;
296         };
297
298         pinctrl_wdog: wdog1grp {
299                 fsl,pins = <
300                         MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
301                 >;
302         };
303 };