arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
[muen/linux.git] / arch / arm64 / boot / dts / hisilicon / hi3670.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * dts file for Hisilicon Hi3670 SoC
4  *
5  * Copyright (C) 2016, Hisilicon Ltd.
6  * Copyright (C) 2018, Linaro Ltd.
7  */
8
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
11
12 / {
13         compatible = "hisilicon,hi3670";
14         interrupt-parent = <&gic>;
15         #address-cells = <2>;
16         #size-cells = <2>;
17
18         psci {
19                 compatible = "arm,psci-0.2";
20                 method = "smc";
21         };
22
23         cpus {
24                 #address-cells = <2>;
25                 #size-cells = <0>;
26
27                 cpu-map {
28                         cluster0 {
29                                 core0 {
30                                         cpu = <&cpu0>;
31                                 };
32                                 core1 {
33                                         cpu = <&cpu1>;
34                                 };
35                                 core2 {
36                                         cpu = <&cpu2>;
37                                 };
38                                 core3 {
39                                         cpu = <&cpu3>;
40                                 };
41                         };
42                         cluster1 {
43                                 core0 {
44                                         cpu = <&cpu4>;
45                                 };
46                                 core1 {
47                                         cpu = <&cpu5>;
48                                 };
49                                 core2 {
50                                         cpu = <&cpu6>;
51                                 };
52                                 core3 {
53                                         cpu = <&cpu7>;
54                                 };
55                         };
56                 };
57
58                 cpu0: cpu@0 {
59                         compatible = "arm,cortex-a53", "arm,armv8";
60                         device_type = "cpu";
61                         reg = <0x0 0x0>;
62                         enable-method = "psci";
63                 };
64
65                 cpu1: cpu@1 {
66                         compatible = "arm,cortex-a53", "arm,armv8";
67                         device_type = "cpu";
68                         reg = <0x0 0x1>;
69                         enable-method = "psci";
70                 };
71
72                 cpu2: cpu@2 {
73                         compatible = "arm,cortex-a53", "arm,armv8";
74                         device_type = "cpu";
75                         reg = <0x0 0x2>;
76                         enable-method = "psci";
77                 };
78
79                 cpu3: cpu@3 {
80                         compatible = "arm,cortex-a53", "arm,armv8";
81                         device_type = "cpu";
82                         reg = <0x0 0x3>;
83                         enable-method = "psci";
84                 };
85
86                 cpu4: cpu@100 {
87                         compatible = "arm,cortex-a73", "arm,armv8";
88                         device_type = "cpu";
89                         reg = <0x0 0x100>;
90                         enable-method = "psci";
91                 };
92
93                 cpu5: cpu@101 {
94                         compatible = "arm,cortex-a73", "arm,armv8";
95                         device_type = "cpu";
96                         reg = <0x0 0x101>;
97                         enable-method = "psci";
98                 };
99
100                 cpu6: cpu@102 {
101                         compatible = "arm,cortex-a73", "arm,armv8";
102                         device_type = "cpu";
103                         reg = <0x0 0x102>;
104                         enable-method = "psci";
105                 };
106
107                 cpu7: cpu@103 {
108                         compatible = "arm,cortex-a73", "arm,armv8";
109                         device_type = "cpu";
110                         reg = <0x0 0x103>;
111                         enable-method = "psci";
112                 };
113         };
114
115         gic: interrupt-controller@e82b0000 {
116                 compatible = "arm,gic-400";
117                 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
118                       <0x0 0xe82b2000 0 0x2000>, /* GICC */
119                       <0x0 0xe82b4000 0 0x2000>, /* GICH */
120                       <0x0 0xe82b6000 0 0x2000>; /* GICV */
121                 #interrupt-cells = <3>;
122                 #address-cells = <0>;
123                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
124                                          IRQ_TYPE_LEVEL_HIGH)>;
125                 interrupt-controller;
126         };
127
128         timer {
129                 compatible = "arm,armv8-timer";
130                 interrupt-parent = <&gic>;
131                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
132                                           IRQ_TYPE_LEVEL_LOW)>,
133                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
134                                           IRQ_TYPE_LEVEL_LOW)>,
135                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
136                                           IRQ_TYPE_LEVEL_LOW)>,
137                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
138                                           IRQ_TYPE_LEVEL_LOW)>;
139                 clock-frequency = <1920000>;
140         };
141
142         soc {
143                 compatible = "simple-bus";
144                 #address-cells = <2>;
145                 #size-cells = <2>;
146                 ranges;
147
148                 crg_ctrl: crg_ctrl@fff35000 {
149                         compatible = "hisilicon,hi3670-crgctrl", "syscon";
150                         reg = <0x0 0xfff35000 0x0 0x1000>;
151                         #clock-cells = <1>;
152                 };
153
154                 pctrl: pctrl@e8a09000 {
155                         compatible = "hisilicon,hi3670-pctrl", "syscon";
156                         reg = <0x0 0xe8a09000 0x0 0x1000>;
157                         #clock-cells = <1>;
158                 };
159
160                 pmuctrl: crg_ctrl@fff34000 {
161                         compatible = "hisilicon,hi3670-pmuctrl", "syscon";
162                         reg = <0x0 0xfff34000 0x0 0x1000>;
163                         #clock-cells = <1>;
164                 };
165
166                 sctrl: sctrl@fff0a000 {
167                         compatible = "hisilicon,hi3670-sctrl", "syscon";
168                         reg = <0x0 0xfff0a000 0x0 0x1000>;
169                         #clock-cells = <1>;
170                 };
171
172                 iomcu: iomcu@ffd7e000 {
173                         compatible = "hisilicon,hi3670-iomcu", "syscon";
174                         reg = <0x0 0xffd7e000 0x0 0x1000>;
175                         #clock-cells = <1>;
176                 };
177
178                 media1_crg: media1_crgctrl@e87ff000 {
179                         compatible = "hisilicon,hi3670-media1-crg", "syscon";
180                         reg = <0x0 0xe87ff000 0x0 0x1000>;
181                         #clock-cells = <1>;
182                 };
183
184                 media2_crg: media2_crgctrl@e8900000 {
185                         compatible = "hisilicon,hi3670-media2-crg","syscon";
186                         reg = <0x0 0xe8900000 0x0 0x1000>;
187                         #clock-cells = <1>;
188                 };
189
190                 uart6_clk: clk_19_2M {
191                         compatible = "fixed-clock";
192                         #clock-cells = <0>;
193                         clock-frequency = <19200000>;
194                 };
195
196                 uart6: serial@fff32000 {
197                         compatible = "arm,pl011", "arm,primecell";
198                         reg = <0x0 0xfff32000 0x0 0x1000>;
199                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
200                         clocks = <&uart6_clk &uart6_clk>;
201                         clock-names = "uartclk", "apb_pclk";
202                         status = "disabled";
203                 };
204         };
205 };