Merge tag 'v4.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[muen/linux.git] / arch / arm64 / boot / dts / hisilicon / hi3798cv200.dtsi
1 /*
2  * DTS File for HiSilicon Hi3798cv200 SoC.
3  *
4  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
5  *
6  * Released under the GPLv2 only.
7  * SPDX-License-Identifier: GPL-2.0
8  */
9
10 #include <dt-bindings/clock/histb-clock.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/ti-syscon.h>
13
14 / {
15         compatible = "hisilicon,hi3798cv200";
16         interrupt-parent = <&gic>;
17         #address-cells = <2>;
18         #size-cells = <2>;
19
20         psci {
21                 compatible = "arm,psci-0.2";
22                 method = "smc";
23         };
24
25         cpus {
26                 #address-cells = <2>;
27                 #size-cells = <0>;
28
29                 cpu@0 {
30                         compatible = "arm,cortex-a53";
31                         device_type = "cpu";
32                         reg = <0x0 0x0>;
33                         enable-method = "psci";
34                 };
35
36                 cpu@1 {
37                         compatible = "arm,cortex-a53";
38                         device_type = "cpu";
39                         reg = <0x0 0x1>;
40                         enable-method = "psci";
41                 };
42
43                 cpu@2 {
44                         compatible = "arm,cortex-a53";
45                         device_type = "cpu";
46                         reg = <0x0 0x2>;
47                         enable-method = "psci";
48                 };
49
50                 cpu@3 {
51                         compatible = "arm,cortex-a53";
52                         device_type = "cpu";
53                         reg = <0x0 0x3>;
54                         enable-method = "psci";
55                 };
56         };
57
58         gic: interrupt-controller@f1001000 {
59                 compatible = "arm,gic-400";
60                 reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
61                       <0x0 0xf1002000 0x0 0x100>;   /* GICC */
62                 #address-cells = <0>;
63                 #interrupt-cells = <3>;
64                 interrupt-controller;
65         };
66
67         timer {
68                 compatible = "arm,armv8-timer";
69                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
70                               IRQ_TYPE_LEVEL_LOW)>,
71                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
72                               IRQ_TYPE_LEVEL_LOW)>,
73                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
74                               IRQ_TYPE_LEVEL_LOW)>,
75                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
76                               IRQ_TYPE_LEVEL_LOW)>;
77         };
78
79         soc: soc@f0000000 {
80                 compatible = "simple-bus";
81                 #address-cells = <1>;
82                 #size-cells = <1>;
83                 ranges = <0x0 0x0 0xf0000000 0x10000000>;
84
85                 crg: clock-reset-controller@8a22000 {
86                         compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
87                         reg = <0x8a22000 0x1000>;
88                         #clock-cells = <1>;
89                         #reset-cells = <2>;
90
91                         gmacphyrst: reset-controller {
92                                 compatible = "ti,syscon-reset";
93                                 #reset-cells = <1>;
94                                 ti,reset-bits =
95                                         <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
96                                          DEASSERT_SET|STATUS_NONE)>,
97                                         <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
98                                          DEASSERT_SET|STATUS_NONE)>;
99                         };
100                 };
101
102                 sysctrl: system-controller@8000000 {
103                         compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
104                         reg = <0x8000000 0x1000>;
105                         #clock-cells = <1>;
106                         #reset-cells = <2>;
107                 };
108
109                 uart0: serial@8b00000 {
110                         compatible = "arm,pl011", "arm,primecell";
111                         reg = <0x8b00000 0x1000>;
112                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
113                         clocks = <&sysctrl HISTB_UART0_CLK>;
114                         clock-names = "apb_pclk";
115                         status = "disabled";
116                 };
117
118                 uart2: serial@8b02000 {
119                         compatible = "arm,pl011", "arm,primecell";
120                         reg = <0x8b02000 0x1000>;
121                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
122                         clocks = <&crg HISTB_UART2_CLK>;
123                         clock-names = "apb_pclk";
124                         status = "disabled";
125                 };
126
127                 i2c0: i2c@8b10000 {
128                         compatible = "hisilicon,hix5hd2-i2c";
129                         reg = <0x8b10000 0x1000>;
130                         #address-cells = <1>;
131                         #size-cells = <0>;
132                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
133                         clock-frequency = <400000>;
134                         clocks = <&crg HISTB_I2C0_CLK>;
135                         status = "disabled";
136                 };
137
138                 i2c1: i2c@8b11000 {
139                         compatible = "hisilicon,hix5hd2-i2c";
140                         reg = <0x8b11000 0x1000>;
141                         #address-cells = <1>;
142                         #size-cells = <0>;
143                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
144                         clock-frequency = <400000>;
145                         clocks = <&crg HISTB_I2C1_CLK>;
146                         status = "disabled";
147                 };
148
149                 i2c2: i2c@8b12000 {
150                         compatible = "hisilicon,hix5hd2-i2c";
151                         reg = <0x8b12000 0x1000>;
152                         #address-cells = <1>;
153                         #size-cells = <0>;
154                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
155                         clock-frequency = <400000>;
156                         clocks = <&crg HISTB_I2C2_CLK>;
157                         status = "disabled";
158                 };
159
160                 i2c3: i2c@8b13000 {
161                         compatible = "hisilicon,hix5hd2-i2c";
162                         reg = <0x8b13000 0x1000>;
163                         #address-cells = <1>;
164                         #size-cells = <0>;
165                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
166                         clock-frequency = <400000>;
167                         clocks = <&crg HISTB_I2C3_CLK>;
168                         status = "disabled";
169                 };
170
171                 i2c4: i2c@8b14000 {
172                         compatible = "hisilicon,hix5hd2-i2c";
173                         reg = <0x8b14000 0x1000>;
174                         #address-cells = <1>;
175                         #size-cells = <0>;
176                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
177                         clock-frequency = <400000>;
178                         clocks = <&crg HISTB_I2C4_CLK>;
179                         status = "disabled";
180                 };
181
182                 spi0: spi@8b1a000 {
183                         compatible = "arm,pl022", "arm,primecell";
184                         reg = <0x8b1a000 0x1000>;
185                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
186                         num-cs = <1>;
187                         cs-gpios = <&gpio7 1 0>;
188                         clocks = <&crg HISTB_SPI0_CLK>;
189                         clock-names = "apb_pclk";
190                         #address-cells = <1>;
191                         #size-cells = <0>;
192                         status = "disabled";
193                 };
194
195                 sd0: mmc@9820000 {
196                         compatible = "snps,dw-mshc";
197                         reg = <0x9820000 0x10000>;
198                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199                         clocks = <&crg HISTB_SDIO0_CIU_CLK>,
200                                  <&crg HISTB_SDIO0_BIU_CLK>;
201                         clock-names = "ciu", "biu";
202                         resets = <&crg 0x9c 4>;
203                         reset-names = "reset";
204                         status = "disabled";
205                 };
206
207                 emmc: mmc@9830000 {
208                         compatible = "snps,dw-mshc";
209                         reg = <0x9830000 0x10000>;
210                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
211                         clocks = <&crg HISTB_MMC_CIU_CLK>,
212                                  <&crg HISTB_MMC_BIU_CLK>;
213                         clock-names = "ciu", "biu";
214                 };
215
216                 gpio0: gpio@8b20000 {
217                         compatible = "arm,pl061", "arm,primecell";
218                         reg = <0x8b20000 0x1000>;
219                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
220                         gpio-controller;
221                         #gpio-cells = <2>;
222                         interrupt-controller;
223                         #interrupt-cells = <2>;
224                         clocks = <&crg HISTB_APB_CLK>;
225                         clock-names = "apb_pclk";
226                         status = "disabled";
227                 };
228
229                 gpio1: gpio@8b21000 {
230                         compatible = "arm,pl061", "arm,primecell";
231                         reg = <0x8b21000 0x1000>;
232                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
233                         gpio-controller;
234                         #gpio-cells = <2>;
235                         interrupt-controller;
236                         #interrupt-cells = <2>;
237                         clocks = <&crg HISTB_APB_CLK>;
238                         clock-names = "apb_pclk";
239                         status = "disabled";
240                 };
241
242                 gpio2: gpio@8b22000 {
243                         compatible = "arm,pl061", "arm,primecell";
244                         reg = <0x8b22000 0x1000>;
245                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
246                         gpio-controller;
247                         #gpio-cells = <2>;
248                         interrupt-controller;
249                         #interrupt-cells = <2>;
250                         clocks = <&crg HISTB_APB_CLK>;
251                         clock-names = "apb_pclk";
252                         status = "disabled";
253                 };
254
255                 gpio3: gpio@8b23000 {
256                         compatible = "arm,pl061", "arm,primecell";
257                         reg = <0x8b23000 0x1000>;
258                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
259                         gpio-controller;
260                         #gpio-cells = <2>;
261                         interrupt-controller;
262                         #interrupt-cells = <2>;
263                         clocks = <&crg HISTB_APB_CLK>;
264                         clock-names = "apb_pclk";
265                         status = "disabled";
266                 };
267
268                 gpio4: gpio@8b24000 {
269                         compatible = "arm,pl061", "arm,primecell";
270                         reg = <0x8b24000 0x1000>;
271                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
272                         gpio-controller;
273                         #gpio-cells = <2>;
274                         interrupt-controller;
275                         #interrupt-cells = <2>;
276                         clocks = <&crg HISTB_APB_CLK>;
277                         clock-names = "apb_pclk";
278                         status = "disabled";
279                 };
280
281                 gpio5: gpio@8004000 {
282                         compatible = "arm,pl061", "arm,primecell";
283                         reg = <0x8004000 0x1000>;
284                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
285                         gpio-controller;
286                         #gpio-cells = <2>;
287                         interrupt-controller;
288                         #interrupt-cells = <2>;
289                         clocks = <&crg HISTB_APB_CLK>;
290                         clock-names = "apb_pclk";
291                         status = "disabled";
292                 };
293
294                 gpio6: gpio@8b26000 {
295                         compatible = "arm,pl061", "arm,primecell";
296                         reg = <0x8b26000 0x1000>;
297                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
298                         gpio-controller;
299                         #gpio-cells = <2>;
300                         interrupt-controller;
301                         #interrupt-cells = <2>;
302                         clocks = <&crg HISTB_APB_CLK>;
303                         clock-names = "apb_pclk";
304                         status = "disabled";
305                 };
306
307                 gpio7: gpio@8b27000 {
308                         compatible = "arm,pl061", "arm,primecell";
309                         reg = <0x8b27000 0x1000>;
310                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
311                         gpio-controller;
312                         #gpio-cells = <2>;
313                         interrupt-controller;
314                         #interrupt-cells = <2>;
315                         clocks = <&crg HISTB_APB_CLK>;
316                         clock-names = "apb_pclk";
317                         status = "disabled";
318                 };
319
320                 gpio8: gpio@8b28000 {
321                         compatible = "arm,pl061", "arm,primecell";
322                         reg = <0x8b28000 0x1000>;
323                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
324                         gpio-controller;
325                         #gpio-cells = <2>;
326                         interrupt-controller;
327                         #interrupt-cells = <2>;
328                         clocks = <&crg HISTB_APB_CLK>;
329                         clock-names = "apb_pclk";
330                         status = "disabled";
331                 };
332
333                 gpio9: gpio@8b29000 {
334                         compatible = "arm,pl061", "arm,primecell";
335                         reg = <0x8b29000 0x1000>;
336                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
337                         gpio-controller;
338                         #gpio-cells = <2>;
339                         interrupt-controller;
340                         #interrupt-cells = <2>;
341                         clocks = <&crg HISTB_APB_CLK>;
342                         clock-names = "apb_pclk";
343                         status = "disabled";
344                 };
345
346                 gpio10: gpio@8b2a000 {
347                         compatible = "arm,pl061", "arm,primecell";
348                         reg = <0x8b2a000 0x1000>;
349                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
350                         gpio-controller;
351                         #gpio-cells = <2>;
352                         interrupt-controller;
353                         #interrupt-cells = <2>;
354                         clocks = <&crg HISTB_APB_CLK>;
355                         clock-names = "apb_pclk";
356                         status = "disabled";
357                 };
358
359                 gpio11: gpio@8b2b000 {
360                         compatible = "arm,pl061", "arm,primecell";
361                         reg = <0x8b2b000 0x1000>;
362                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
363                         gpio-controller;
364                         #gpio-cells = <2>;
365                         interrupt-controller;
366                         #interrupt-cells = <2>;
367                         clocks = <&crg HISTB_APB_CLK>;
368                         clock-names = "apb_pclk";
369                         status = "disabled";
370                 };
371
372                 gpio12: gpio@8b2c000 {
373                         compatible = "arm,pl061", "arm,primecell";
374                         reg = <0x8b2c000 0x1000>;
375                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
376                         gpio-controller;
377                         #gpio-cells = <2>;
378                         interrupt-controller;
379                         #interrupt-cells = <2>;
380                         clocks = <&crg HISTB_APB_CLK>;
381                         clock-names = "apb_pclk";
382                         status = "disabled";
383                 };
384
385                 gmac0: ethernet@9840000 {
386                         compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
387                         reg = <0x9840000 0x1000>,
388                               <0x984300c 0x4>;
389                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
390                         clocks = <&crg HISTB_ETH0_MAC_CLK>,
391                                  <&crg HISTB_ETH0_MACIF_CLK>;
392                         clock-names = "mac_core", "mac_ifc";
393                         resets = <&crg 0xcc 8>,
394                                  <&crg 0xcc 10>,
395                                  <&gmacphyrst 0>;
396                         reset-names = "mac_core", "mac_ifc", "phy";
397                         status = "disabled";
398                 };
399
400                 gmac1: ethernet@9841000 {
401                         compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
402                         reg = <0x9841000 0x1000>,
403                               <0x9843010 0x4>;
404                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
405                         clocks = <&crg HISTB_ETH1_MAC_CLK>,
406                                  <&crg HISTB_ETH1_MACIF_CLK>;
407                         clock-names = "mac_core", "mac_ifc";
408                         resets = <&crg 0xcc 9>,
409                                  <&crg 0xcc 11>,
410                                  <&gmacphyrst 1>;
411                         reset-names = "mac_core", "mac_ifc", "phy";
412                         status = "disabled";
413                 };
414
415                 ir: ir@8001000 {
416                         compatible = "hisilicon,hix5hd2-ir";
417                         reg = <0x8001000 0x1000>;
418                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
419                         clocks = <&sysctrl HISTB_IR_CLK>;
420                         status = "disabled";
421                 };
422         };
423 };