arm64: dts: rockchip: add Gru Scarlet devicetrees
[muen/linux.git] / arch / arm64 / boot / dts / rockchip / rk3328.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4  */
5
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16         compatible = "rockchip,rk3328";
17
18         interrupt-parent = <&gic>;
19         #address-cells = <2>;
20         #size-cells = <2>;
21
22         aliases {
23                 serial0 = &uart0;
24                 serial1 = &uart1;
25                 serial2 = &uart2;
26                 i2c0 = &i2c0;
27                 i2c1 = &i2c1;
28                 i2c2 = &i2c2;
29                 i2c3 = &i2c3;
30                 ethernet0 = &gmac2io;
31                 ethernet1 = &gmac2phy;
32         };
33
34         cpus {
35                 #address-cells = <2>;
36                 #size-cells = <0>;
37
38                 cpu0: cpu@0 {
39                         device_type = "cpu";
40                         compatible = "arm,cortex-a53", "arm,armv8";
41                         reg = <0x0 0x0>;
42                         clocks = <&cru ARMCLK>;
43                         #cooling-cells = <2>;
44                         dynamic-power-coefficient = <120>;
45                         enable-method = "psci";
46                         next-level-cache = <&l2>;
47                         operating-points-v2 = <&cpu0_opp_table>;
48                 };
49
50                 cpu1: cpu@1 {
51                         device_type = "cpu";
52                         compatible = "arm,cortex-a53", "arm,armv8";
53                         reg = <0x0 0x1>;
54                         clocks = <&cru ARMCLK>;
55                         #cooling-cells = <2>;
56                         dynamic-power-coefficient = <120>;
57                         enable-method = "psci";
58                         next-level-cache = <&l2>;
59                         operating-points-v2 = <&cpu0_opp_table>;
60                 };
61
62                 cpu2: cpu@2 {
63                         device_type = "cpu";
64                         compatible = "arm,cortex-a53", "arm,armv8";
65                         reg = <0x0 0x2>;
66                         clocks = <&cru ARMCLK>;
67                         #cooling-cells = <2>;
68                         dynamic-power-coefficient = <120>;
69                         enable-method = "psci";
70                         next-level-cache = <&l2>;
71                         operating-points-v2 = <&cpu0_opp_table>;
72                 };
73
74                 cpu3: cpu@3 {
75                         device_type = "cpu";
76                         compatible = "arm,cortex-a53", "arm,armv8";
77                         reg = <0x0 0x3>;
78                         clocks = <&cru ARMCLK>;
79                         #cooling-cells = <2>;
80                         dynamic-power-coefficient = <120>;
81                         enable-method = "psci";
82                         next-level-cache = <&l2>;
83                         operating-points-v2 = <&cpu0_opp_table>;
84                 };
85
86                 l2: l2-cache0 {
87                         compatible = "cache";
88                 };
89         };
90
91         cpu0_opp_table: opp_table0 {
92                 compatible = "operating-points-v2";
93                 opp-shared;
94
95                 opp-408000000 {
96                         opp-hz = /bits/ 64 <408000000>;
97                         opp-microvolt = <950000>;
98                         clock-latency-ns = <40000>;
99                         opp-suspend;
100                 };
101                 opp-600000000 {
102                         opp-hz = /bits/ 64 <600000000>;
103                         opp-microvolt = <950000>;
104                         clock-latency-ns = <40000>;
105                 };
106                 opp-816000000 {
107                         opp-hz = /bits/ 64 <816000000>;
108                         opp-microvolt = <1000000>;
109                         clock-latency-ns = <40000>;
110                 };
111                 opp-1008000000 {
112                         opp-hz = /bits/ 64 <1008000000>;
113                         opp-microvolt = <1100000>;
114                         clock-latency-ns = <40000>;
115                 };
116                 opp-1200000000 {
117                         opp-hz = /bits/ 64 <1200000000>;
118                         opp-microvolt = <1225000>;
119                         clock-latency-ns = <40000>;
120                 };
121                 opp-1296000000 {
122                         opp-hz = /bits/ 64 <1296000000>;
123                         opp-microvolt = <1300000>;
124                         clock-latency-ns = <40000>;
125                 };
126         };
127
128         amba {
129                 compatible = "simple-bus";
130                 #address-cells = <2>;
131                 #size-cells = <2>;
132                 ranges;
133
134                 dmac: dmac@ff1f0000 {
135                         compatible = "arm,pl330", "arm,primecell";
136                         reg = <0x0 0xff1f0000 0x0 0x4000>;
137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139                         clocks = <&cru ACLK_DMAC>;
140                         clock-names = "apb_pclk";
141                         #dma-cells = <1>;
142                 };
143         };
144
145         arm-pmu {
146                 compatible = "arm,cortex-a53-pmu";
147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152         };
153
154         display_subsystem: display-subsystem {
155                 compatible = "rockchip,display-subsystem";
156                 ports = <&vop_out>;
157         };
158
159         psci {
160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
161                 method = "smc";
162         };
163
164         timer {
165                 compatible = "arm,armv8-timer";
166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170         };
171
172         xin24m: xin24m {
173                 compatible = "fixed-clock";
174                 #clock-cells = <0>;
175                 clock-frequency = <24000000>;
176                 clock-output-names = "xin24m";
177         };
178
179         i2s0: i2s@ff000000 {
180                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
181                 reg = <0x0 0xff000000 0x0 0x1000>;
182                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
183                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
184                 clock-names = "i2s_clk", "i2s_hclk";
185                 dmas = <&dmac 11>, <&dmac 12>;
186                 dma-names = "tx", "rx";
187                 status = "disabled";
188         };
189
190         i2s1: i2s@ff010000 {
191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
192                 reg = <0x0 0xff010000 0x0 0x1000>;
193                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
194                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
195                 clock-names = "i2s_clk", "i2s_hclk";
196                 dmas = <&dmac 14>, <&dmac 15>;
197                 dma-names = "tx", "rx";
198                 status = "disabled";
199         };
200
201         i2s2: i2s@ff020000 {
202                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
203                 reg = <0x0 0xff020000 0x0 0x1000>;
204                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
205                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
206                 clock-names = "i2s_clk", "i2s_hclk";
207                 dmas = <&dmac 0>, <&dmac 1>;
208                 dma-names = "tx", "rx";
209                 status = "disabled";
210         };
211
212         spdif: spdif@ff030000 {
213                 compatible = "rockchip,rk3328-spdif";
214                 reg = <0x0 0xff030000 0x0 0x1000>;
215                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
216                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
217                 clock-names = "mclk", "hclk";
218                 dmas = <&dmac 10>;
219                 dma-names = "tx";
220                 pinctrl-names = "default";
221                 pinctrl-0 = <&spdifm2_tx>;
222                 status = "disabled";
223         };
224
225         pdm: pdm@ff040000 {
226                 compatible = "rockchip,pdm";
227                 reg = <0x0 0xff040000 0x0 0x1000>;
228                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
229                 clock-names = "pdm_clk", "pdm_hclk";
230                 dmas = <&dmac 16>;
231                 dma-names = "rx";
232                 pinctrl-names = "default", "sleep";
233                 pinctrl-0 = <&pdmm0_clk
234                              &pdmm0_sdi0
235                              &pdmm0_sdi1
236                              &pdmm0_sdi2
237                              &pdmm0_sdi3>;
238                 pinctrl-1 = <&pdmm0_clk_sleep
239                              &pdmm0_sdi0_sleep
240                              &pdmm0_sdi1_sleep
241                              &pdmm0_sdi2_sleep
242                              &pdmm0_sdi3_sleep>;
243                 status = "disabled";
244         };
245
246         grf: syscon@ff100000 {
247                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
248                 reg = <0x0 0xff100000 0x0 0x1000>;
249                 #address-cells = <1>;
250                 #size-cells = <1>;
251
252                 io_domains: io-domains {
253                         compatible = "rockchip,rk3328-io-voltage-domain";
254                         status = "disabled";
255                 };
256
257                 grf_gpio: grf-gpio {
258                         compatible = "rockchip,rk3328-grf-gpio";
259                         gpio-controller;
260                         #gpio-cells = <2>;
261                 };
262
263                 power: power-controller {
264                         compatible = "rockchip,rk3328-power-controller";
265                         #power-domain-cells = <1>;
266                         #address-cells = <1>;
267                         #size-cells = <0>;
268
269                         pd_hevc@RK3328_PD_HEVC {
270                                 reg = <RK3328_PD_HEVC>;
271                         };
272                         pd_video@RK3328_PD_VIDEO {
273                                 reg = <RK3328_PD_VIDEO>;
274                         };
275                         pd_vpu@RK3328_PD_VPU {
276                                 reg = <RK3328_PD_VPU>;
277                         };
278                 };
279
280                 reboot-mode {
281                         compatible = "syscon-reboot-mode";
282                         offset = <0x5c8>;
283                         mode-normal = <BOOT_NORMAL>;
284                         mode-recovery = <BOOT_RECOVERY>;
285                         mode-bootloader = <BOOT_FASTBOOT>;
286                         mode-loader = <BOOT_BL_DOWNLOAD>;
287                 };
288         };
289
290         uart0: serial@ff110000 {
291                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
292                 reg = <0x0 0xff110000 0x0 0x100>;
293                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
294                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
295                 clock-names = "baudclk", "apb_pclk";
296                 dmas = <&dmac 2>, <&dmac 3>;
297                 dma-names = "tx", "rx";
298                 pinctrl-names = "default";
299                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
300                 reg-io-width = <4>;
301                 reg-shift = <2>;
302                 status = "disabled";
303         };
304
305         uart1: serial@ff120000 {
306                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
307                 reg = <0x0 0xff120000 0x0 0x100>;
308                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
309                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
310                 clock-names = "baudclk", "apb_pclk";
311                 dmas = <&dmac 4>, <&dmac 5>;
312                 dma-names = "tx", "rx";
313                 pinctrl-names = "default";
314                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
315                 reg-io-width = <4>;
316                 reg-shift = <2>;
317                 status = "disabled";
318         };
319
320         uart2: serial@ff130000 {
321                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
322                 reg = <0x0 0xff130000 0x0 0x100>;
323                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
324                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
325                 clock-names = "baudclk", "apb_pclk";
326                 dmas = <&dmac 6>, <&dmac 7>;
327                 dma-names = "tx", "rx";
328                 pinctrl-names = "default";
329                 pinctrl-0 = <&uart2m1_xfer>;
330                 reg-io-width = <4>;
331                 reg-shift = <2>;
332                 status = "disabled";
333         };
334
335         i2c0: i2c@ff150000 {
336                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
337                 reg = <0x0 0xff150000 0x0 0x1000>;
338                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
339                 #address-cells = <1>;
340                 #size-cells = <0>;
341                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
342                 clock-names = "i2c", "pclk";
343                 pinctrl-names = "default";
344                 pinctrl-0 = <&i2c0_xfer>;
345                 status = "disabled";
346         };
347
348         i2c1: i2c@ff160000 {
349                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
350                 reg = <0x0 0xff160000 0x0 0x1000>;
351                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
352                 #address-cells = <1>;
353                 #size-cells = <0>;
354                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
355                 clock-names = "i2c", "pclk";
356                 pinctrl-names = "default";
357                 pinctrl-0 = <&i2c1_xfer>;
358                 status = "disabled";
359         };
360
361         i2c2: i2c@ff170000 {
362                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
363                 reg = <0x0 0xff170000 0x0 0x1000>;
364                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
365                 #address-cells = <1>;
366                 #size-cells = <0>;
367                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
368                 clock-names = "i2c", "pclk";
369                 pinctrl-names = "default";
370                 pinctrl-0 = <&i2c2_xfer>;
371                 status = "disabled";
372         };
373
374         i2c3: i2c@ff180000 {
375                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
376                 reg = <0x0 0xff180000 0x0 0x1000>;
377                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
378                 #address-cells = <1>;
379                 #size-cells = <0>;
380                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
381                 clock-names = "i2c", "pclk";
382                 pinctrl-names = "default";
383                 pinctrl-0 = <&i2c3_xfer>;
384                 status = "disabled";
385         };
386
387         spi0: spi@ff190000 {
388                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
389                 reg = <0x0 0xff190000 0x0 0x1000>;
390                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
391                 #address-cells = <1>;
392                 #size-cells = <0>;
393                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
394                 clock-names = "spiclk", "apb_pclk";
395                 dmas = <&dmac 8>, <&dmac 9>;
396                 dma-names = "tx", "rx";
397                 pinctrl-names = "default";
398                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
399                 status = "disabled";
400         };
401
402         wdt: watchdog@ff1a0000 {
403                 compatible = "snps,dw-wdt";
404                 reg = <0x0 0xff1a0000 0x0 0x100>;
405                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
406         };
407
408         pwm0: pwm@ff1b0000 {
409                 compatible = "rockchip,rk3328-pwm";
410                 reg = <0x0 0xff1b0000 0x0 0x10>;
411                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
412                 clock-names = "pwm", "pclk";
413                 pinctrl-names = "default";
414                 pinctrl-0 = <&pwm0_pin>;
415                 #pwm-cells = <3>;
416                 status = "disabled";
417         };
418
419         pwm1: pwm@ff1b0010 {
420                 compatible = "rockchip,rk3328-pwm";
421                 reg = <0x0 0xff1b0010 0x0 0x10>;
422                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
423                 clock-names = "pwm", "pclk";
424                 pinctrl-names = "default";
425                 pinctrl-0 = <&pwm1_pin>;
426                 #pwm-cells = <3>;
427                 status = "disabled";
428         };
429
430         pwm2: pwm@ff1b0020 {
431                 compatible = "rockchip,rk3328-pwm";
432                 reg = <0x0 0xff1b0020 0x0 0x10>;
433                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
434                 clock-names = "pwm", "pclk";
435                 pinctrl-names = "default";
436                 pinctrl-0 = <&pwm2_pin>;
437                 #pwm-cells = <3>;
438                 status = "disabled";
439         };
440
441         pwm3: pwm@ff1b0030 {
442                 compatible = "rockchip,rk3328-pwm";
443                 reg = <0x0 0xff1b0030 0x0 0x10>;
444                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
445                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
446                 clock-names = "pwm", "pclk";
447                 pinctrl-names = "default";
448                 pinctrl-0 = <&pwmir_pin>;
449                 #pwm-cells = <3>;
450                 status = "disabled";
451         };
452
453         thermal-zones {
454                 soc_thermal: soc-thermal {
455                         polling-delay-passive = <20>;
456                         polling-delay = <1000>;
457                         sustainable-power = <1000>;
458
459                         thermal-sensors = <&tsadc 0>;
460
461                         trips {
462                                 threshold: trip-point0 {
463                                         temperature = <70000>;
464                                         hysteresis = <2000>;
465                                         type = "passive";
466                                 };
467                                 target: trip-point1 {
468                                         temperature = <85000>;
469                                         hysteresis = <2000>;
470                                         type = "passive";
471                                 };
472                                 soc_crit: soc-crit {
473                                         temperature = <95000>;
474                                         hysteresis = <2000>;
475                                         type = "critical";
476                                 };
477                         };
478
479                         cooling-maps {
480                                 map0 {
481                                         trip = <&target>;
482                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
483                                         contribution = <4096>;
484                                 };
485                         };
486                 };
487
488         };
489
490         tsadc: tsadc@ff250000 {
491                 compatible = "rockchip,rk3328-tsadc";
492                 reg = <0x0 0xff250000 0x0 0x100>;
493                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
494                 assigned-clocks = <&cru SCLK_TSADC>;
495                 assigned-clock-rates = <50000>;
496                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
497                 clock-names = "tsadc", "apb_pclk";
498                 pinctrl-names = "init", "default", "sleep";
499                 pinctrl-0 = <&otp_gpio>;
500                 pinctrl-1 = <&otp_out>;
501                 pinctrl-2 = <&otp_gpio>;
502                 resets = <&cru SRST_TSADC>;
503                 reset-names = "tsadc-apb";
504                 rockchip,grf = <&grf>;
505                 rockchip,hw-tshut-temp = <100000>;
506                 #thermal-sensor-cells = <1>;
507                 status = "disabled";
508         };
509
510         efuse: efuse@ff260000 {
511                 compatible = "rockchip,rk3328-efuse";
512                 reg = <0x0 0xff260000 0x0 0x50>;
513                 #address-cells = <1>;
514                 #size-cells = <1>;
515                 clocks = <&cru SCLK_EFUSE>;
516                 clock-names = "pclk_efuse";
517                 rockchip,efuse-size = <0x20>;
518
519                 /* Data cells */
520                 efuse_id: id@7 {
521                         reg = <0x07 0x10>;
522                 };
523                 cpu_leakage: cpu-leakage@17 {
524                         reg = <0x17 0x1>;
525                 };
526                 logic_leakage: logic-leakage@19 {
527                         reg = <0x19 0x1>;
528                 };
529                 efuse_cpu_version: cpu-version@1a {
530                         reg = <0x1a 0x1>;
531                         bits = <3 3>;
532                 };
533         };
534
535         saradc: adc@ff280000 {
536                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
537                 reg = <0x0 0xff280000 0x0 0x100>;
538                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
539                 #io-channel-cells = <1>;
540                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
541                 clock-names = "saradc", "apb_pclk";
542                 resets = <&cru SRST_SARADC_P>;
543                 reset-names = "saradc-apb";
544                 status = "disabled";
545         };
546
547         gpu: gpu@ff300000 {
548                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
549                 reg = <0x0 0xff300000 0x0 0x40000>;
550                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
551                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
552                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
553                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
554                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
555                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
556                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
557                 interrupt-names = "gp",
558                                   "gpmmu",
559                                   "pp",
560                                   "pp0",
561                                   "ppmmu0",
562                                   "pp1",
563                                   "ppmmu1";
564                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
565                 clock-names = "bus", "core";
566                 resets = <&cru SRST_GPU_A>;
567         };
568
569         h265e_mmu: iommu@ff330200 {
570                 compatible = "rockchip,iommu";
571                 reg = <0x0 0xff330200 0 0x100>;
572                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
573                 interrupt-names = "h265e_mmu";
574                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
575                 clock-names = "aclk", "iface";
576                 #iommu-cells = <0>;
577                 status = "disabled";
578         };
579
580         vepu_mmu: iommu@ff340800 {
581                 compatible = "rockchip,iommu";
582                 reg = <0x0 0xff340800 0x0 0x40>;
583                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
584                 interrupt-names = "vepu_mmu";
585                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
586                 clock-names = "aclk", "iface";
587                 #iommu-cells = <0>;
588                 status = "disabled";
589         };
590
591         vpu_mmu: iommu@ff350800 {
592                 compatible = "rockchip,iommu";
593                 reg = <0x0 0xff350800 0x0 0x40>;
594                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
595                 interrupt-names = "vpu_mmu";
596                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
597                 clock-names = "aclk", "iface";
598                 #iommu-cells = <0>;
599                 status = "disabled";
600         };
601
602         rkvdec_mmu: iommu@ff360480 {
603                 compatible = "rockchip,iommu";
604                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
605                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
606                 interrupt-names = "rkvdec_mmu";
607                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
608                 clock-names = "aclk", "iface";
609                 #iommu-cells = <0>;
610                 status = "disabled";
611         };
612
613         vop: vop@ff370000 {
614                 compatible = "rockchip,rk3328-vop";
615                 reg = <0x0 0xff370000 0x0 0x3efc>;
616                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
617                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
618                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
619                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
620                 reset-names = "axi", "ahb", "dclk";
621                 iommus = <&vop_mmu>;
622                 status = "disabled";
623
624                 vop_out: port {
625                         #address-cells = <1>;
626                         #size-cells = <0>;
627
628                         vop_out_hdmi: endpoint@0 {
629                                 reg = <0>;
630                                 remote-endpoint = <&hdmi_in_vop>;
631                         };
632                 };
633         };
634
635         vop_mmu: iommu@ff373f00 {
636                 compatible = "rockchip,iommu";
637                 reg = <0x0 0xff373f00 0x0 0x100>;
638                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
639                 interrupt-names = "vop_mmu";
640                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
641                 clock-names = "aclk", "iface";
642                 #iommu-cells = <0>;
643                 status = "disabled";
644         };
645
646         hdmi: hdmi@ff3c0000 {
647                 compatible = "rockchip,rk3328-dw-hdmi";
648                 reg = <0x0 0xff3c0000 0x0 0x20000>;
649                 reg-io-width = <4>;
650                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
651                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
652                 clocks = <&cru PCLK_HDMI>,
653                          <&cru SCLK_HDMI_SFC>;
654                 clock-names = "iahb",
655                               "isfr";
656                 phys = <&hdmiphy>;
657                 phy-names = "hdmi";
658                 pinctrl-names = "default";
659                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
660                 rockchip,grf = <&grf>;
661                 status = "disabled";
662
663                 ports {
664                         hdmi_in: port {
665                                 hdmi_in_vop: endpoint {
666                                         remote-endpoint = <&vop_out_hdmi>;
667                                 };
668                         };
669                 };
670         };
671
672         hdmiphy: phy@ff430000 {
673                 compatible = "rockchip,rk3328-hdmi-phy";
674                 reg = <0x0 0xff430000 0x0 0x10000>;
675                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
676                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
677                 clock-names = "sysclk", "refoclk", "refpclk";
678                 clock-output-names = "hdmi_phy";
679                 #clock-cells = <0>;
680                 nvmem-cells = <&efuse_cpu_version>;
681                 nvmem-cell-names = "cpu-version";
682                 #phy-cells = <0>;
683                 status = "disabled";
684         };
685
686         cru: clock-controller@ff440000 {
687                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
688                 reg = <0x0 0xff440000 0x0 0x1000>;
689                 rockchip,grf = <&grf>;
690                 #clock-cells = <1>;
691                 #reset-cells = <1>;
692                 assigned-clocks =
693                         /*
694                          * CPLL should run at 1200, but that is to high for
695                          * the initial dividers of most of its children.
696                          * We need set cpll child clk div first,
697                          * and then set the cpll frequency.
698                          */
699                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
700                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
701                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
702                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
703                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
704                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
705                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
706                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
707                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
708                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
709                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
710                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
711                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
712                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
713                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
714                         <&cru SCLK_RTC32K>;
715                 assigned-clock-parents =
716                         <&cru HDMIPHY>, <&cru PLL_APLL>,
717                         <&cru PLL_GPLL>, <&xin24m>,
718                         <&xin24m>, <&xin24m>;
719                 assigned-clock-rates =
720                         <0>, <61440000>,
721                         <0>, <24000000>,
722                         <24000000>, <24000000>,
723                         <15000000>, <15000000>,
724                         <100000000>, <100000000>,
725                         <100000000>, <100000000>,
726                         <50000000>, <100000000>,
727                         <100000000>, <100000000>,
728                         <50000000>, <50000000>,
729                         <50000000>, <50000000>,
730                         <24000000>, <600000000>,
731                         <491520000>, <1200000000>,
732                         <150000000>, <75000000>,
733                         <75000000>, <150000000>,
734                         <75000000>, <75000000>,
735                         <32768>;
736         };
737
738         usb2phy_grf: syscon@ff450000 {
739                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
740                              "simple-mfd";
741                 reg = <0x0 0xff450000 0x0 0x10000>;
742                 #address-cells = <1>;
743                 #size-cells = <1>;
744
745                 u2phy: usb2-phy@100 {
746                         compatible = "rockchip,rk3328-usb2phy";
747                         reg = <0x100 0x10>;
748                         clocks = <&xin24m>;
749                         clock-names = "phyclk";
750                         clock-output-names = "usb480m_phy";
751                         #clock-cells = <0>;
752                         assigned-clocks = <&cru USB480M>;
753                         assigned-clock-parents = <&u2phy>;
754                         status = "disabled";
755
756                         u2phy_otg: otg-port {
757                                 #phy-cells = <0>;
758                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
759                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
760                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
761                                 interrupt-names = "otg-bvalid", "otg-id",
762                                                   "linestate";
763                                 status = "disabled";
764                         };
765
766                         u2phy_host: host-port {
767                                 #phy-cells = <0>;
768                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
769                                 interrupt-names = "linestate";
770                                 status = "disabled";
771                         };
772                 };
773         };
774
775         sdmmc: dwmmc@ff500000 {
776                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
777                 reg = <0x0 0xff500000 0x0 0x4000>;
778                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
779                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
780                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
781                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
782                 fifo-depth = <0x100>;
783                 status = "disabled";
784         };
785
786         sdio: dwmmc@ff510000 {
787                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
788                 reg = <0x0 0xff510000 0x0 0x4000>;
789                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
790                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
791                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
792                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
793                 fifo-depth = <0x100>;
794                 status = "disabled";
795         };
796
797         emmc: dwmmc@ff520000 {
798                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
799                 reg = <0x0 0xff520000 0x0 0x4000>;
800                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
801                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
802                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
803                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
804                 fifo-depth = <0x100>;
805                 status = "disabled";
806         };
807
808         gmac2io: ethernet@ff540000 {
809                 compatible = "rockchip,rk3328-gmac";
810                 reg = <0x0 0xff540000 0x0 0x10000>;
811                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
812                 interrupt-names = "macirq";
813                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
814                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
815                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
816                          <&cru PCLK_MAC2IO>;
817                 clock-names = "stmmaceth", "mac_clk_rx",
818                               "mac_clk_tx", "clk_mac_ref",
819                               "clk_mac_refout", "aclk_mac",
820                               "pclk_mac";
821                 resets = <&cru SRST_GMAC2IO_A>;
822                 reset-names = "stmmaceth";
823                 rockchip,grf = <&grf>;
824                 status = "disabled";
825         };
826
827         gmac2phy: ethernet@ff550000 {
828                 compatible = "rockchip,rk3328-gmac";
829                 reg = <0x0 0xff550000 0x0 0x10000>;
830                 rockchip,grf = <&grf>;
831                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
832                 interrupt-names = "macirq";
833                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
834                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
835                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
836                          <&cru SCLK_MAC2PHY_OUT>;
837                 clock-names = "stmmaceth", "mac_clk_rx",
838                               "mac_clk_tx", "clk_mac_ref",
839                               "aclk_mac", "pclk_mac",
840                               "clk_macphy";
841                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
842                 reset-names = "stmmaceth", "mac-phy";
843                 phy-mode = "rmii";
844                 phy-handle = <&phy>;
845                 status = "disabled";
846
847                 mdio {
848                         compatible = "snps,dwmac-mdio";
849                         #address-cells = <1>;
850                         #size-cells = <0>;
851
852                         phy: phy@0 {
853                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
854                                 reg = <0>;
855                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
856                                 resets = <&cru SRST_MACPHY>;
857                                 pinctrl-names = "default";
858                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
859                                 phy-is-integrated;
860                         };
861                 };
862         };
863
864         usb20_otg: usb@ff580000 {
865                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
866                              "snps,dwc2";
867                 reg = <0x0 0xff580000 0x0 0x40000>;
868                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
869                 clocks = <&cru HCLK_OTG>;
870                 clock-names = "otg";
871                 dr_mode = "otg";
872                 g-np-tx-fifo-size = <16>;
873                 g-rx-fifo-size = <280>;
874                 g-tx-fifo-size = <256 128 128 64 32 16>;
875                 g-use-dma;
876                 phys = <&u2phy_otg>;
877                 phy-names = "usb2-phy";
878                 status = "disabled";
879         };
880
881         usb_host0_ehci: usb@ff5c0000 {
882                 compatible = "generic-ehci";
883                 reg = <0x0 0xff5c0000 0x0 0x10000>;
884                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
885                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
886                 clock-names = "usbhost", "utmi";
887                 phys = <&u2phy_host>;
888                 phy-names = "usb";
889                 status = "disabled";
890         };
891
892         usb_host0_ohci: usb@ff5d0000 {
893                 compatible = "generic-ohci";
894                 reg = <0x0 0xff5d0000 0x0 0x10000>;
895                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
896                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
897                 clock-names = "usbhost", "utmi";
898                 phys = <&u2phy_host>;
899                 phy-names = "usb";
900                 status = "disabled";
901         };
902
903         gic: interrupt-controller@ff811000 {
904                 compatible = "arm,gic-400";
905                 #interrupt-cells = <3>;
906                 #address-cells = <0>;
907                 interrupt-controller;
908                 reg = <0x0 0xff811000 0 0x1000>,
909                       <0x0 0xff812000 0 0x2000>,
910                       <0x0 0xff814000 0 0x2000>,
911                       <0x0 0xff816000 0 0x2000>;
912                 interrupts = <GIC_PPI 9
913                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
914         };
915
916         pinctrl: pinctrl {
917                 compatible = "rockchip,rk3328-pinctrl";
918                 rockchip,grf = <&grf>;
919                 #address-cells = <2>;
920                 #size-cells = <2>;
921                 ranges;
922
923                 gpio0: gpio0@ff210000 {
924                         compatible = "rockchip,gpio-bank";
925                         reg = <0x0 0xff210000 0x0 0x100>;
926                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
927                         clocks = <&cru PCLK_GPIO0>;
928
929                         gpio-controller;
930                         #gpio-cells = <2>;
931
932                         interrupt-controller;
933                         #interrupt-cells = <2>;
934                 };
935
936                 gpio1: gpio1@ff220000 {
937                         compatible = "rockchip,gpio-bank";
938                         reg = <0x0 0xff220000 0x0 0x100>;
939                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
940                         clocks = <&cru PCLK_GPIO1>;
941
942                         gpio-controller;
943                         #gpio-cells = <2>;
944
945                         interrupt-controller;
946                         #interrupt-cells = <2>;
947                 };
948
949                 gpio2: gpio2@ff230000 {
950                         compatible = "rockchip,gpio-bank";
951                         reg = <0x0 0xff230000 0x0 0x100>;
952                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
953                         clocks = <&cru PCLK_GPIO2>;
954
955                         gpio-controller;
956                         #gpio-cells = <2>;
957
958                         interrupt-controller;
959                         #interrupt-cells = <2>;
960                 };
961
962                 gpio3: gpio3@ff240000 {
963                         compatible = "rockchip,gpio-bank";
964                         reg = <0x0 0xff240000 0x0 0x100>;
965                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
966                         clocks = <&cru PCLK_GPIO3>;
967
968                         gpio-controller;
969                         #gpio-cells = <2>;
970
971                         interrupt-controller;
972                         #interrupt-cells = <2>;
973                 };
974
975                 pcfg_pull_up: pcfg-pull-up {
976                         bias-pull-up;
977                 };
978
979                 pcfg_pull_down: pcfg-pull-down {
980                         bias-pull-down;
981                 };
982
983                 pcfg_pull_none: pcfg-pull-none {
984                         bias-disable;
985                 };
986
987                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
988                         bias-disable;
989                         drive-strength = <2>;
990                 };
991
992                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
993                         bias-pull-up;
994                         drive-strength = <2>;
995                 };
996
997                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
998                         bias-pull-up;
999                         drive-strength = <4>;
1000                 };
1001
1002                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1003                         bias-disable;
1004                         drive-strength = <4>;
1005                 };
1006
1007                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1008                         bias-pull-down;
1009                         drive-strength = <4>;
1010                 };
1011
1012                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1013                         bias-disable;
1014                         drive-strength = <8>;
1015                 };
1016
1017                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1018                         bias-pull-up;
1019                         drive-strength = <8>;
1020                 };
1021
1022                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1023                         bias-disable;
1024                         drive-strength = <12>;
1025                 };
1026
1027                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1028                         bias-pull-up;
1029                         drive-strength = <12>;
1030                 };
1031
1032                 pcfg_output_high: pcfg-output-high {
1033                         output-high;
1034                 };
1035
1036                 pcfg_output_low: pcfg-output-low {
1037                         output-low;
1038                 };
1039
1040                 pcfg_input_high: pcfg-input-high {
1041                         bias-pull-up;
1042                         input-enable;
1043                 };
1044
1045                 pcfg_input: pcfg-input {
1046                         input-enable;
1047                 };
1048
1049                 i2c0 {
1050                         i2c0_xfer: i2c0-xfer {
1051                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1052                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1053                         };
1054                 };
1055
1056                 i2c1 {
1057                         i2c1_xfer: i2c1-xfer {
1058                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1059                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1060                         };
1061                 };
1062
1063                 i2c2 {
1064                         i2c2_xfer: i2c2-xfer {
1065                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1066                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1067                         };
1068                 };
1069
1070                 i2c3 {
1071                         i2c3_xfer: i2c3-xfer {
1072                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1073                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1074                         };
1075                         i2c3_gpio: i2c3-gpio {
1076                                 rockchip,pins =
1077                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1078                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 hdmi_i2c {
1083                         hdmii2c_xfer: hdmii2c-xfer {
1084                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1085                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1086                         };
1087                 };
1088
1089                 pdm-0 {
1090                         pdmm0_clk: pdmm0-clk {
1091                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1092                         };
1093
1094                         pdmm0_fsync: pdmm0-fsync {
1095                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1096                         };
1097
1098                         pdmm0_sdi0: pdmm0-sdi0 {
1099                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1100                         };
1101
1102                         pdmm0_sdi1: pdmm0-sdi1 {
1103                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1104                         };
1105
1106                         pdmm0_sdi2: pdmm0-sdi2 {
1107                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1108                         };
1109
1110                         pdmm0_sdi3: pdmm0-sdi3 {
1111                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1112                         };
1113
1114                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1115                                 rockchip,pins =
1116                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1117                         };
1118
1119                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1120                                 rockchip,pins =
1121                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1122                         };
1123
1124                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1125                                 rockchip,pins =
1126                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1127                         };
1128
1129                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1130                                 rockchip,pins =
1131                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1132                         };
1133
1134                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1135                                 rockchip,pins =
1136                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1137                         };
1138
1139                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1140                                 rockchip,pins =
1141                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1142                         };
1143                 };
1144
1145                 tsadc {
1146                         otp_gpio: otp-gpio {
1147                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1148                         };
1149
1150                         otp_out: otp-out {
1151                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1152                         };
1153                 };
1154
1155                 uart0 {
1156                         uart0_xfer: uart0-xfer {
1157                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1158                                                 <1 RK_PB0 1 &pcfg_pull_none>;
1159                         };
1160
1161                         uart0_cts: uart0-cts {
1162                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1163                         };
1164
1165                         uart0_rts: uart0-rts {
1166                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1167                         };
1168
1169                         uart0_rts_gpio: uart0-rts-gpio {
1170                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1171                         };
1172                 };
1173
1174                 uart1 {
1175                         uart1_xfer: uart1-xfer {
1176                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1177                                                 <3 RK_PA6 4 &pcfg_pull_none>;
1178                         };
1179
1180                         uart1_cts: uart1-cts {
1181                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1182                         };
1183
1184                         uart1_rts: uart1-rts {
1185                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1186                         };
1187
1188                         uart1_rts_gpio: uart1-rts-gpio {
1189                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1190                         };
1191                 };
1192
1193                 uart2-0 {
1194                         uart2m0_xfer: uart2m0-xfer {
1195                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1196                                                 <1 RK_PA1 2 &pcfg_pull_none>;
1197                         };
1198                 };
1199
1200                 uart2-1 {
1201                         uart2m1_xfer: uart2m1-xfer {
1202                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1203                                                 <2 RK_PA1 1 &pcfg_pull_none>;
1204                         };
1205                 };
1206
1207                 spi0-0 {
1208                         spi0m0_clk: spi0m0-clk {
1209                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1210                         };
1211
1212                         spi0m0_cs0: spi0m0-cs0 {
1213                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1214                         };
1215
1216                         spi0m0_tx: spi0m0-tx {
1217                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1218                         };
1219
1220                         spi0m0_rx: spi0m0-rx {
1221                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1222                         };
1223
1224                         spi0m0_cs1: spi0m0-cs1 {
1225                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1226                         };
1227                 };
1228
1229                 spi0-1 {
1230                         spi0m1_clk: spi0m1-clk {
1231                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1232                         };
1233
1234                         spi0m1_cs0: spi0m1-cs0 {
1235                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1236                         };
1237
1238                         spi0m1_tx: spi0m1-tx {
1239                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1240                         };
1241
1242                         spi0m1_rx: spi0m1-rx {
1243                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1244                         };
1245
1246                         spi0m1_cs1: spi0m1-cs1 {
1247                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1248                         };
1249                 };
1250
1251                 spi0-2 {
1252                         spi0m2_clk: spi0m2-clk {
1253                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1254                         };
1255
1256                         spi0m2_cs0: spi0m2-cs0 {
1257                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1258                         };
1259
1260                         spi0m2_tx: spi0m2-tx {
1261                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1262                         };
1263
1264                         spi0m2_rx: spi0m2-rx {
1265                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1266                         };
1267                 };
1268
1269                 i2s1 {
1270                         i2s1_mclk: i2s1-mclk {
1271                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1272                         };
1273
1274                         i2s1_sclk: i2s1-sclk {
1275                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1276                         };
1277
1278                         i2s1_lrckrx: i2s1-lrckrx {
1279                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1280                         };
1281
1282                         i2s1_lrcktx: i2s1-lrcktx {
1283                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1284                         };
1285
1286                         i2s1_sdi: i2s1-sdi {
1287                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1288                         };
1289
1290                         i2s1_sdo: i2s1-sdo {
1291                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1292                         };
1293
1294                         i2s1_sdio1: i2s1-sdio1 {
1295                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1296                         };
1297
1298                         i2s1_sdio2: i2s1-sdio2 {
1299                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1300                         };
1301
1302                         i2s1_sdio3: i2s1-sdio3 {
1303                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1304                         };
1305
1306                         i2s1_sleep: i2s1-sleep {
1307                                 rockchip,pins =
1308                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1309                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1310                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1311                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1312                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1313                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1314                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1315                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1316                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1317                         };
1318                 };
1319
1320                 i2s2-0 {
1321                         i2s2m0_mclk: i2s2m0-mclk {
1322                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1323                         };
1324
1325                         i2s2m0_sclk: i2s2m0-sclk {
1326                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1327                         };
1328
1329                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1330                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1331                         };
1332
1333                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1334                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1335                         };
1336
1337                         i2s2m0_sdi: i2s2m0-sdi {
1338                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1339                         };
1340
1341                         i2s2m0_sdo: i2s2m0-sdo {
1342                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1343                         };
1344
1345                         i2s2m0_sleep: i2s2m0-sleep {
1346                                 rockchip,pins =
1347                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1348                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1349                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1350                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1351                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1352                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1353                         };
1354                 };
1355
1356                 i2s2-1 {
1357                         i2s2m1_mclk: i2s2m1-mclk {
1358                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1359                         };
1360
1361                         i2s2m1_sclk: i2s2m1-sclk {
1362                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1363                         };
1364
1365                         i2s2m1_lrckrx: i2sm1-lrckrx {
1366                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1367                         };
1368
1369                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1370                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1371                         };
1372
1373                         i2s2m1_sdi: i2s2m1-sdi {
1374                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1375                         };
1376
1377                         i2s2m1_sdo: i2s2m1-sdo {
1378                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1379                         };
1380
1381                         i2s2m1_sleep: i2s2m1-sleep {
1382                                 rockchip,pins =
1383                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1384                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1385                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1386                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1387                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1388                         };
1389                 };
1390
1391                 spdif-0 {
1392                         spdifm0_tx: spdifm0-tx {
1393                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1394                         };
1395                 };
1396
1397                 spdif-1 {
1398                         spdifm1_tx: spdifm1-tx {
1399                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 spdif-2 {
1404                         spdifm2_tx: spdifm2-tx {
1405                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1406                         };
1407                 };
1408
1409                 sdmmc0-0 {
1410                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1411                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1412                         };
1413
1414                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1415                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1416                         };
1417                 };
1418
1419                 sdmmc0-1 {
1420                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1421                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1422                         };
1423
1424                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1425                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1426                         };
1427                 };
1428
1429                 sdmmc0 {
1430                         sdmmc0_clk: sdmmc0-clk {
1431                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1432                         };
1433
1434                         sdmmc0_cmd: sdmmc0-cmd {
1435                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1436                         };
1437
1438                         sdmmc0_dectn: sdmmc0-dectn {
1439                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1440                         };
1441
1442                         sdmmc0_wrprt: sdmmc0-wrprt {
1443                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1444                         };
1445
1446                         sdmmc0_bus1: sdmmc0-bus1 {
1447                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1448                         };
1449
1450                         sdmmc0_bus4: sdmmc0-bus4 {
1451                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1452                                                 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1453                                                 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1454                                                 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1455                         };
1456
1457                         sdmmc0_gpio: sdmmc0-gpio {
1458                                 rockchip,pins =
1459                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1460                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1461                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1462                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1463                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1464                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1465                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1466                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1467                         };
1468                 };
1469
1470                 sdmmc0ext {
1471                         sdmmc0ext_clk: sdmmc0ext-clk {
1472                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1473                         };
1474
1475                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1476                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1477                         };
1478
1479                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1480                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1481                         };
1482
1483                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1484                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1485                         };
1486
1487                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1488                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1489                         };
1490
1491                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1492                                 rockchip,pins =
1493                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1494                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1495                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1496                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1497                         };
1498
1499                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1500                                 rockchip,pins =
1501                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1502                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1503                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1504                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1505                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1506                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1507                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1508                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1509                         };
1510                 };
1511
1512                 sdmmc1 {
1513                         sdmmc1_clk: sdmmc1-clk {
1514                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1515                         };
1516
1517                         sdmmc1_cmd: sdmmc1-cmd {
1518                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1519                         };
1520
1521                         sdmmc1_pwren: sdmmc1-pwren {
1522                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1523                         };
1524
1525                         sdmmc1_wrprt: sdmmc1-wrprt {
1526                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1527                         };
1528
1529                         sdmmc1_dectn: sdmmc1-dectn {
1530                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1531                         };
1532
1533                         sdmmc1_bus1: sdmmc1-bus1 {
1534                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1535                         };
1536
1537                         sdmmc1_bus4: sdmmc1-bus4 {
1538                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1539                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1540                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1541                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1542                         };
1543
1544                         sdmmc1_gpio: sdmmc1-gpio {
1545                                 rockchip,pins =
1546                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1547                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1548                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1549                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1550                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1551                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1552                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1553                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1554                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1555                         };
1556                 };
1557
1558                 emmc {
1559                         emmc_clk: emmc-clk {
1560                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1561                         };
1562
1563                         emmc_cmd: emmc-cmd {
1564                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1565                         };
1566
1567                         emmc_pwren: emmc-pwren {
1568                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1569                         };
1570
1571                         emmc_rstnout: emmc-rstnout {
1572                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1573                         };
1574
1575                         emmc_bus1: emmc-bus1 {
1576                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1577                         };
1578
1579                         emmc_bus4: emmc-bus4 {
1580                                 rockchip,pins =
1581                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1582                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1583                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1584                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1585                         };
1586
1587                         emmc_bus8: emmc-bus8 {
1588                                 rockchip,pins =
1589                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1590                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1591                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1592                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1593                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1594                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1595                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1596                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1597                         };
1598                 };
1599
1600                 pwm0 {
1601                         pwm0_pin: pwm0-pin {
1602                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1603                         };
1604                 };
1605
1606                 pwm1 {
1607                         pwm1_pin: pwm1-pin {
1608                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1609                         };
1610                 };
1611
1612                 pwm2 {
1613                         pwm2_pin: pwm2-pin {
1614                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 pwmir {
1619                         pwmir_pin: pwmir-pin {
1620                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 gmac-1 {
1625                         rgmiim1_pins: rgmiim1-pins {
1626                                 rockchip,pins =
1627                                         /* mac_txclk */
1628                                         <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1629                                         /* mac_rxclk */
1630                                         <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1631                                         /* mac_mdio */
1632                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1633                                         /* mac_txen */
1634                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1635                                         /* mac_clk */
1636                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1637                                         /* mac_rxdv */
1638                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1639                                         /* mac_mdc */
1640                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1641                                         /* mac_rxd1 */
1642                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1643                                         /* mac_rxd0 */
1644                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1645                                         /* mac_txd1 */
1646                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1647                                         /* mac_txd0 */
1648                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1649                                         /* mac_rxd3 */
1650                                         <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1651                                         /* mac_rxd2 */
1652                                         <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1653                                         /* mac_txd3 */
1654                                         <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1655                                         /* mac_txd2 */
1656                                         <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1657
1658                                         /* mac_txclk */
1659                                         <0 RK_PB0 1 &pcfg_pull_none>,
1660                                         /* mac_txen */
1661                                         <0 RK_PB4 1 &pcfg_pull_none>,
1662                                         /* mac_clk */
1663                                         <0 RK_PD0 1 &pcfg_pull_none>,
1664                                         /* mac_txd1 */
1665                                         <0 RK_PC0 1 &pcfg_pull_none>,
1666                                         /* mac_txd0 */
1667                                         <0 RK_PC1 1 &pcfg_pull_none>,
1668                                         /* mac_txd3 */
1669                                         <0 RK_PC7 1 &pcfg_pull_none>,
1670                                         /* mac_txd2 */
1671                                         <0 RK_PC6 1 &pcfg_pull_none>;
1672                         };
1673
1674                         rmiim1_pins: rmiim1-pins {
1675                                 rockchip,pins =
1676                                         /* mac_mdio */
1677                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1678                                         /* mac_txen */
1679                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1680                                         /* mac_clk */
1681                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1682                                         /* mac_rxer */
1683                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1684                                         /* mac_rxdv */
1685                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1686                                         /* mac_mdc */
1687                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1688                                         /* mac_rxd1 */
1689                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1690                                         /* mac_rxd0 */
1691                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1692                                         /* mac_txd1 */
1693                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1694                                         /* mac_txd0 */
1695                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1696
1697                                         /* mac_mdio */
1698                                         <0 RK_PB3 1 &pcfg_pull_none>,
1699                                         /* mac_txen */
1700                                         <0 RK_PB4 1 &pcfg_pull_none>,
1701                                         /* mac_clk */
1702                                         <0 RK_PD0 1 &pcfg_pull_none>,
1703                                         /* mac_mdc */
1704                                         <0 RK_PC3 1 &pcfg_pull_none>,
1705                                         /* mac_txd1 */
1706                                         <0 RK_PC0 1 &pcfg_pull_none>,
1707                                         /* mac_txd0 */
1708                                         <0 RK_PC1 1 &pcfg_pull_none>;
1709                         };
1710                 };
1711
1712                 gmac2phy {
1713                         fephyled_speed100: fephyled-speed100 {
1714                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1715                         };
1716
1717                         fephyled_speed10: fephyled-speed10 {
1718                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1719                         };
1720
1721                         fephyled_duplex: fephyled-duplex {
1722                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1723                         };
1724
1725                         fephyled_rxm0: fephyled-rxm0 {
1726                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1727                         };
1728
1729                         fephyled_txm0: fephyled-txm0 {
1730                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1731                         };
1732
1733                         fephyled_linkm0: fephyled-linkm0 {
1734                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1735                         };
1736
1737                         fephyled_rxm1: fephyled-rxm1 {
1738                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1739                         };
1740
1741                         fephyled_txm1: fephyled-txm1 {
1742                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1743                         };
1744
1745                         fephyled_linkm1: fephyled-linkm1 {
1746                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 tsadc_pin {
1751                         tsadc_int: tsadc-int {
1752                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1753                         };
1754                         tsadc_gpio: tsadc-gpio {
1755                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1756                         };
1757                 };
1758
1759                 hdmi_pin {
1760                         hdmi_cec: hdmi-cec {
1761                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1762                         };
1763
1764                         hdmi_hpd: hdmi-hpd {
1765                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1766                         };
1767                 };
1768
1769                 cif-0 {
1770                         dvp_d2d9_m0:dvp-d2d9-m0 {
1771                                 rockchip,pins =
1772                                         /* cif_d0 */
1773                                         <3 RK_PA4 2 &pcfg_pull_none>,
1774                                         /* cif_d1 */
1775                                         <3 RK_PA5 2 &pcfg_pull_none>,
1776                                         /* cif_d2 */
1777                                         <3 RK_PA6 2 &pcfg_pull_none>,
1778                                         /* cif_d3 */
1779                                         <3 RK_PA7 2 &pcfg_pull_none>,
1780                                         /* cif_d4 */
1781                                         <3 RK_PB0 2 &pcfg_pull_none>,
1782                                         /* cif_d5m0 */
1783                                         <3 RK_PB1 2 &pcfg_pull_none>,
1784                                         /* cif_d6m0 */
1785                                         <3 RK_PB2 2 &pcfg_pull_none>,
1786                                         /* cif_d7m0 */
1787                                         <3 RK_PB3 2 &pcfg_pull_none>,
1788                                         /* cif_href */
1789                                         <3 RK_PA1 2 &pcfg_pull_none>,
1790                                         /* cif_vsync */
1791                                         <3 RK_PA0 2 &pcfg_pull_none>,
1792                                         /* cif_clkoutm0 */
1793                                         <3 RK_PA3 2 &pcfg_pull_none>,
1794                                         /* cif_clkin */
1795                                         <3 RK_PA2 2 &pcfg_pull_none>;
1796                         };
1797                 };
1798
1799                 cif-1 {
1800                         dvp_d2d9_m1:dvp-d2d9-m1 {
1801                                 rockchip,pins =
1802                                         /* cif_d0 */
1803                                         <3 RK_PA4 2 &pcfg_pull_none>,
1804                                         /* cif_d1 */
1805                                         <3 RK_PA5 2 &pcfg_pull_none>,
1806                                         /* cif_d2 */
1807                                         <3 RK_PA6 2 &pcfg_pull_none>,
1808                                         /* cif_d3 */
1809                                         <3 RK_PA7 2 &pcfg_pull_none>,
1810                                         /* cif_d4 */
1811                                         <3 RK_PB0 2 &pcfg_pull_none>,
1812                                         /* cif_d5m1 */
1813                                         <2 RK_PC0 4 &pcfg_pull_none>,
1814                                         /* cif_d6m1 */
1815                                         <2 RK_PC1 4 &pcfg_pull_none>,
1816                                         /* cif_d7m1 */
1817                                         <2 RK_PC2 4 &pcfg_pull_none>,
1818                                         /* cif_href */
1819                                         <3 RK_PA1 2 &pcfg_pull_none>,
1820                                         /* cif_vsync */
1821                                         <3 RK_PA0 2 &pcfg_pull_none>,
1822                                         /* cif_clkoutm1 */
1823                                         <2 RK_PB7 4 &pcfg_pull_none>,
1824                                         /* cif_clkin */
1825                                         <3 RK_PA2 2 &pcfg_pull_none>;
1826                         };
1827                 };
1828         };
1829 };