arm64: dts: rockchip: add Gru Scarlet devicetrees
[muen/linux.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4  */
5
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15         compatible = "rockchip,rk3368";
16         interrupt-parent = <&gic>;
17         #address-cells = <2>;
18         #size-cells = <2>;
19
20         aliases {
21                 ethernet0 = &gmac;
22                 i2c0 = &i2c0;
23                 i2c1 = &i2c1;
24                 i2c2 = &i2c2;
25                 i2c3 = &i2c3;
26                 i2c4 = &i2c4;
27                 i2c5 = &i2c5;
28                 serial0 = &uart0;
29                 serial1 = &uart1;
30                 serial2 = &uart2;
31                 serial3 = &uart3;
32                 serial4 = &uart4;
33                 spi0 = &spi0;
34                 spi1 = &spi1;
35                 spi2 = &spi2;
36         };
37
38         cpus {
39                 #address-cells = <0x2>;
40                 #size-cells = <0x0>;
41
42                 cpu-map {
43                         cluster0 {
44                                 core0 {
45                                         cpu = <&cpu_b0>;
46                                 };
47                                 core1 {
48                                         cpu = <&cpu_b1>;
49                                 };
50                                 core2 {
51                                         cpu = <&cpu_b2>;
52                                 };
53                                 core3 {
54                                         cpu = <&cpu_b3>;
55                                 };
56                         };
57
58                         cluster1 {
59                                 core0 {
60                                         cpu = <&cpu_l0>;
61                                 };
62                                 core1 {
63                                         cpu = <&cpu_l1>;
64                                 };
65                                 core2 {
66                                         cpu = <&cpu_l2>;
67                                 };
68                                 core3 {
69                                         cpu = <&cpu_l3>;
70                                 };
71                         };
72                 };
73
74                 cpu_l0: cpu@0 {
75                         device_type = "cpu";
76                         compatible = "arm,cortex-a53", "arm,armv8";
77                         reg = <0x0 0x0>;
78                         enable-method = "psci";
79                         #cooling-cells = <2>; /* min followed by max */
80                 };
81
82                 cpu_l1: cpu@1 {
83                         device_type = "cpu";
84                         compatible = "arm,cortex-a53", "arm,armv8";
85                         reg = <0x0 0x1>;
86                         enable-method = "psci";
87                         #cooling-cells = <2>; /* min followed by max */
88                 };
89
90                 cpu_l2: cpu@2 {
91                         device_type = "cpu";
92                         compatible = "arm,cortex-a53", "arm,armv8";
93                         reg = <0x0 0x2>;
94                         enable-method = "psci";
95                         #cooling-cells = <2>; /* min followed by max */
96                 };
97
98                 cpu_l3: cpu@3 {
99                         device_type = "cpu";
100                         compatible = "arm,cortex-a53", "arm,armv8";
101                         reg = <0x0 0x3>;
102                         enable-method = "psci";
103                         #cooling-cells = <2>; /* min followed by max */
104                 };
105
106                 cpu_b0: cpu@100 {
107                         device_type = "cpu";
108                         compatible = "arm,cortex-a53", "arm,armv8";
109                         reg = <0x0 0x100>;
110                         enable-method = "psci";
111                         #cooling-cells = <2>; /* min followed by max */
112                 };
113
114                 cpu_b1: cpu@101 {
115                         device_type = "cpu";
116                         compatible = "arm,cortex-a53", "arm,armv8";
117                         reg = <0x0 0x101>;
118                         enable-method = "psci";
119                         #cooling-cells = <2>; /* min followed by max */
120                 };
121
122                 cpu_b2: cpu@102 {
123                         device_type = "cpu";
124                         compatible = "arm,cortex-a53", "arm,armv8";
125                         reg = <0x0 0x102>;
126                         enable-method = "psci";
127                         #cooling-cells = <2>; /* min followed by max */
128                 };
129
130                 cpu_b3: cpu@103 {
131                         device_type = "cpu";
132                         compatible = "arm,cortex-a53", "arm,armv8";
133                         reg = <0x0 0x103>;
134                         enable-method = "psci";
135                         #cooling-cells = <2>; /* min followed by max */
136                 };
137         };
138
139         amba {
140                 compatible = "simple-bus";
141                 #address-cells = <2>;
142                 #size-cells = <2>;
143                 ranges;
144
145                 dmac_peri: dma-controller@ff250000 {
146                         compatible = "arm,pl330", "arm,primecell";
147                         reg = <0x0 0xff250000 0x0 0x4000>;
148                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
150                         #dma-cells = <1>;
151                         arm,pl330-broken-no-flushp;
152                         clocks = <&cru ACLK_DMAC_PERI>;
153                         clock-names = "apb_pclk";
154                 };
155
156                 dmac_bus: dma-controller@ff600000 {
157                         compatible = "arm,pl330", "arm,primecell";
158                         reg = <0x0 0xff600000 0x0 0x4000>;
159                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
160                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
161                         #dma-cells = <1>;
162                         arm,pl330-broken-no-flushp;
163                         clocks = <&cru ACLK_DMAC_BUS>;
164                         clock-names = "apb_pclk";
165                 };
166         };
167
168         arm-pmu {
169                 compatible = "arm,armv8-pmuv3";
170                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
171                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
172                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
173                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
174                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
175                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
176                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
177                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
178                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
179                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
180                                      <&cpu_b2>, <&cpu_b3>;
181         };
182
183         psci {
184                 compatible = "arm,psci-0.2";
185                 method = "smc";
186         };
187
188         timer {
189                 compatible = "arm,armv8-timer";
190                 interrupts = <GIC_PPI 13
191                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
192                              <GIC_PPI 14
193                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
194                              <GIC_PPI 11
195                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
196                              <GIC_PPI 10
197                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
198         };
199
200         xin24m: oscillator {
201                 compatible = "fixed-clock";
202                 clock-frequency = <24000000>;
203                 clock-output-names = "xin24m";
204                 #clock-cells = <0>;
205         };
206
207         sdmmc: dwmmc@ff0c0000 {
208                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
209                 reg = <0x0 0xff0c0000 0x0 0x4000>;
210                 max-frequency = <150000000>;
211                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214                 fifo-depth = <0x100>;
215                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
216                 resets = <&cru SRST_MMC0>;
217                 reset-names = "reset";
218                 status = "disabled";
219         };
220
221         sdio0: dwmmc@ff0d0000 {
222                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
223                 reg = <0x0 0xff0d0000 0x0 0x4000>;
224                 max-frequency = <150000000>;
225                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
226                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
227                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228                 fifo-depth = <0x100>;
229                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
230                 resets = <&cru SRST_SDIO0>;
231                 reset-names = "reset";
232                 status = "disabled";
233         };
234
235         emmc: dwmmc@ff0f0000 {
236                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
237                 reg = <0x0 0xff0f0000 0x0 0x4000>;
238                 max-frequency = <150000000>;
239                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
240                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
241                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242                 fifo-depth = <0x100>;
243                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
244                 resets = <&cru SRST_EMMC>;
245                 reset-names = "reset";
246                 status = "disabled";
247         };
248
249         saradc: saradc@ff100000 {
250                 compatible = "rockchip,saradc";
251                 reg = <0x0 0xff100000 0x0 0x100>;
252                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
253                 #io-channel-cells = <1>;
254                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
255                 clock-names = "saradc", "apb_pclk";
256                 resets = <&cru SRST_SARADC>;
257                 reset-names = "saradc-apb";
258                 status = "disabled";
259         };
260
261         spi0: spi@ff110000 {
262                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
263                 reg = <0x0 0xff110000 0x0 0x1000>;
264                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
265                 clock-names = "spiclk", "apb_pclk";
266                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
267                 pinctrl-names = "default";
268                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
269                 #address-cells = <1>;
270                 #size-cells = <0>;
271                 status = "disabled";
272         };
273
274         spi1: spi@ff120000 {
275                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
276                 reg = <0x0 0xff120000 0x0 0x1000>;
277                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
278                 clock-names = "spiclk", "apb_pclk";
279                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
280                 pinctrl-names = "default";
281                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
282                 #address-cells = <1>;
283                 #size-cells = <0>;
284                 status = "disabled";
285         };
286
287         spi2: spi@ff130000 {
288                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
289                 reg = <0x0 0xff130000 0x0 0x1000>;
290                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
291                 clock-names = "spiclk", "apb_pclk";
292                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
293                 pinctrl-names = "default";
294                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
295                 #address-cells = <1>;
296                 #size-cells = <0>;
297                 status = "disabled";
298         };
299
300         i2c2: i2c@ff140000 {
301                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
302                 reg = <0x0 0xff140000 0x0 0x1000>;
303                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
304                 #address-cells = <1>;
305                 #size-cells = <0>;
306                 clock-names = "i2c";
307                 clocks = <&cru PCLK_I2C2>;
308                 pinctrl-names = "default";
309                 pinctrl-0 = <&i2c2_xfer>;
310                 status = "disabled";
311         };
312
313         i2c3: i2c@ff150000 {
314                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
315                 reg = <0x0 0xff150000 0x0 0x1000>;
316                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
317                 #address-cells = <1>;
318                 #size-cells = <0>;
319                 clock-names = "i2c";
320                 clocks = <&cru PCLK_I2C3>;
321                 pinctrl-names = "default";
322                 pinctrl-0 = <&i2c3_xfer>;
323                 status = "disabled";
324         };
325
326         i2c4: i2c@ff160000 {
327                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
328                 reg = <0x0 0xff160000 0x0 0x1000>;
329                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
330                 #address-cells = <1>;
331                 #size-cells = <0>;
332                 clock-names = "i2c";
333                 clocks = <&cru PCLK_I2C4>;
334                 pinctrl-names = "default";
335                 pinctrl-0 = <&i2c4_xfer>;
336                 status = "disabled";
337         };
338
339         i2c5: i2c@ff170000 {
340                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
341                 reg = <0x0 0xff170000 0x0 0x1000>;
342                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
343                 #address-cells = <1>;
344                 #size-cells = <0>;
345                 clock-names = "i2c";
346                 clocks = <&cru PCLK_I2C5>;
347                 pinctrl-names = "default";
348                 pinctrl-0 = <&i2c5_xfer>;
349                 status = "disabled";
350         };
351
352         uart0: serial@ff180000 {
353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354                 reg = <0x0 0xff180000 0x0 0x100>;
355                 clock-frequency = <24000000>;
356                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
357                 clock-names = "baudclk", "apb_pclk";
358                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
359                 reg-shift = <2>;
360                 reg-io-width = <4>;
361                 status = "disabled";
362         };
363
364         uart1: serial@ff190000 {
365                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
366                 reg = <0x0 0xff190000 0x0 0x100>;
367                 clock-frequency = <24000000>;
368                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
369                 clock-names = "baudclk", "apb_pclk";
370                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
371                 reg-shift = <2>;
372                 reg-io-width = <4>;
373                 status = "disabled";
374         };
375
376         uart3: serial@ff1b0000 {
377                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
378                 reg = <0x0 0xff1b0000 0x0 0x100>;
379                 clock-frequency = <24000000>;
380                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
381                 clock-names = "baudclk", "apb_pclk";
382                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
383                 reg-shift = <2>;
384                 reg-io-width = <4>;
385                 status = "disabled";
386         };
387
388         uart4: serial@ff1c0000 {
389                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
390                 reg = <0x0 0xff1c0000 0x0 0x100>;
391                 clock-frequency = <24000000>;
392                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
393                 clock-names = "baudclk", "apb_pclk";
394                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
395                 reg-shift = <2>;
396                 reg-io-width = <4>;
397                 status = "disabled";
398         };
399
400         thermal-zones {
401                 cpu {
402                         polling-delay-passive = <100>; /* milliseconds */
403                         polling-delay = <5000>; /* milliseconds */
404
405                         thermal-sensors = <&tsadc 0>;
406
407                         trips {
408                                 cpu_alert0: cpu_alert0 {
409                                         temperature = <75000>; /* millicelsius */
410                                         hysteresis = <2000>; /* millicelsius */
411                                         type = "passive";
412                                 };
413                                 cpu_alert1: cpu_alert1 {
414                                         temperature = <80000>; /* millicelsius */
415                                         hysteresis = <2000>; /* millicelsius */
416                                         type = "passive";
417                                 };
418                                 cpu_crit: cpu_crit {
419                                         temperature = <95000>; /* millicelsius */
420                                         hysteresis = <2000>; /* millicelsius */
421                                         type = "critical";
422                                 };
423                         };
424
425                         cooling-maps {
426                                 map0 {
427                                         trip = <&cpu_alert0>;
428                                         cooling-device =
429                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
430                                 };
431                                 map1 {
432                                         trip = <&cpu_alert1>;
433                                         cooling-device =
434                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
435                                 };
436                         };
437                 };
438
439                 gpu {
440                         polling-delay-passive = <100>; /* milliseconds */
441                         polling-delay = <5000>; /* milliseconds */
442
443                         thermal-sensors = <&tsadc 1>;
444
445                         trips {
446                                 gpu_alert0: gpu_alert0 {
447                                         temperature = <80000>; /* millicelsius */
448                                         hysteresis = <2000>; /* millicelsius */
449                                         type = "passive";
450                                 };
451                                 gpu_crit: gpu_crit {
452                                         temperature = <115000>; /* millicelsius */
453                                         hysteresis = <2000>; /* millicelsius */
454                                         type = "critical";
455                                 };
456                         };
457
458                         cooling-maps {
459                                 map0 {
460                                         trip = <&gpu_alert0>;
461                                         cooling-device =
462                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
463                                 };
464                         };
465                 };
466         };
467
468         tsadc: tsadc@ff280000 {
469                 compatible = "rockchip,rk3368-tsadc";
470                 reg = <0x0 0xff280000 0x0 0x100>;
471                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
472                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
473                 clock-names = "tsadc", "apb_pclk";
474                 resets = <&cru SRST_TSADC>;
475                 reset-names = "tsadc-apb";
476                 pinctrl-names = "init", "default", "sleep";
477                 pinctrl-0 = <&otp_gpio>;
478                 pinctrl-1 = <&otp_out>;
479                 pinctrl-2 = <&otp_gpio>;
480                 #thermal-sensor-cells = <1>;
481                 rockchip,hw-tshut-temp = <95000>;
482                 status = "disabled";
483         };
484
485         gmac: ethernet@ff290000 {
486                 compatible = "rockchip,rk3368-gmac";
487                 reg = <0x0 0xff290000 0x0 0x10000>;
488                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
489                 interrupt-names = "macirq";
490                 rockchip,grf = <&grf>;
491                 clocks = <&cru SCLK_MAC>,
492                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
493                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
494                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
495                 clock-names = "stmmaceth",
496                         "mac_clk_rx", "mac_clk_tx",
497                         "clk_mac_ref", "clk_mac_refout",
498                         "aclk_mac", "pclk_mac";
499                 status = "disabled";
500         };
501
502         usb_host0_ehci: usb@ff500000 {
503                 compatible = "generic-ehci";
504                 reg = <0x0 0xff500000 0x0 0x100>;
505                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
506                 clocks = <&cru HCLK_HOST0>;
507                 clock-names = "usbhost";
508                 status = "disabled";
509         };
510
511         usb_otg: usb@ff580000 {
512                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
513                                 "snps,dwc2";
514                 reg = <0x0 0xff580000 0x0 0x40000>;
515                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
516                 clocks = <&cru HCLK_OTG0>;
517                 clock-names = "otg";
518                 dr_mode = "otg";
519                 g-np-tx-fifo-size = <16>;
520                 g-rx-fifo-size = <275>;
521                 g-tx-fifo-size = <256 128 128 64 64 32>;
522                 status = "disabled";
523         };
524
525         i2c0: i2c@ff650000 {
526                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
527                 reg = <0x0 0xff650000 0x0 0x1000>;
528                 clocks = <&cru PCLK_I2C0>;
529                 clock-names = "i2c";
530                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
531                 pinctrl-names = "default";
532                 pinctrl-0 = <&i2c0_xfer>;
533                 #address-cells = <1>;
534                 #size-cells = <0>;
535                 status = "disabled";
536         };
537
538         i2c1: i2c@ff660000 {
539                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
540                 reg = <0x0 0xff660000 0x0 0x1000>;
541                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
542                 #address-cells = <1>;
543                 #size-cells = <0>;
544                 clock-names = "i2c";
545                 clocks = <&cru PCLK_I2C1>;
546                 pinctrl-names = "default";
547                 pinctrl-0 = <&i2c1_xfer>;
548                 status = "disabled";
549         };
550
551         pwm0: pwm@ff680000 {
552                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
553                 reg = <0x0 0xff680000 0x0 0x10>;
554                 #pwm-cells = <3>;
555                 pinctrl-names = "default";
556                 pinctrl-0 = <&pwm0_pin>;
557                 clocks = <&cru PCLK_PWM1>;
558                 clock-names = "pwm";
559                 status = "disabled";
560         };
561
562         pwm1: pwm@ff680010 {
563                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
564                 reg = <0x0 0xff680010 0x0 0x10>;
565                 #pwm-cells = <3>;
566                 pinctrl-names = "default";
567                 pinctrl-0 = <&pwm1_pin>;
568                 clocks = <&cru PCLK_PWM1>;
569                 clock-names = "pwm";
570                 status = "disabled";
571         };
572
573         pwm2: pwm@ff680020 {
574                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
575                 reg = <0x0 0xff680020 0x0 0x10>;
576                 #pwm-cells = <3>;
577                 clocks = <&cru PCLK_PWM1>;
578                 clock-names = "pwm";
579                 status = "disabled";
580         };
581
582         pwm3: pwm@ff680030 {
583                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
584                 reg = <0x0 0xff680030 0x0 0x10>;
585                 #pwm-cells = <3>;
586                 pinctrl-names = "default";
587                 pinctrl-0 = <&pwm3_pin>;
588                 clocks = <&cru PCLK_PWM1>;
589                 clock-names = "pwm";
590                 status = "disabled";
591         };
592
593         uart2: serial@ff690000 {
594                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
595                 reg = <0x0 0xff690000 0x0 0x100>;
596                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
597                 clock-names = "baudclk", "apb_pclk";
598                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
599                 pinctrl-names = "default";
600                 pinctrl-0 = <&uart2_xfer>;
601                 reg-shift = <2>;
602                 reg-io-width = <4>;
603                 status = "disabled";
604         };
605
606         mbox: mbox@ff6b0000 {
607                 compatible = "rockchip,rk3368-mailbox";
608                 reg = <0x0 0xff6b0000 0x0 0x1000>;
609                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
610                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
611                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
612                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
613                 clocks = <&cru PCLK_MAILBOX>;
614                 clock-names = "pclk_mailbox";
615                 #mbox-cells = <1>;
616                 status = "disabled";
617         };
618
619         pmugrf: syscon@ff738000 {
620                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
621                 reg = <0x0 0xff738000 0x0 0x1000>;
622
623                 pmu_io_domains: io-domains {
624                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
625                         status = "disabled";
626                 };
627
628                 reboot-mode {
629                         compatible = "syscon-reboot-mode";
630                         offset = <0x200>;
631                         mode-normal = <BOOT_NORMAL>;
632                         mode-recovery = <BOOT_RECOVERY>;
633                         mode-bootloader = <BOOT_FASTBOOT>;
634                         mode-loader = <BOOT_BL_DOWNLOAD>;
635                 };
636         };
637
638         cru: clock-controller@ff760000 {
639                 compatible = "rockchip,rk3368-cru";
640                 reg = <0x0 0xff760000 0x0 0x1000>;
641                 rockchip,grf = <&grf>;
642                 #clock-cells = <1>;
643                 #reset-cells = <1>;
644         };
645
646         grf: syscon@ff770000 {
647                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
648                 reg = <0x0 0xff770000 0x0 0x1000>;
649
650                 io_domains: io-domains {
651                         compatible = "rockchip,rk3368-io-voltage-domain";
652                         status = "disabled";
653                 };
654         };
655
656         wdt: watchdog@ff800000 {
657                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
658                 reg = <0x0 0xff800000 0x0 0x100>;
659                 clocks = <&cru PCLK_WDT>;
660                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
661                 status = "disabled";
662         };
663
664         timer@ff810000 {
665                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
666                 reg = <0x0 0xff810000 0x0 0x20>;
667                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
668         };
669
670         spdif: spdif@ff880000 {
671                 compatible = "rockchip,rk3368-spdif";
672                 reg = <0x0 0xff880000 0x0 0x1000>;
673                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
674                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
675                 clock-names = "mclk", "hclk";
676                 dmas = <&dmac_bus 3>;
677                 dma-names = "tx";
678                 pinctrl-names = "default";
679                 pinctrl-0 = <&spdif_tx>;
680                 status = "disabled";
681         };
682
683         i2s_2ch: i2s-2ch@ff890000 {
684                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
685                 reg = <0x0 0xff890000 0x0 0x1000>;
686                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
687                 clock-names = "i2s_clk", "i2s_hclk";
688                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
689                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
690                 dma-names = "tx", "rx";
691                 status = "disabled";
692         };
693
694         i2s_8ch: i2s-8ch@ff898000 {
695                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
696                 reg = <0x0 0xff898000 0x0 0x1000>;
697                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
698                 clock-names = "i2s_clk", "i2s_hclk";
699                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
700                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
701                 dma-names = "tx", "rx";
702                 pinctrl-names = "default";
703                 pinctrl-0 = <&i2s_8ch_bus>;
704                 status = "disabled";
705         };
706
707         iep_mmu: iommu@ff900800 {
708                 compatible = "rockchip,iommu";
709                 reg = <0x0 0xff900800 0x0 0x100>;
710                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
711                 interrupt-names = "iep_mmu";
712                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
713                 clock-names = "aclk", "iface";
714                 #iommu-cells = <0>;
715                 status = "disabled";
716         };
717
718         isp_mmu: iommu@ff914000 {
719                 compatible = "rockchip,iommu";
720                 reg = <0x0 0xff914000 0x0 0x100>,
721                       <0x0 0xff915000 0x0 0x100>;
722                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
723                 interrupt-names = "isp_mmu";
724                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
725                 clock-names = "aclk", "iface";
726                 #iommu-cells = <0>;
727                 rockchip,disable-mmu-reset;
728                 status = "disabled";
729         };
730
731         vop_mmu: iommu@ff930300 {
732                 compatible = "rockchip,iommu";
733                 reg = <0x0 0xff930300 0x0 0x100>;
734                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
735                 interrupt-names = "vop_mmu";
736                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
737                 clock-names = "aclk", "iface";
738                 #iommu-cells = <0>;
739                 status = "disabled";
740         };
741
742         hevc_mmu: iommu@ff9a0440 {
743                 compatible = "rockchip,iommu";
744                 reg = <0x0 0xff9a0440 0x0 0x40>,
745                       <0x0 0xff9a0480 0x0 0x40>;
746                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
747                 interrupt-names = "hevc_mmu";
748                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
749                 clock-names = "aclk", "iface";
750                 #iommu-cells = <0>;
751                 status = "disabled";
752         };
753
754         vpu_mmu: iommu@ff9a0800 {
755                 compatible = "rockchip,iommu";
756                 reg = <0x0 0xff9a0800 0x0 0x100>;
757                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
758                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
759                 interrupt-names = "vepu_mmu", "vdpu_mmu";
760                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
761                 clock-names = "aclk", "iface";
762                 #iommu-cells = <0>;
763                 status = "disabled";
764         };
765
766         efuse256: efuse@ffb00000 {
767                 compatible = "rockchip,rk3368-efuse";
768                 reg = <0x0 0xffb00000 0x0 0x20>;
769                 #address-cells = <1>;
770                 #size-cells = <1>;
771                 clocks = <&cru PCLK_EFUSE256>;
772                 clock-names = "pclk_efuse";
773
774                 cpu_leakage: cpu-leakage@17 {
775                         reg = <0x17 0x1>;
776                 };
777                 temp_adjust: temp-adjust@1f {
778                         reg = <0x1f 0x1>;
779                 };
780         };
781
782         gic: interrupt-controller@ffb71000 {
783                 compatible = "arm,gic-400";
784                 interrupt-controller;
785                 #interrupt-cells = <3>;
786                 #address-cells = <0>;
787
788                 reg = <0x0 0xffb71000 0x0 0x1000>,
789                       <0x0 0xffb72000 0x0 0x2000>,
790                       <0x0 0xffb74000 0x0 0x2000>,
791                       <0x0 0xffb76000 0x0 0x2000>;
792                 interrupts = <GIC_PPI 9
793                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
794         };
795
796         pinctrl: pinctrl {
797                 compatible = "rockchip,rk3368-pinctrl";
798                 rockchip,grf = <&grf>;
799                 rockchip,pmu = <&pmugrf>;
800                 #address-cells = <0x2>;
801                 #size-cells = <0x2>;
802                 ranges;
803
804                 gpio0: gpio0@ff750000 {
805                         compatible = "rockchip,gpio-bank";
806                         reg = <0x0 0xff750000 0x0 0x100>;
807                         clocks = <&cru PCLK_GPIO0>;
808                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
809
810                         gpio-controller;
811                         #gpio-cells = <0x2>;
812
813                         interrupt-controller;
814                         #interrupt-cells = <0x2>;
815                 };
816
817                 gpio1: gpio1@ff780000 {
818                         compatible = "rockchip,gpio-bank";
819                         reg = <0x0 0xff780000 0x0 0x100>;
820                         clocks = <&cru PCLK_GPIO1>;
821                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
822
823                         gpio-controller;
824                         #gpio-cells = <0x2>;
825
826                         interrupt-controller;
827                         #interrupt-cells = <0x2>;
828                 };
829
830                 gpio2: gpio2@ff790000 {
831                         compatible = "rockchip,gpio-bank";
832                         reg = <0x0 0xff790000 0x0 0x100>;
833                         clocks = <&cru PCLK_GPIO2>;
834                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
835
836                         gpio-controller;
837                         #gpio-cells = <0x2>;
838
839                         interrupt-controller;
840                         #interrupt-cells = <0x2>;
841                 };
842
843                 gpio3: gpio3@ff7a0000 {
844                         compatible = "rockchip,gpio-bank";
845                         reg = <0x0 0xff7a0000 0x0 0x100>;
846                         clocks = <&cru PCLK_GPIO3>;
847                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
848
849                         gpio-controller;
850                         #gpio-cells = <0x2>;
851
852                         interrupt-controller;
853                         #interrupt-cells = <0x2>;
854                 };
855
856                 pcfg_pull_up: pcfg-pull-up {
857                         bias-pull-up;
858                 };
859
860                 pcfg_pull_down: pcfg-pull-down {
861                         bias-pull-down;
862                 };
863
864                 pcfg_pull_none: pcfg-pull-none {
865                         bias-disable;
866                 };
867
868                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
869                         bias-disable;
870                         drive-strength = <12>;
871                 };
872
873                 emmc {
874                         emmc_clk: emmc-clk {
875                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
876                         };
877
878                         emmc_cmd: emmc-cmd {
879                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
880                         };
881
882                         emmc_pwr: emmc-pwr {
883                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
884                         };
885
886                         emmc_bus1: emmc-bus1 {
887                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
888                         };
889
890                         emmc_bus4: emmc-bus4 {
891                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
892                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
893                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
894                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
895                         };
896
897                         emmc_bus8: emmc-bus8 {
898                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
899                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
900                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
901                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
902                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
903                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
904                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
905                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
906                         };
907                 };
908
909                 gmac {
910                         rgmii_pins: rgmii-pins {
911                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
912                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
913                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
914                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
915                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
916                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
917                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
918                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
919                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
920                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
921                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
922                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
923                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
924                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
925                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
926                         };
927
928                         rmii_pins: rmii-pins {
929                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
930                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
931                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
932                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
933                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
934                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
935                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
936                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
937                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
938                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
939                         };
940                 };
941
942                 i2c0 {
943                         i2c0_xfer: i2c0-xfer {
944                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
945                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
946                         };
947                 };
948
949                 i2c1 {
950                         i2c1_xfer: i2c1-xfer {
951                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
952                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
953                         };
954                 };
955
956                 i2c2 {
957                         i2c2_xfer: i2c2-xfer {
958                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
959                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
960                         };
961                 };
962
963                 i2c3 {
964                         i2c3_xfer: i2c3-xfer {
965                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
966                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
967                         };
968                 };
969
970                 i2c4 {
971                         i2c4_xfer: i2c4-xfer {
972                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
973                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
974                         };
975                 };
976
977                 i2c5 {
978                         i2c5_xfer: i2c5-xfer {
979                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
980                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
981                         };
982                 };
983
984                 i2s {
985                         i2s_8ch_bus: i2s-8ch-bus {
986                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
987                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
988                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
989                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
990                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
991                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
992                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
993                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
994                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
995                         };
996                 };
997
998                 pwm0 {
999                         pwm0_pin: pwm0-pin {
1000                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 pwm1 {
1005                         pwm1_pin: pwm1-pin {
1006                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1007                         };
1008                 };
1009
1010                 pwm3 {
1011                         pwm3_pin: pwm3-pin {
1012                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1013                         };
1014                 };
1015
1016                 sdio0 {
1017                         sdio0_bus1: sdio0-bus1 {
1018                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1019                         };
1020
1021                         sdio0_bus4: sdio0-bus4 {
1022                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1023                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1024                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1025                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1026                         };
1027
1028                         sdio0_cmd: sdio0-cmd {
1029                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1030                         };
1031
1032                         sdio0_clk: sdio0-clk {
1033                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1034                         };
1035
1036                         sdio0_cd: sdio0-cd {
1037                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1038                         };
1039
1040                         sdio0_wp: sdio0-wp {
1041                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1042                         };
1043
1044                         sdio0_pwr: sdio0-pwr {
1045                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1046                         };
1047
1048                         sdio0_bkpwr: sdio0-bkpwr {
1049                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1050                         };
1051
1052                         sdio0_int: sdio0-int {
1053                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1054                         };
1055                 };
1056
1057                 sdmmc {
1058                         sdmmc_clk: sdmmc-clk {
1059                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1060                         };
1061
1062                         sdmmc_cmd: sdmmc-cmd {
1063                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1064                         };
1065
1066                         sdmmc_cd: sdmmc-cd {
1067                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1068                         };
1069
1070                         sdmmc_bus1: sdmmc-bus1 {
1071                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1072                         };
1073
1074                         sdmmc_bus4: sdmmc-bus4 {
1075                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1076                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1077                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1078                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1079                         };
1080                 };
1081
1082                 spdif {
1083                         spdif_tx: spdif-tx {
1084                                 rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1085                         };
1086                 };
1087
1088                 spi0 {
1089                         spi0_clk: spi0-clk {
1090                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1091                         };
1092                         spi0_cs0: spi0-cs0 {
1093                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1094                         };
1095                         spi0_cs1: spi0-cs1 {
1096                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1097                         };
1098                         spi0_tx: spi0-tx {
1099                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1100                         };
1101                         spi0_rx: spi0-rx {
1102                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1103                         };
1104                 };
1105
1106                 spi1 {
1107                         spi1_clk: spi1-clk {
1108                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1109                         };
1110                         spi1_cs0: spi1-cs0 {
1111                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1112                         };
1113                         spi1_cs1: spi1-cs1 {
1114                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1115                         };
1116                         spi1_rx: spi1-rx {
1117                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1118                         };
1119                         spi1_tx: spi1-tx {
1120                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1121                         };
1122                 };
1123
1124                 spi2 {
1125                         spi2_clk: spi2-clk {
1126                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1127                         };
1128                         spi2_cs0: spi2-cs0 {
1129                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1130                         };
1131                         spi2_rx: spi2-rx {
1132                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1133                         };
1134                         spi2_tx: spi2-tx {
1135                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1136                         };
1137                 };
1138
1139                 tsadc {
1140                         otp_gpio: otp-gpio {
1141                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1142                         };
1143
1144                         otp_out: otp-out {
1145                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1146                         };
1147                 };
1148
1149                 uart0 {
1150                         uart0_xfer: uart0-xfer {
1151                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1152                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1153                         };
1154
1155                         uart0_cts: uart0-cts {
1156                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1157                         };
1158
1159                         uart0_rts: uart0-rts {
1160                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162                 };
1163
1164                 uart1 {
1165                         uart1_xfer: uart1-xfer {
1166                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1167                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1168                         };
1169
1170                         uart1_cts: uart1-cts {
1171                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1172                         };
1173
1174                         uart1_rts: uart1-rts {
1175                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1176                         };
1177                 };
1178
1179                 uart2 {
1180                         uart2_xfer: uart2-xfer {
1181                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1182                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1183                         };
1184                         /* no rts / cts for uart2 */
1185                 };
1186
1187                 uart3 {
1188                         uart3_xfer: uart3-xfer {
1189                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1190                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1191                         };
1192
1193                         uart3_cts: uart3-cts {
1194                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1195                         };
1196
1197                         uart3_rts: uart3-rts {
1198                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 uart4 {
1203                         uart4_xfer: uart4-xfer {
1204                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1205                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1206                         };
1207
1208                         uart4_cts: uart4-cts {
1209                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1210                         };
1211
1212                         uart4_rts: uart4-rts {
1213                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1214                         };
1215                 };
1216         };
1217 };