arm64: dts: rockchip: Add all CPUs in cooling maps
[muen/linux.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4  */
5
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15         compatible = "rockchip,rk3399";
16
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
20
21         aliases {
22                 ethernet0 = &gmac;
23                 i2c0 = &i2c0;
24                 i2c1 = &i2c1;
25                 i2c2 = &i2c2;
26                 i2c3 = &i2c3;
27                 i2c4 = &i2c4;
28                 i2c5 = &i2c5;
29                 i2c6 = &i2c6;
30                 i2c7 = &i2c7;
31                 i2c8 = &i2c8;
32                 serial0 = &uart0;
33                 serial1 = &uart1;
34                 serial2 = &uart2;
35                 serial3 = &uart3;
36                 serial4 = &uart4;
37         };
38
39         cpus {
40                 #address-cells = <2>;
41                 #size-cells = <0>;
42
43                 cpu-map {
44                         cluster0 {
45                                 core0 {
46                                         cpu = <&cpu_l0>;
47                                 };
48                                 core1 {
49                                         cpu = <&cpu_l1>;
50                                 };
51                                 core2 {
52                                         cpu = <&cpu_l2>;
53                                 };
54                                 core3 {
55                                         cpu = <&cpu_l3>;
56                                 };
57                         };
58
59                         cluster1 {
60                                 core0 {
61                                         cpu = <&cpu_b0>;
62                                 };
63                                 core1 {
64                                         cpu = <&cpu_b1>;
65                                 };
66                         };
67                 };
68
69                 cpu_l0: cpu@0 {
70                         device_type = "cpu";
71                         compatible = "arm,cortex-a53", "arm,armv8";
72                         reg = <0x0 0x0>;
73                         enable-method = "psci";
74                         clocks = <&cru ARMCLKL>;
75                         #cooling-cells = <2>; /* min followed by max */
76                         dynamic-power-coefficient = <100>;
77                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
78                 };
79
80                 cpu_l1: cpu@1 {
81                         device_type = "cpu";
82                         compatible = "arm,cortex-a53", "arm,armv8";
83                         reg = <0x0 0x1>;
84                         enable-method = "psci";
85                         clocks = <&cru ARMCLKL>;
86                         #cooling-cells = <2>; /* min followed by max */
87                         dynamic-power-coefficient = <100>;
88                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
89                 };
90
91                 cpu_l2: cpu@2 {
92                         device_type = "cpu";
93                         compatible = "arm,cortex-a53", "arm,armv8";
94                         reg = <0x0 0x2>;
95                         enable-method = "psci";
96                         clocks = <&cru ARMCLKL>;
97                         #cooling-cells = <2>; /* min followed by max */
98                         dynamic-power-coefficient = <100>;
99                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
100                 };
101
102                 cpu_l3: cpu@3 {
103                         device_type = "cpu";
104                         compatible = "arm,cortex-a53", "arm,armv8";
105                         reg = <0x0 0x3>;
106                         enable-method = "psci";
107                         clocks = <&cru ARMCLKL>;
108                         #cooling-cells = <2>; /* min followed by max */
109                         dynamic-power-coefficient = <100>;
110                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
111                 };
112
113                 cpu_b0: cpu@100 {
114                         device_type = "cpu";
115                         compatible = "arm,cortex-a72", "arm,armv8";
116                         reg = <0x0 0x100>;
117                         enable-method = "psci";
118                         clocks = <&cru ARMCLKB>;
119                         #cooling-cells = <2>; /* min followed by max */
120                         dynamic-power-coefficient = <436>;
121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122                 };
123
124                 cpu_b1: cpu@101 {
125                         device_type = "cpu";
126                         compatible = "arm,cortex-a72", "arm,armv8";
127                         reg = <0x0 0x101>;
128                         enable-method = "psci";
129                         clocks = <&cru ARMCLKB>;
130                         #cooling-cells = <2>; /* min followed by max */
131                         dynamic-power-coefficient = <436>;
132                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
133                 };
134
135                 idle-states {
136                         entry-method = "psci";
137
138                         CPU_SLEEP: cpu-sleep {
139                                 compatible = "arm,idle-state";
140                                 local-timer-stop;
141                                 arm,psci-suspend-param = <0x0010000>;
142                                 entry-latency-us = <120>;
143                                 exit-latency-us = <250>;
144                                 min-residency-us = <900>;
145                         };
146
147                         CLUSTER_SLEEP: cluster-sleep {
148                                 compatible = "arm,idle-state";
149                                 local-timer-stop;
150                                 arm,psci-suspend-param = <0x1010000>;
151                                 entry-latency-us = <400>;
152                                 exit-latency-us = <500>;
153                                 min-residency-us = <2000>;
154                         };
155                 };
156         };
157
158         display-subsystem {
159                 compatible = "rockchip,display-subsystem";
160                 ports = <&vopl_out>, <&vopb_out>;
161         };
162
163         pmu_a53 {
164                 compatible = "arm,cortex-a53-pmu";
165                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
166         };
167
168         pmu_a72 {
169                 compatible = "arm,cortex-a72-pmu";
170                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
171         };
172
173         psci {
174                 compatible = "arm,psci-1.0";
175                 method = "smc";
176         };
177
178         timer {
179                 compatible = "arm,armv8-timer";
180                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
181                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
182                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
183                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
184                 arm,no-tick-in-suspend;
185         };
186
187         xin24m: xin24m {
188                 compatible = "fixed-clock";
189                 clock-frequency = <24000000>;
190                 clock-output-names = "xin24m";
191                 #clock-cells = <0>;
192         };
193
194         amba {
195                 compatible = "simple-bus";
196                 #address-cells = <2>;
197                 #size-cells = <2>;
198                 ranges;
199
200                 dmac_bus: dma-controller@ff6d0000 {
201                         compatible = "arm,pl330", "arm,primecell";
202                         reg = <0x0 0xff6d0000 0x0 0x4000>;
203                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
204                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
205                         #dma-cells = <1>;
206                         clocks = <&cru ACLK_DMAC0_PERILP>;
207                         clock-names = "apb_pclk";
208                 };
209
210                 dmac_peri: dma-controller@ff6e0000 {
211                         compatible = "arm,pl330", "arm,primecell";
212                         reg = <0x0 0xff6e0000 0x0 0x4000>;
213                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
214                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
215                         #dma-cells = <1>;
216                         clocks = <&cru ACLK_DMAC1_PERILP>;
217                         clock-names = "apb_pclk";
218                 };
219         };
220
221         pcie0: pcie@f8000000 {
222                 compatible = "rockchip,rk3399-pcie";
223                 reg = <0x0 0xf8000000 0x0 0x2000000>,
224                       <0x0 0xfd000000 0x0 0x1000000>;
225                 reg-names = "axi-base", "apb-base";
226                 #address-cells = <3>;
227                 #size-cells = <2>;
228                 #interrupt-cells = <1>;
229                 aspm-no-l0s;
230                 bus-range = <0x0 0x1f>;
231                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
232                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
233                 clock-names = "aclk", "aclk-perf",
234                               "hclk", "pm";
235                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
236                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
237                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
238                 interrupt-names = "sys", "legacy", "client";
239                 interrupt-map-mask = <0 0 0 7>;
240                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
241                                 <0 0 0 2 &pcie0_intc 1>,
242                                 <0 0 0 3 &pcie0_intc 2>,
243                                 <0 0 0 4 &pcie0_intc 3>;
244                 linux,pci-domain = <0>;
245                 max-link-speed = <1>;
246                 msi-map = <0x0 &its 0x0 0x1000>;
247                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
248                        <&pcie_phy 2>, <&pcie_phy 3>;
249                 phy-names = "pcie-phy-0", "pcie-phy-1",
250                             "pcie-phy-2", "pcie-phy-3";
251                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
252                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
253                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
254                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
255                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
256                          <&cru SRST_A_PCIE>;
257                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
258                               "pm", "pclk", "aclk";
259                 status = "disabled";
260
261                 pcie0_intc: interrupt-controller {
262                         interrupt-controller;
263                         #address-cells = <0>;
264                         #interrupt-cells = <1>;
265                 };
266         };
267
268         gmac: ethernet@fe300000 {
269                 compatible = "rockchip,rk3399-gmac";
270                 reg = <0x0 0xfe300000 0x0 0x10000>;
271                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
272                 interrupt-names = "macirq";
273                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
274                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
275                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
276                          <&cru PCLK_GMAC>;
277                 clock-names = "stmmaceth", "mac_clk_rx",
278                               "mac_clk_tx", "clk_mac_ref",
279                               "clk_mac_refout", "aclk_mac",
280                               "pclk_mac";
281                 power-domains = <&power RK3399_PD_GMAC>;
282                 resets = <&cru SRST_A_GMAC>;
283                 reset-names = "stmmaceth";
284                 rockchip,grf = <&grf>;
285                 status = "disabled";
286         };
287
288         sdio0: dwmmc@fe310000 {
289                 compatible = "rockchip,rk3399-dw-mshc",
290                              "rockchip,rk3288-dw-mshc";
291                 reg = <0x0 0xfe310000 0x0 0x4000>;
292                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
293                 max-frequency = <150000000>;
294                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
295                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
296                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
297                 fifo-depth = <0x100>;
298                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
299                 resets = <&cru SRST_SDIO0>;
300                 reset-names = "reset";
301                 status = "disabled";
302         };
303
304         sdmmc: dwmmc@fe320000 {
305                 compatible = "rockchip,rk3399-dw-mshc",
306                              "rockchip,rk3288-dw-mshc";
307                 reg = <0x0 0xfe320000 0x0 0x4000>;
308                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
309                 max-frequency = <150000000>;
310                 assigned-clocks = <&cru HCLK_SD>;
311                 assigned-clock-rates = <200000000>;
312                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
313                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
314                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
315                 fifo-depth = <0x100>;
316                 power-domains = <&power RK3399_PD_SD>;
317                 resets = <&cru SRST_SDMMC>;
318                 reset-names = "reset";
319                 status = "disabled";
320         };
321
322         sdhci: sdhci@fe330000 {
323                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
324                 reg = <0x0 0xfe330000 0x0 0x10000>;
325                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
326                 arasan,soc-ctl-syscon = <&grf>;
327                 assigned-clocks = <&cru SCLK_EMMC>;
328                 assigned-clock-rates = <200000000>;
329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
330                 clock-names = "clk_xin", "clk_ahb";
331                 clock-output-names = "emmc_cardclock";
332                 #clock-cells = <0>;
333                 phys = <&emmc_phy>;
334                 phy-names = "phy_arasan";
335                 power-domains = <&power RK3399_PD_EMMC>;
336                 status = "disabled";
337         };
338
339         usb_host0_ehci: usb@fe380000 {
340                 compatible = "generic-ehci";
341                 reg = <0x0 0xfe380000 0x0 0x20000>;
342                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
343                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
344                          <&u2phy0>;
345                 clock-names = "usbhost", "arbiter",
346                               "utmi";
347                 phys = <&u2phy0_host>;
348                 phy-names = "usb";
349                 status = "disabled";
350         };
351
352         usb_host0_ohci: usb@fe3a0000 {
353                 compatible = "generic-ohci";
354                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
357                          <&u2phy0>;
358                 clock-names = "usbhost", "arbiter",
359                               "utmi";
360                 phys = <&u2phy0_host>;
361                 phy-names = "usb";
362                 status = "disabled";
363         };
364
365         usb_host1_ehci: usb@fe3c0000 {
366                 compatible = "generic-ehci";
367                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
368                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
369                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
370                          <&u2phy1>;
371                 clock-names = "usbhost", "arbiter",
372                               "utmi";
373                 phys = <&u2phy1_host>;
374                 phy-names = "usb";
375                 status = "disabled";
376         };
377
378         usb_host1_ohci: usb@fe3e0000 {
379                 compatible = "generic-ohci";
380                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
381                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
382                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
383                          <&u2phy1>;
384                 clock-names = "usbhost", "arbiter",
385                               "utmi";
386                 phys = <&u2phy1_host>;
387                 phy-names = "usb";
388                 status = "disabled";
389         };
390
391         usbdrd3_0: usb@fe800000 {
392                 compatible = "rockchip,rk3399-dwc3";
393                 #address-cells = <2>;
394                 #size-cells = <2>;
395                 ranges;
396                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
397                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
398                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
399                 clock-names = "ref_clk", "suspend_clk",
400                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
401                               "aclk_usb3", "grf_clk";
402                 resets = <&cru SRST_A_USB3_OTG0>;
403                 reset-names = "usb3-otg";
404                 status = "disabled";
405
406                 usbdrd_dwc3_0: dwc3 {
407                         compatible = "snps,dwc3";
408                         reg = <0x0 0xfe800000 0x0 0x100000>;
409                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
410                         dr_mode = "otg";
411                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
412                         phy-names = "usb2-phy", "usb3-phy";
413                         phy_type = "utmi_wide";
414                         snps,dis_enblslpm_quirk;
415                         snps,dis-u2-freeclk-exists-quirk;
416                         snps,dis_u2_susphy_quirk;
417                         snps,dis-del-phy-power-chg-quirk;
418                         snps,dis-tx-ipgap-linecheck-quirk;
419                         power-domains = <&power RK3399_PD_USB3>;
420                         status = "disabled";
421                 };
422         };
423
424         usbdrd3_1: usb@fe900000 {
425                 compatible = "rockchip,rk3399-dwc3";
426                 #address-cells = <2>;
427                 #size-cells = <2>;
428                 ranges;
429                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
430                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
431                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
432                 clock-names = "ref_clk", "suspend_clk",
433                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
434                               "aclk_usb3", "grf_clk";
435                 resets = <&cru SRST_A_USB3_OTG1>;
436                 reset-names = "usb3-otg";
437                 status = "disabled";
438
439                 usbdrd_dwc3_1: dwc3 {
440                         compatible = "snps,dwc3";
441                         reg = <0x0 0xfe900000 0x0 0x100000>;
442                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
443                         dr_mode = "otg";
444                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
445                         phy-names = "usb2-phy", "usb3-phy";
446                         phy_type = "utmi_wide";
447                         snps,dis_enblslpm_quirk;
448                         snps,dis-u2-freeclk-exists-quirk;
449                         snps,dis_u2_susphy_quirk;
450                         snps,dis-del-phy-power-chg-quirk;
451                         snps,dis-tx-ipgap-linecheck-quirk;
452                         power-domains = <&power RK3399_PD_USB3>;
453                         status = "disabled";
454                 };
455         };
456
457         cdn_dp: dp@fec00000 {
458                 compatible = "rockchip,rk3399-cdn-dp";
459                 reg = <0x0 0xfec00000 0x0 0x100000>;
460                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
461                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
462                 assigned-clock-rates = <100000000>, <200000000>;
463                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
464                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
465                 clock-names = "core-clk", "pclk", "spdif", "grf";
466                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
467                 power-domains = <&power RK3399_PD_HDCP>;
468                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
469                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
470                 reset-names = "spdif", "dptx", "apb", "core";
471                 rockchip,grf = <&grf>;
472                 #sound-dai-cells = <1>;
473                 status = "disabled";
474
475                 ports {
476                         dp_in: port {
477                                 #address-cells = <1>;
478                                 #size-cells = <0>;
479
480                                 dp_in_vopb: endpoint@0 {
481                                         reg = <0>;
482                                         remote-endpoint = <&vopb_out_dp>;
483                                 };
484
485                                 dp_in_vopl: endpoint@1 {
486                                         reg = <1>;
487                                         remote-endpoint = <&vopl_out_dp>;
488                                 };
489                         };
490                 };
491         };
492
493         gic: interrupt-controller@fee00000 {
494                 compatible = "arm,gic-v3";
495                 #interrupt-cells = <4>;
496                 #address-cells = <2>;
497                 #size-cells = <2>;
498                 ranges;
499                 interrupt-controller;
500
501                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
502                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
503                       <0x0 0xfff00000 0 0x10000>, /* GICC */
504                       <0x0 0xfff10000 0 0x10000>, /* GICH */
505                       <0x0 0xfff20000 0 0x10000>; /* GICV */
506                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
507                 its: interrupt-controller@fee20000 {
508                         compatible = "arm,gic-v3-its";
509                         msi-controller;
510                         reg = <0x0 0xfee20000 0x0 0x20000>;
511                 };
512
513                 ppi-partitions {
514                         ppi_cluster0: interrupt-partition-0 {
515                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
516                         };
517
518                         ppi_cluster1: interrupt-partition-1 {
519                                 affinity = <&cpu_b0 &cpu_b1>;
520                         };
521                 };
522         };
523
524         saradc: saradc@ff100000 {
525                 compatible = "rockchip,rk3399-saradc";
526                 reg = <0x0 0xff100000 0x0 0x100>;
527                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
528                 #io-channel-cells = <1>;
529                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
530                 clock-names = "saradc", "apb_pclk";
531                 resets = <&cru SRST_P_SARADC>;
532                 reset-names = "saradc-apb";
533                 status = "disabled";
534         };
535
536         i2c1: i2c@ff110000 {
537                 compatible = "rockchip,rk3399-i2c";
538                 reg = <0x0 0xff110000 0x0 0x1000>;
539                 assigned-clocks = <&cru SCLK_I2C1>;
540                 assigned-clock-rates = <200000000>;
541                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
542                 clock-names = "i2c", "pclk";
543                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
544                 pinctrl-names = "default";
545                 pinctrl-0 = <&i2c1_xfer>;
546                 #address-cells = <1>;
547                 #size-cells = <0>;
548                 status = "disabled";
549         };
550
551         i2c2: i2c@ff120000 {
552                 compatible = "rockchip,rk3399-i2c";
553                 reg = <0x0 0xff120000 0x0 0x1000>;
554                 assigned-clocks = <&cru SCLK_I2C2>;
555                 assigned-clock-rates = <200000000>;
556                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
557                 clock-names = "i2c", "pclk";
558                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
559                 pinctrl-names = "default";
560                 pinctrl-0 = <&i2c2_xfer>;
561                 #address-cells = <1>;
562                 #size-cells = <0>;
563                 status = "disabled";
564         };
565
566         i2c3: i2c@ff130000 {
567                 compatible = "rockchip,rk3399-i2c";
568                 reg = <0x0 0xff130000 0x0 0x1000>;
569                 assigned-clocks = <&cru SCLK_I2C3>;
570                 assigned-clock-rates = <200000000>;
571                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
572                 clock-names = "i2c", "pclk";
573                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
574                 pinctrl-names = "default";
575                 pinctrl-0 = <&i2c3_xfer>;
576                 #address-cells = <1>;
577                 #size-cells = <0>;
578                 status = "disabled";
579         };
580
581         i2c5: i2c@ff140000 {
582                 compatible = "rockchip,rk3399-i2c";
583                 reg = <0x0 0xff140000 0x0 0x1000>;
584                 assigned-clocks = <&cru SCLK_I2C5>;
585                 assigned-clock-rates = <200000000>;
586                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
587                 clock-names = "i2c", "pclk";
588                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
589                 pinctrl-names = "default";
590                 pinctrl-0 = <&i2c5_xfer>;
591                 #address-cells = <1>;
592                 #size-cells = <0>;
593                 status = "disabled";
594         };
595
596         i2c6: i2c@ff150000 {
597                 compatible = "rockchip,rk3399-i2c";
598                 reg = <0x0 0xff150000 0x0 0x1000>;
599                 assigned-clocks = <&cru SCLK_I2C6>;
600                 assigned-clock-rates = <200000000>;
601                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
602                 clock-names = "i2c", "pclk";
603                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
604                 pinctrl-names = "default";
605                 pinctrl-0 = <&i2c6_xfer>;
606                 #address-cells = <1>;
607                 #size-cells = <0>;
608                 status = "disabled";
609         };
610
611         i2c7: i2c@ff160000 {
612                 compatible = "rockchip,rk3399-i2c";
613                 reg = <0x0 0xff160000 0x0 0x1000>;
614                 assigned-clocks = <&cru SCLK_I2C7>;
615                 assigned-clock-rates = <200000000>;
616                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
617                 clock-names = "i2c", "pclk";
618                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
619                 pinctrl-names = "default";
620                 pinctrl-0 = <&i2c7_xfer>;
621                 #address-cells = <1>;
622                 #size-cells = <0>;
623                 status = "disabled";
624         };
625
626         uart0: serial@ff180000 {
627                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
628                 reg = <0x0 0xff180000 0x0 0x100>;
629                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
630                 clock-names = "baudclk", "apb_pclk";
631                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
632                 reg-shift = <2>;
633                 reg-io-width = <4>;
634                 pinctrl-names = "default";
635                 pinctrl-0 = <&uart0_xfer>;
636                 status = "disabled";
637         };
638
639         uart1: serial@ff190000 {
640                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641                 reg = <0x0 0xff190000 0x0 0x100>;
642                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
643                 clock-names = "baudclk", "apb_pclk";
644                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
645                 reg-shift = <2>;
646                 reg-io-width = <4>;
647                 pinctrl-names = "default";
648                 pinctrl-0 = <&uart1_xfer>;
649                 status = "disabled";
650         };
651
652         uart2: serial@ff1a0000 {
653                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654                 reg = <0x0 0xff1a0000 0x0 0x100>;
655                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
656                 clock-names = "baudclk", "apb_pclk";
657                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
658                 reg-shift = <2>;
659                 reg-io-width = <4>;
660                 pinctrl-names = "default";
661                 pinctrl-0 = <&uart2c_xfer>;
662                 status = "disabled";
663         };
664
665         uart3: serial@ff1b0000 {
666                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
667                 reg = <0x0 0xff1b0000 0x0 0x100>;
668                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
669                 clock-names = "baudclk", "apb_pclk";
670                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
671                 reg-shift = <2>;
672                 reg-io-width = <4>;
673                 pinctrl-names = "default";
674                 pinctrl-0 = <&uart3_xfer>;
675                 status = "disabled";
676         };
677
678         spi0: spi@ff1c0000 {
679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680                 reg = <0x0 0xff1c0000 0x0 0x1000>;
681                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
682                 clock-names = "spiclk", "apb_pclk";
683                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
684                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
685                 dma-names = "tx", "rx";
686                 pinctrl-names = "default";
687                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
688                 #address-cells = <1>;
689                 #size-cells = <0>;
690                 status = "disabled";
691         };
692
693         spi1: spi@ff1d0000 {
694                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
695                 reg = <0x0 0xff1d0000 0x0 0x1000>;
696                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
697                 clock-names = "spiclk", "apb_pclk";
698                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
699                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
700                 dma-names = "tx", "rx";
701                 pinctrl-names = "default";
702                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
703                 #address-cells = <1>;
704                 #size-cells = <0>;
705                 status = "disabled";
706         };
707
708         spi2: spi@ff1e0000 {
709                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
710                 reg = <0x0 0xff1e0000 0x0 0x1000>;
711                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
712                 clock-names = "spiclk", "apb_pclk";
713                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
714                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
715                 dma-names = "tx", "rx";
716                 pinctrl-names = "default";
717                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
718                 #address-cells = <1>;
719                 #size-cells = <0>;
720                 status = "disabled";
721         };
722
723         spi4: spi@ff1f0000 {
724                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
725                 reg = <0x0 0xff1f0000 0x0 0x1000>;
726                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
727                 clock-names = "spiclk", "apb_pclk";
728                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
729                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
730                 dma-names = "tx", "rx";
731                 pinctrl-names = "default";
732                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
733                 #address-cells = <1>;
734                 #size-cells = <0>;
735                 status = "disabled";
736         };
737
738         spi5: spi@ff200000 {
739                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
740                 reg = <0x0 0xff200000 0x0 0x1000>;
741                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
742                 clock-names = "spiclk", "apb_pclk";
743                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
744                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
745                 dma-names = "tx", "rx";
746                 pinctrl-names = "default";
747                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
748                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
749                 #address-cells = <1>;
750                 #size-cells = <0>;
751                 status = "disabled";
752         };
753
754         thermal_zones: thermal-zones {
755                 cpu_thermal: cpu {
756                         polling-delay-passive = <100>;
757                         polling-delay = <1000>;
758
759                         thermal-sensors = <&tsadc 0>;
760
761                         trips {
762                                 cpu_alert0: cpu_alert0 {
763                                         temperature = <70000>;
764                                         hysteresis = <2000>;
765                                         type = "passive";
766                                 };
767                                 cpu_alert1: cpu_alert1 {
768                                         temperature = <75000>;
769                                         hysteresis = <2000>;
770                                         type = "passive";
771                                 };
772                                 cpu_crit: cpu_crit {
773                                         temperature = <95000>;
774                                         hysteresis = <2000>;
775                                         type = "critical";
776                                 };
777                         };
778
779                         cooling-maps {
780                                 map0 {
781                                         trip = <&cpu_alert0>;
782                                         cooling-device =
783                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
784                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
785                                 };
786                                 map1 {
787                                         trip = <&cpu_alert1>;
788                                         cooling-device =
789                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
790                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
791                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
792                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
793                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
794                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
795                                 };
796                         };
797                 };
798
799                 gpu_thermal: gpu {
800                         polling-delay-passive = <100>;
801                         polling-delay = <1000>;
802
803                         thermal-sensors = <&tsadc 1>;
804
805                         trips {
806                                 gpu_alert0: gpu_alert0 {
807                                         temperature = <75000>;
808                                         hysteresis = <2000>;
809                                         type = "passive";
810                                 };
811                                 gpu_crit: gpu_crit {
812                                         temperature = <95000>;
813                                         hysteresis = <2000>;
814                                         type = "critical";
815                                 };
816                         };
817
818                         cooling-maps {
819                                 map0 {
820                                         trip = <&gpu_alert0>;
821                                         cooling-device =
822                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
823                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
824                                 };
825                         };
826                 };
827         };
828
829         tsadc: tsadc@ff260000 {
830                 compatible = "rockchip,rk3399-tsadc";
831                 reg = <0x0 0xff260000 0x0 0x100>;
832                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
833                 assigned-clocks = <&cru SCLK_TSADC>;
834                 assigned-clock-rates = <750000>;
835                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
836                 clock-names = "tsadc", "apb_pclk";
837                 resets = <&cru SRST_TSADC>;
838                 reset-names = "tsadc-apb";
839                 rockchip,grf = <&grf>;
840                 rockchip,hw-tshut-temp = <95000>;
841                 pinctrl-names = "init", "default", "sleep";
842                 pinctrl-0 = <&otp_gpio>;
843                 pinctrl-1 = <&otp_out>;
844                 pinctrl-2 = <&otp_gpio>;
845                 #thermal-sensor-cells = <1>;
846                 status = "disabled";
847         };
848
849         qos_emmc: qos@ffa58000 {
850                 compatible = "syscon";
851                 reg = <0x0 0xffa58000 0x0 0x20>;
852         };
853
854         qos_gmac: qos@ffa5c000 {
855                 compatible = "syscon";
856                 reg = <0x0 0xffa5c000 0x0 0x20>;
857         };
858
859         qos_pcie: qos@ffa60080 {
860                 compatible = "syscon";
861                 reg = <0x0 0xffa60080 0x0 0x20>;
862         };
863
864         qos_usb_host0: qos@ffa60100 {
865                 compatible = "syscon";
866                 reg = <0x0 0xffa60100 0x0 0x20>;
867         };
868
869         qos_usb_host1: qos@ffa60180 {
870                 compatible = "syscon";
871                 reg = <0x0 0xffa60180 0x0 0x20>;
872         };
873
874         qos_usb_otg0: qos@ffa70000 {
875                 compatible = "syscon";
876                 reg = <0x0 0xffa70000 0x0 0x20>;
877         };
878
879         qos_usb_otg1: qos@ffa70080 {
880                 compatible = "syscon";
881                 reg = <0x0 0xffa70080 0x0 0x20>;
882         };
883
884         qos_sd: qos@ffa74000 {
885                 compatible = "syscon";
886                 reg = <0x0 0xffa74000 0x0 0x20>;
887         };
888
889         qos_sdioaudio: qos@ffa76000 {
890                 compatible = "syscon";
891                 reg = <0x0 0xffa76000 0x0 0x20>;
892         };
893
894         qos_hdcp: qos@ffa90000 {
895                 compatible = "syscon";
896                 reg = <0x0 0xffa90000 0x0 0x20>;
897         };
898
899         qos_iep: qos@ffa98000 {
900                 compatible = "syscon";
901                 reg = <0x0 0xffa98000 0x0 0x20>;
902         };
903
904         qos_isp0_m0: qos@ffaa0000 {
905                 compatible = "syscon";
906                 reg = <0x0 0xffaa0000 0x0 0x20>;
907         };
908
909         qos_isp0_m1: qos@ffaa0080 {
910                 compatible = "syscon";
911                 reg = <0x0 0xffaa0080 0x0 0x20>;
912         };
913
914         qos_isp1_m0: qos@ffaa8000 {
915                 compatible = "syscon";
916                 reg = <0x0 0xffaa8000 0x0 0x20>;
917         };
918
919         qos_isp1_m1: qos@ffaa8080 {
920                 compatible = "syscon";
921                 reg = <0x0 0xffaa8080 0x0 0x20>;
922         };
923
924         qos_rga_r: qos@ffab0000 {
925                 compatible = "syscon";
926                 reg = <0x0 0xffab0000 0x0 0x20>;
927         };
928
929         qos_rga_w: qos@ffab0080 {
930                 compatible = "syscon";
931                 reg = <0x0 0xffab0080 0x0 0x20>;
932         };
933
934         qos_video_m0: qos@ffab8000 {
935                 compatible = "syscon";
936                 reg = <0x0 0xffab8000 0x0 0x20>;
937         };
938
939         qos_video_m1_r: qos@ffac0000 {
940                 compatible = "syscon";
941                 reg = <0x0 0xffac0000 0x0 0x20>;
942         };
943
944         qos_video_m1_w: qos@ffac0080 {
945                 compatible = "syscon";
946                 reg = <0x0 0xffac0080 0x0 0x20>;
947         };
948
949         qos_vop_big_r: qos@ffac8000 {
950                 compatible = "syscon";
951                 reg = <0x0 0xffac8000 0x0 0x20>;
952         };
953
954         qos_vop_big_w: qos@ffac8080 {
955                 compatible = "syscon";
956                 reg = <0x0 0xffac8080 0x0 0x20>;
957         };
958
959         qos_vop_little: qos@ffad0000 {
960                 compatible = "syscon";
961                 reg = <0x0 0xffad0000 0x0 0x20>;
962         };
963
964         qos_perihp: qos@ffad8080 {
965                 compatible = "syscon";
966                 reg = <0x0 0xffad8080 0x0 0x20>;
967         };
968
969         qos_gpu: qos@ffae0000 {
970                 compatible = "syscon";
971                 reg = <0x0 0xffae0000 0x0 0x20>;
972         };
973
974         pmu: power-management@ff310000 {
975                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
976                 reg = <0x0 0xff310000 0x0 0x1000>;
977
978                 /*
979                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
980                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
981                  * Some of the power domains are grouped together for every
982                  * voltage domain.
983                  * The detail contents as below.
984                  */
985                 power: power-controller {
986                         compatible = "rockchip,rk3399-power-controller";
987                         #power-domain-cells = <1>;
988                         #address-cells = <1>;
989                         #size-cells = <0>;
990
991                         /* These power domains are grouped by VD_CENTER */
992                         pd_iep@RK3399_PD_IEP {
993                                 reg = <RK3399_PD_IEP>;
994                                 clocks = <&cru ACLK_IEP>,
995                                          <&cru HCLK_IEP>;
996                                 pm_qos = <&qos_iep>;
997                         };
998                         pd_rga@RK3399_PD_RGA {
999                                 reg = <RK3399_PD_RGA>;
1000                                 clocks = <&cru ACLK_RGA>,
1001                                          <&cru HCLK_RGA>;
1002                                 pm_qos = <&qos_rga_r>,
1003                                          <&qos_rga_w>;
1004                         };
1005                         pd_vcodec@RK3399_PD_VCODEC {
1006                                 reg = <RK3399_PD_VCODEC>;
1007                                 clocks = <&cru ACLK_VCODEC>,
1008                                          <&cru HCLK_VCODEC>;
1009                                 pm_qos = <&qos_video_m0>;
1010                         };
1011                         pd_vdu@RK3399_PD_VDU {
1012                                 reg = <RK3399_PD_VDU>;
1013                                 clocks = <&cru ACLK_VDU>,
1014                                          <&cru HCLK_VDU>;
1015                                 pm_qos = <&qos_video_m1_r>,
1016                                          <&qos_video_m1_w>;
1017                         };
1018
1019                         /* These power domains are grouped by VD_GPU */
1020                         pd_gpu@RK3399_PD_GPU {
1021                                 reg = <RK3399_PD_GPU>;
1022                                 clocks = <&cru ACLK_GPU>;
1023                                 pm_qos = <&qos_gpu>;
1024                         };
1025
1026                         /* These power domains are grouped by VD_LOGIC */
1027                         pd_edp@RK3399_PD_EDP {
1028                                 reg = <RK3399_PD_EDP>;
1029                                 clocks = <&cru PCLK_EDP_CTRL>;
1030                         };
1031                         pd_emmc@RK3399_PD_EMMC {
1032                                 reg = <RK3399_PD_EMMC>;
1033                                 clocks = <&cru ACLK_EMMC>;
1034                                 pm_qos = <&qos_emmc>;
1035                         };
1036                         pd_gmac@RK3399_PD_GMAC {
1037                                 reg = <RK3399_PD_GMAC>;
1038                                 clocks = <&cru ACLK_GMAC>,
1039                                          <&cru PCLK_GMAC>;
1040                                 pm_qos = <&qos_gmac>;
1041                         };
1042                         pd_sd@RK3399_PD_SD {
1043                                 reg = <RK3399_PD_SD>;
1044                                 clocks = <&cru HCLK_SDMMC>,
1045                                          <&cru SCLK_SDMMC>;
1046                                 pm_qos = <&qos_sd>;
1047                         };
1048                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1049                                 reg = <RK3399_PD_SDIOAUDIO>;
1050                                 clocks = <&cru HCLK_SDIO>;
1051                                 pm_qos = <&qos_sdioaudio>;
1052                         };
1053                         pd_usb3@RK3399_PD_USB3 {
1054                                 reg = <RK3399_PD_USB3>;
1055                                 clocks = <&cru ACLK_USB3>;
1056                                 pm_qos = <&qos_usb_otg0>,
1057                                          <&qos_usb_otg1>;
1058                         };
1059                         pd_vio@RK3399_PD_VIO {
1060                                 reg = <RK3399_PD_VIO>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063
1064                                 pd_hdcp@RK3399_PD_HDCP {
1065                                         reg = <RK3399_PD_HDCP>;
1066                                         clocks = <&cru ACLK_HDCP>,
1067                                                  <&cru HCLK_HDCP>,
1068                                                  <&cru PCLK_HDCP>;
1069                                         pm_qos = <&qos_hdcp>;
1070                                 };
1071                                 pd_isp0@RK3399_PD_ISP0 {
1072                                         reg = <RK3399_PD_ISP0>;
1073                                         clocks = <&cru ACLK_ISP0>,
1074                                                  <&cru HCLK_ISP0>;
1075                                         pm_qos = <&qos_isp0_m0>,
1076                                                  <&qos_isp0_m1>;
1077                                 };
1078                                 pd_isp1@RK3399_PD_ISP1 {
1079                                         reg = <RK3399_PD_ISP1>;
1080                                         clocks = <&cru ACLK_ISP1>,
1081                                                  <&cru HCLK_ISP1>;
1082                                         pm_qos = <&qos_isp1_m0>,
1083                                                  <&qos_isp1_m1>;
1084                                 };
1085                                 pd_tcpc0@RK3399_PD_TCPC0 {
1086                                         reg = <RK3399_PD_TCPD0>;
1087                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1088                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1089                                 };
1090                                 pd_tcpc1@RK3399_PD_TCPC1 {
1091                                         reg = <RK3399_PD_TCPD1>;
1092                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1093                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1094                                 };
1095                                 pd_vo@RK3399_PD_VO {
1096                                         reg = <RK3399_PD_VO>;
1097                                         #address-cells = <1>;
1098                                         #size-cells = <0>;
1099
1100                                         pd_vopb@RK3399_PD_VOPB {
1101                                                 reg = <RK3399_PD_VOPB>;
1102                                                 clocks = <&cru ACLK_VOP0>,
1103                                                          <&cru HCLK_VOP0>;
1104                                                 pm_qos = <&qos_vop_big_r>,
1105                                                          <&qos_vop_big_w>;
1106                                         };
1107                                         pd_vopl@RK3399_PD_VOPL {
1108                                                 reg = <RK3399_PD_VOPL>;
1109                                                 clocks = <&cru ACLK_VOP1>,
1110                                                          <&cru HCLK_VOP1>;
1111                                                 pm_qos = <&qos_vop_little>;
1112                                         };
1113                                 };
1114                         };
1115                 };
1116         };
1117
1118         pmugrf: syscon@ff320000 {
1119                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1120                 reg = <0x0 0xff320000 0x0 0x1000>;
1121                 #address-cells = <1>;
1122                 #size-cells = <1>;
1123
1124                 pmu_io_domains: io-domains {
1125                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1126                         status = "disabled";
1127                 };
1128         };
1129
1130         spi3: spi@ff350000 {
1131                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1132                 reg = <0x0 0xff350000 0x0 0x1000>;
1133                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1134                 clock-names = "spiclk", "apb_pclk";
1135                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1136                 pinctrl-names = "default";
1137                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1138                 #address-cells = <1>;
1139                 #size-cells = <0>;
1140                 status = "disabled";
1141         };
1142
1143         uart4: serial@ff370000 {
1144                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1145                 reg = <0x0 0xff370000 0x0 0x100>;
1146                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1147                 clock-names = "baudclk", "apb_pclk";
1148                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1149                 reg-shift = <2>;
1150                 reg-io-width = <4>;
1151                 pinctrl-names = "default";
1152                 pinctrl-0 = <&uart4_xfer>;
1153                 status = "disabled";
1154         };
1155
1156         i2c0: i2c@ff3c0000 {
1157                 compatible = "rockchip,rk3399-i2c";
1158                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1159                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1160                 assigned-clock-rates = <200000000>;
1161                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1162                 clock-names = "i2c", "pclk";
1163                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1164                 pinctrl-names = "default";
1165                 pinctrl-0 = <&i2c0_xfer>;
1166                 #address-cells = <1>;
1167                 #size-cells = <0>;
1168                 status = "disabled";
1169         };
1170
1171         i2c4: i2c@ff3d0000 {
1172                 compatible = "rockchip,rk3399-i2c";
1173                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1174                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1175                 assigned-clock-rates = <200000000>;
1176                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1177                 clock-names = "i2c", "pclk";
1178                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1179                 pinctrl-names = "default";
1180                 pinctrl-0 = <&i2c4_xfer>;
1181                 #address-cells = <1>;
1182                 #size-cells = <0>;
1183                 status = "disabled";
1184         };
1185
1186         i2c8: i2c@ff3e0000 {
1187                 compatible = "rockchip,rk3399-i2c";
1188                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1189                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1190                 assigned-clock-rates = <200000000>;
1191                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1192                 clock-names = "i2c", "pclk";
1193                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1194                 pinctrl-names = "default";
1195                 pinctrl-0 = <&i2c8_xfer>;
1196                 #address-cells = <1>;
1197                 #size-cells = <0>;
1198                 status = "disabled";
1199         };
1200
1201         pwm0: pwm@ff420000 {
1202                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1203                 reg = <0x0 0xff420000 0x0 0x10>;
1204                 #pwm-cells = <3>;
1205                 pinctrl-names = "default";
1206                 pinctrl-0 = <&pwm0_pin>;
1207                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1208                 clock-names = "pwm";
1209                 status = "disabled";
1210         };
1211
1212         pwm1: pwm@ff420010 {
1213                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1214                 reg = <0x0 0xff420010 0x0 0x10>;
1215                 #pwm-cells = <3>;
1216                 pinctrl-names = "default";
1217                 pinctrl-0 = <&pwm1_pin>;
1218                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1219                 clock-names = "pwm";
1220                 status = "disabled";
1221         };
1222
1223         pwm2: pwm@ff420020 {
1224                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1225                 reg = <0x0 0xff420020 0x0 0x10>;
1226                 #pwm-cells = <3>;
1227                 pinctrl-names = "default";
1228                 pinctrl-0 = <&pwm2_pin>;
1229                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1230                 clock-names = "pwm";
1231                 status = "disabled";
1232         };
1233
1234         pwm3: pwm@ff420030 {
1235                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1236                 reg = <0x0 0xff420030 0x0 0x10>;
1237                 #pwm-cells = <3>;
1238                 pinctrl-names = "default";
1239                 pinctrl-0 = <&pwm3a_pin>;
1240                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1241                 clock-names = "pwm";
1242                 status = "disabled";
1243         };
1244
1245         vpu_mmu: iommu@ff650800 {
1246                 compatible = "rockchip,iommu";
1247                 reg = <0x0 0xff650800 0x0 0x40>;
1248                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1249                 interrupt-names = "vpu_mmu";
1250                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1251                 clock-names = "aclk", "iface";
1252                 #iommu-cells = <0>;
1253                 status = "disabled";
1254         };
1255
1256         vdec_mmu: iommu@ff660480 {
1257                 compatible = "rockchip,iommu";
1258                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1259                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1260                 interrupt-names = "vdec_mmu";
1261                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1262                 clock-names = "aclk", "iface";
1263                 #iommu-cells = <0>;
1264                 status = "disabled";
1265         };
1266
1267         iep_mmu: iommu@ff670800 {
1268                 compatible = "rockchip,iommu";
1269                 reg = <0x0 0xff670800 0x0 0x40>;
1270                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1271                 interrupt-names = "iep_mmu";
1272                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1273                 clock-names = "aclk", "iface";
1274                 #iommu-cells = <0>;
1275                 status = "disabled";
1276         };
1277
1278         rga: rga@ff680000 {
1279                 compatible = "rockchip,rk3399-rga";
1280                 reg = <0x0 0xff680000 0x0 0x10000>;
1281                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1282                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1283                 clock-names = "aclk", "hclk", "sclk";
1284                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1285                 reset-names = "core", "axi", "ahb";
1286                 power-domains = <&power RK3399_PD_RGA>;
1287         };
1288
1289         efuse0: efuse@ff690000 {
1290                 compatible = "rockchip,rk3399-efuse";
1291                 reg = <0x0 0xff690000 0x0 0x80>;
1292                 #address-cells = <1>;
1293                 #size-cells = <1>;
1294                 clocks = <&cru PCLK_EFUSE1024NS>;
1295                 clock-names = "pclk_efuse";
1296
1297                 /* Data cells */
1298                 cpu_id: cpu-id@7 {
1299                         reg = <0x07 0x10>;
1300                 };
1301                 cpub_leakage: cpu-leakage@17 {
1302                         reg = <0x17 0x1>;
1303                 };
1304                 gpu_leakage: gpu-leakage@18 {
1305                         reg = <0x18 0x1>;
1306                 };
1307                 center_leakage: center-leakage@19 {
1308                         reg = <0x19 0x1>;
1309                 };
1310                 cpul_leakage: cpu-leakage@1a {
1311                         reg = <0x1a 0x1>;
1312                 };
1313                 logic_leakage: logic-leakage@1b {
1314                         reg = <0x1b 0x1>;
1315                 };
1316                 wafer_info: wafer-info@1c {
1317                         reg = <0x1c 0x1>;
1318                 };
1319         };
1320
1321         pmucru: pmu-clock-controller@ff750000 {
1322                 compatible = "rockchip,rk3399-pmucru";
1323                 reg = <0x0 0xff750000 0x0 0x1000>;
1324                 rockchip,grf = <&pmugrf>;
1325                 #clock-cells = <1>;
1326                 #reset-cells = <1>;
1327                 assigned-clocks = <&pmucru PLL_PPLL>;
1328                 assigned-clock-rates = <676000000>;
1329         };
1330
1331         cru: clock-controller@ff760000 {
1332                 compatible = "rockchip,rk3399-cru";
1333                 reg = <0x0 0xff760000 0x0 0x1000>;
1334                 rockchip,grf = <&grf>;
1335                 #clock-cells = <1>;
1336                 #reset-cells = <1>;
1337                 assigned-clocks =
1338                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1339                         <&cru PLL_NPLL>,
1340                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1341                         <&cru PCLK_PERIHP>,
1342                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1343                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1344                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1345                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1346                         <&cru ACLK_GIC_PRE>,
1347                         <&cru PCLK_DDR>;
1348                 assigned-clock-rates =
1349                          <594000000>,  <800000000>,
1350                         <1000000000>,
1351                          <150000000>,   <75000000>,
1352                           <37500000>,
1353                          <100000000>,  <100000000>,
1354                           <50000000>, <600000000>,
1355                          <100000000>,   <50000000>,
1356                          <400000000>, <400000000>,
1357                          <200000000>,
1358                          <200000000>;
1359         };
1360
1361         grf: syscon@ff770000 {
1362                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1363                 reg = <0x0 0xff770000 0x0 0x10000>;
1364                 #address-cells = <1>;
1365                 #size-cells = <1>;
1366
1367                 io_domains: io-domains {
1368                         compatible = "rockchip,rk3399-io-voltage-domain";
1369                         status = "disabled";
1370                 };
1371
1372                 u2phy0: usb2-phy@e450 {
1373                         compatible = "rockchip,rk3399-usb2phy";
1374                         reg = <0xe450 0x10>;
1375                         clocks = <&cru SCLK_USB2PHY0_REF>;
1376                         clock-names = "phyclk";
1377                         #clock-cells = <0>;
1378                         clock-output-names = "clk_usbphy0_480m";
1379                         status = "disabled";
1380
1381                         u2phy0_host: host-port {
1382                                 #phy-cells = <0>;
1383                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1384                                 interrupt-names = "linestate";
1385                                 status = "disabled";
1386                         };
1387
1388                         u2phy0_otg: otg-port {
1389                                 #phy-cells = <0>;
1390                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1391                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1392                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1393                                 interrupt-names = "otg-bvalid", "otg-id",
1394                                                   "linestate";
1395                                 status = "disabled";
1396                         };
1397                 };
1398
1399                 u2phy1: usb2-phy@e460 {
1400                         compatible = "rockchip,rk3399-usb2phy";
1401                         reg = <0xe460 0x10>;
1402                         clocks = <&cru SCLK_USB2PHY1_REF>;
1403                         clock-names = "phyclk";
1404                         #clock-cells = <0>;
1405                         clock-output-names = "clk_usbphy1_480m";
1406                         status = "disabled";
1407
1408                         u2phy1_host: host-port {
1409                                 #phy-cells = <0>;
1410                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1411                                 interrupt-names = "linestate";
1412                                 status = "disabled";
1413                         };
1414
1415                         u2phy1_otg: otg-port {
1416                                 #phy-cells = <0>;
1417                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1418                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1419                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1420                                 interrupt-names = "otg-bvalid", "otg-id",
1421                                                   "linestate";
1422                                 status = "disabled";
1423                         };
1424                 };
1425
1426                 emmc_phy: phy@f780 {
1427                         compatible = "rockchip,rk3399-emmc-phy";
1428                         reg = <0xf780 0x24>;
1429                         clocks = <&sdhci>;
1430                         clock-names = "emmcclk";
1431                         #phy-cells = <0>;
1432                         status = "disabled";
1433                 };
1434
1435                 pcie_phy: pcie-phy {
1436                         compatible = "rockchip,rk3399-pcie-phy";
1437                         clocks = <&cru SCLK_PCIEPHY_REF>;
1438                         clock-names = "refclk";
1439                         #phy-cells = <1>;
1440                         resets = <&cru SRST_PCIEPHY>;
1441                         reset-names = "phy";
1442                         status = "disabled";
1443                 };
1444         };
1445
1446         tcphy0: phy@ff7c0000 {
1447                 compatible = "rockchip,rk3399-typec-phy";
1448                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1449                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1450                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1451                 clock-names = "tcpdcore", "tcpdphy-ref";
1452                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1453                 assigned-clock-rates = <50000000>;
1454                 power-domains = <&power RK3399_PD_TCPD0>;
1455                 resets = <&cru SRST_UPHY0>,
1456                          <&cru SRST_UPHY0_PIPE_L00>,
1457                          <&cru SRST_P_UPHY0_TCPHY>;
1458                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1459                 rockchip,grf = <&grf>;
1460                 status = "disabled";
1461
1462                 tcphy0_dp: dp-port {
1463                         #phy-cells = <0>;
1464                 };
1465
1466                 tcphy0_usb3: usb3-port {
1467                         #phy-cells = <0>;
1468                 };
1469         };
1470
1471         tcphy1: phy@ff800000 {
1472                 compatible = "rockchip,rk3399-typec-phy";
1473                 reg = <0x0 0xff800000 0x0 0x40000>;
1474                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1475                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1476                 clock-names = "tcpdcore", "tcpdphy-ref";
1477                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1478                 assigned-clock-rates = <50000000>;
1479                 power-domains = <&power RK3399_PD_TCPD1>;
1480                 resets = <&cru SRST_UPHY1>,
1481                          <&cru SRST_UPHY1_PIPE_L00>,
1482                          <&cru SRST_P_UPHY1_TCPHY>;
1483                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1484                 rockchip,grf = <&grf>;
1485                 status = "disabled";
1486
1487                 tcphy1_dp: dp-port {
1488                         #phy-cells = <0>;
1489                 };
1490
1491                 tcphy1_usb3: usb3-port {
1492                         #phy-cells = <0>;
1493                 };
1494         };
1495
1496         watchdog@ff848000 {
1497                 compatible = "snps,dw-wdt";
1498                 reg = <0x0 0xff848000 0x0 0x100>;
1499                 clocks = <&cru PCLK_WDT>;
1500                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1501         };
1502
1503         rktimer: rktimer@ff850000 {
1504                 compatible = "rockchip,rk3399-timer";
1505                 reg = <0x0 0xff850000 0x0 0x1000>;
1506                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1507                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1508                 clock-names = "pclk", "timer";
1509         };
1510
1511         spdif: spdif@ff870000 {
1512                 compatible = "rockchip,rk3399-spdif";
1513                 reg = <0x0 0xff870000 0x0 0x1000>;
1514                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1515                 dmas = <&dmac_bus 7>;
1516                 dma-names = "tx";
1517                 clock-names = "mclk", "hclk";
1518                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1519                 pinctrl-names = "default";
1520                 pinctrl-0 = <&spdif_bus>;
1521                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1522                 #sound-dai-cells = <0>;
1523                 status = "disabled";
1524         };
1525
1526         i2s0: i2s@ff880000 {
1527                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1528                 reg = <0x0 0xff880000 0x0 0x1000>;
1529                 rockchip,grf = <&grf>;
1530                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1531                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1532                 dma-names = "tx", "rx";
1533                 clock-names = "i2s_clk", "i2s_hclk";
1534                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1535                 pinctrl-names = "default";
1536                 pinctrl-0 = <&i2s0_8ch_bus>;
1537                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1538                 #sound-dai-cells = <0>;
1539                 status = "disabled";
1540         };
1541
1542         i2s1: i2s@ff890000 {
1543                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1544                 reg = <0x0 0xff890000 0x0 0x1000>;
1545                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1546                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1547                 dma-names = "tx", "rx";
1548                 clock-names = "i2s_clk", "i2s_hclk";
1549                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1550                 pinctrl-names = "default";
1551                 pinctrl-0 = <&i2s1_2ch_bus>;
1552                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1553                 #sound-dai-cells = <0>;
1554                 status = "disabled";
1555         };
1556
1557         i2s2: i2s@ff8a0000 {
1558                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1559                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1560                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1561                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1562                 dma-names = "tx", "rx";
1563                 clock-names = "i2s_clk", "i2s_hclk";
1564                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1565                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1566                 #sound-dai-cells = <0>;
1567                 status = "disabled";
1568         };
1569
1570         vopl: vop@ff8f0000 {
1571                 compatible = "rockchip,rk3399-vop-lit";
1572                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1573                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1574                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1575                 assigned-clock-rates = <400000000>, <100000000>;
1576                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1577                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1578                 iommus = <&vopl_mmu>;
1579                 power-domains = <&power RK3399_PD_VOPL>;
1580                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1581                 reset-names = "axi", "ahb", "dclk";
1582                 status = "disabled";
1583
1584                 vopl_out: port {
1585                         #address-cells = <1>;
1586                         #size-cells = <0>;
1587
1588                         vopl_out_mipi: endpoint@0 {
1589                                 reg = <0>;
1590                                 remote-endpoint = <&mipi_in_vopl>;
1591                         };
1592
1593                         vopl_out_edp: endpoint@1 {
1594                                 reg = <1>;
1595                                 remote-endpoint = <&edp_in_vopl>;
1596                         };
1597
1598                         vopl_out_hdmi: endpoint@2 {
1599                                 reg = <2>;
1600                                 remote-endpoint = <&hdmi_in_vopl>;
1601                         };
1602
1603                         vopl_out_mipi1: endpoint@3 {
1604                                 reg = <3>;
1605                                 remote-endpoint = <&mipi1_in_vopl>;
1606                         };
1607
1608                         vopl_out_dp: endpoint@4 {
1609                                 reg = <4>;
1610                                 remote-endpoint = <&dp_in_vopl>;
1611                         };
1612                 };
1613         };
1614
1615         vopl_mmu: iommu@ff8f3f00 {
1616                 compatible = "rockchip,iommu";
1617                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1618                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1619                 interrupt-names = "vopl_mmu";
1620                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1621                 clock-names = "aclk", "iface";
1622                 power-domains = <&power RK3399_PD_VOPL>;
1623                 #iommu-cells = <0>;
1624                 status = "disabled";
1625         };
1626
1627         vopb: vop@ff900000 {
1628                 compatible = "rockchip,rk3399-vop-big";
1629                 reg = <0x0 0xff900000 0x0 0x3efc>;
1630                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1631                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1632                 assigned-clock-rates = <400000000>, <100000000>;
1633                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1634                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1635                 iommus = <&vopb_mmu>;
1636                 power-domains = <&power RK3399_PD_VOPB>;
1637                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1638                 reset-names = "axi", "ahb", "dclk";
1639                 status = "disabled";
1640
1641                 vopb_out: port {
1642                         #address-cells = <1>;
1643                         #size-cells = <0>;
1644
1645                         vopb_out_edp: endpoint@0 {
1646                                 reg = <0>;
1647                                 remote-endpoint = <&edp_in_vopb>;
1648                         };
1649
1650                         vopb_out_mipi: endpoint@1 {
1651                                 reg = <1>;
1652                                 remote-endpoint = <&mipi_in_vopb>;
1653                         };
1654
1655                         vopb_out_hdmi: endpoint@2 {
1656                                 reg = <2>;
1657                                 remote-endpoint = <&hdmi_in_vopb>;
1658                         };
1659
1660                         vopb_out_mipi1: endpoint@3 {
1661                                 reg = <3>;
1662                                 remote-endpoint = <&mipi1_in_vopb>;
1663                         };
1664
1665                         vopb_out_dp: endpoint@4 {
1666                                 reg = <4>;
1667                                 remote-endpoint = <&dp_in_vopb>;
1668                         };
1669                 };
1670         };
1671
1672         vopb_mmu: iommu@ff903f00 {
1673                 compatible = "rockchip,iommu";
1674                 reg = <0x0 0xff903f00 0x0 0x100>;
1675                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1676                 interrupt-names = "vopb_mmu";
1677                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1678                 clock-names = "aclk", "iface";
1679                 power-domains = <&power RK3399_PD_VOPB>;
1680                 #iommu-cells = <0>;
1681                 status = "disabled";
1682         };
1683
1684         isp0_mmu: iommu@ff914000 {
1685                 compatible = "rockchip,iommu";
1686                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1687                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1688                 interrupt-names = "isp0_mmu";
1689                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1690                 clock-names = "aclk", "iface";
1691                 #iommu-cells = <0>;
1692                 rockchip,disable-mmu-reset;
1693                 status = "disabled";
1694         };
1695
1696         isp1_mmu: iommu@ff924000 {
1697                 compatible = "rockchip,iommu";
1698                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1699                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1700                 interrupt-names = "isp1_mmu";
1701                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1702                 clock-names = "aclk", "iface";
1703                 #iommu-cells = <0>;
1704                 rockchip,disable-mmu-reset;
1705                 status = "disabled";
1706         };
1707
1708         hdmi_sound: hdmi-sound {
1709                 compatible = "simple-audio-card";
1710                 simple-audio-card,format = "i2s";
1711                 simple-audio-card,mclk-fs = <256>;
1712                 simple-audio-card,name = "hdmi-sound";
1713                 status = "disabled";
1714
1715                 simple-audio-card,cpu {
1716                         sound-dai = <&i2s2>;
1717                 };
1718                 simple-audio-card,codec {
1719                         sound-dai = <&hdmi>;
1720                 };
1721         };
1722
1723         hdmi: hdmi@ff940000 {
1724                 compatible = "rockchip,rk3399-dw-hdmi";
1725                 reg = <0x0 0xff940000 0x0 0x20000>;
1726                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1727                 clocks = <&cru PCLK_HDMI_CTRL>,
1728                          <&cru SCLK_HDMI_SFR>,
1729                          <&cru PLL_VPLL>,
1730                          <&cru PCLK_VIO_GRF>,
1731                          <&cru SCLK_HDMI_CEC>;
1732                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1733                 power-domains = <&power RK3399_PD_HDCP>;
1734                 reg-io-width = <4>;
1735                 rockchip,grf = <&grf>;
1736                 #sound-dai-cells = <0>;
1737                 status = "disabled";
1738
1739                 ports {
1740                         hdmi_in: port {
1741                                 #address-cells = <1>;
1742                                 #size-cells = <0>;
1743
1744                                 hdmi_in_vopb: endpoint@0 {
1745                                         reg = <0>;
1746                                         remote-endpoint = <&vopb_out_hdmi>;
1747                                 };
1748                                 hdmi_in_vopl: endpoint@1 {
1749                                         reg = <1>;
1750                                         remote-endpoint = <&vopl_out_hdmi>;
1751                                 };
1752                         };
1753                 };
1754         };
1755
1756         mipi_dsi: mipi@ff960000 {
1757                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1758                 reg = <0x0 0xff960000 0x0 0x8000>;
1759                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1760                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1761                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1762                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1763                 power-domains = <&power RK3399_PD_VIO>;
1764                 resets = <&cru SRST_P_MIPI_DSI0>;
1765                 reset-names = "apb";
1766                 rockchip,grf = <&grf>;
1767                 #address-cells = <1>;
1768                 #size-cells = <0>;
1769                 status = "disabled";
1770
1771                 ports {
1772                         #address-cells = <1>;
1773                         #size-cells = <0>;
1774
1775                         mipi_in: port@0 {
1776                                 reg = <0>;
1777                                 #address-cells = <1>;
1778                                 #size-cells = <0>;
1779
1780                                 mipi_in_vopb: endpoint@0 {
1781                                         reg = <0>;
1782                                         remote-endpoint = <&vopb_out_mipi>;
1783                                 };
1784                                 mipi_in_vopl: endpoint@1 {
1785                                         reg = <1>;
1786                                         remote-endpoint = <&vopl_out_mipi>;
1787                                 };
1788                         };
1789                 };
1790         };
1791
1792         mipi_dsi1: mipi@ff968000 {
1793                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1794                 reg = <0x0 0xff968000 0x0 0x8000>;
1795                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1796                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1797                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1798                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1799                 power-domains = <&power RK3399_PD_VIO>;
1800                 resets = <&cru SRST_P_MIPI_DSI1>;
1801                 reset-names = "apb";
1802                 rockchip,grf = <&grf>;
1803                 #address-cells = <1>;
1804                 #size-cells = <0>;
1805                 status = "disabled";
1806
1807                 ports {
1808                         #address-cells = <1>;
1809                         #size-cells = <0>;
1810
1811                         mipi1_in: port@0 {
1812                                 reg = <0>;
1813                                 #address-cells = <1>;
1814                                 #size-cells = <0>;
1815
1816                                 mipi1_in_vopb: endpoint@0 {
1817                                         reg = <0>;
1818                                         remote-endpoint = <&vopb_out_mipi1>;
1819                                 };
1820
1821                                 mipi1_in_vopl: endpoint@1 {
1822                                         reg = <1>;
1823                                         remote-endpoint = <&vopl_out_mipi1>;
1824                                 };
1825                         };
1826                 };
1827         };
1828
1829         edp: edp@ff970000 {
1830                 compatible = "rockchip,rk3399-edp";
1831                 reg = <0x0 0xff970000 0x0 0x8000>;
1832                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1833                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1834                 clock-names = "dp", "pclk", "grf";
1835                 pinctrl-names = "default";
1836                 pinctrl-0 = <&edp_hpd>;
1837                 power-domains = <&power RK3399_PD_EDP>;
1838                 resets = <&cru SRST_P_EDP_CTRL>;
1839                 reset-names = "dp";
1840                 rockchip,grf = <&grf>;
1841                 status = "disabled";
1842
1843                 ports {
1844                         #address-cells = <1>;
1845                         #size-cells = <0>;
1846                         edp_in: port@0 {
1847                                 reg = <0>;
1848                                 #address-cells = <1>;
1849                                 #size-cells = <0>;
1850
1851                                 edp_in_vopb: endpoint@0 {
1852                                         reg = <0>;
1853                                         remote-endpoint = <&vopb_out_edp>;
1854                                 };
1855
1856                                 edp_in_vopl: endpoint@1 {
1857                                         reg = <1>;
1858                                         remote-endpoint = <&vopl_out_edp>;
1859                                 };
1860                         };
1861                 };
1862         };
1863
1864         gpu: gpu@ff9a0000 {
1865                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1866                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1867                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1868                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1869                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1870                 interrupt-names = "gpu", "job", "mmu";
1871                 clocks = <&cru ACLK_GPU>;
1872                 power-domains = <&power RK3399_PD_GPU>;
1873                 status = "disabled";
1874         };
1875
1876         pinctrl: pinctrl {
1877                 compatible = "rockchip,rk3399-pinctrl";
1878                 rockchip,grf = <&grf>;
1879                 rockchip,pmu = <&pmugrf>;
1880                 #address-cells = <2>;
1881                 #size-cells = <2>;
1882                 ranges;
1883
1884                 gpio0: gpio0@ff720000 {
1885                         compatible = "rockchip,gpio-bank";
1886                         reg = <0x0 0xff720000 0x0 0x100>;
1887                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1888                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1889
1890                         gpio-controller;
1891                         #gpio-cells = <0x2>;
1892
1893                         interrupt-controller;
1894                         #interrupt-cells = <0x2>;
1895                 };
1896
1897                 gpio1: gpio1@ff730000 {
1898                         compatible = "rockchip,gpio-bank";
1899                         reg = <0x0 0xff730000 0x0 0x100>;
1900                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1901                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1902
1903                         gpio-controller;
1904                         #gpio-cells = <0x2>;
1905
1906                         interrupt-controller;
1907                         #interrupt-cells = <0x2>;
1908                 };
1909
1910                 gpio2: gpio2@ff780000 {
1911                         compatible = "rockchip,gpio-bank";
1912                         reg = <0x0 0xff780000 0x0 0x100>;
1913                         clocks = <&cru PCLK_GPIO2>;
1914                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1915
1916                         gpio-controller;
1917                         #gpio-cells = <0x2>;
1918
1919                         interrupt-controller;
1920                         #interrupt-cells = <0x2>;
1921                 };
1922
1923                 gpio3: gpio3@ff788000 {
1924                         compatible = "rockchip,gpio-bank";
1925                         reg = <0x0 0xff788000 0x0 0x100>;
1926                         clocks = <&cru PCLK_GPIO3>;
1927                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1928
1929                         gpio-controller;
1930                         #gpio-cells = <0x2>;
1931
1932                         interrupt-controller;
1933                         #interrupt-cells = <0x2>;
1934                 };
1935
1936                 gpio4: gpio4@ff790000 {
1937                         compatible = "rockchip,gpio-bank";
1938                         reg = <0x0 0xff790000 0x0 0x100>;
1939                         clocks = <&cru PCLK_GPIO4>;
1940                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1941
1942                         gpio-controller;
1943                         #gpio-cells = <0x2>;
1944
1945                         interrupt-controller;
1946                         #interrupt-cells = <0x2>;
1947                 };
1948
1949                 pcfg_pull_up: pcfg-pull-up {
1950                         bias-pull-up;
1951                 };
1952
1953                 pcfg_pull_down: pcfg-pull-down {
1954                         bias-pull-down;
1955                 };
1956
1957                 pcfg_pull_none: pcfg-pull-none {
1958                         bias-disable;
1959                 };
1960
1961                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1962                         bias-disable;
1963                         drive-strength = <12>;
1964                 };
1965
1966                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1967                         bias-disable;
1968                         drive-strength = <13>;
1969                 };
1970
1971                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1972                         bias-disable;
1973                         drive-strength = <18>;
1974                 };
1975
1976                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1977                         bias-disable;
1978                         drive-strength = <20>;
1979                 };
1980
1981                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1982                         bias-pull-up;
1983                         drive-strength = <2>;
1984                 };
1985
1986                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1987                         bias-pull-up;
1988                         drive-strength = <8>;
1989                 };
1990
1991                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1992                         bias-pull-up;
1993                         drive-strength = <18>;
1994                 };
1995
1996                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1997                         bias-pull-up;
1998                         drive-strength = <20>;
1999                 };
2000
2001                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2002                         bias-pull-down;
2003                         drive-strength = <4>;
2004                 };
2005
2006                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2007                         bias-pull-down;
2008                         drive-strength = <8>;
2009                 };
2010
2011                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2012                         bias-pull-down;
2013                         drive-strength = <12>;
2014                 };
2015
2016                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2017                         bias-pull-down;
2018                         drive-strength = <18>;
2019                 };
2020
2021                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2022                         bias-pull-down;
2023                         drive-strength = <20>;
2024                 };
2025
2026                 pcfg_output_high: pcfg-output-high {
2027                         output-high;
2028                 };
2029
2030                 pcfg_output_low: pcfg-output-low {
2031                         output-low;
2032                 };
2033
2034                 clock {
2035                         clk_32k: clk-32k {
2036                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
2037                         };
2038                 };
2039
2040                 edp {
2041                         edp_hpd: edp-hpd {
2042                                 rockchip,pins =
2043                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2044                         };
2045                 };
2046
2047                 gmac {
2048                         rgmii_pins: rgmii-pins {
2049                                 rockchip,pins =
2050                                         /* mac_txclk */
2051                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2052                                         /* mac_rxclk */
2053                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2054                                         /* mac_mdio */
2055                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2056                                         /* mac_txen */
2057                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2058                                         /* mac_clk */
2059                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2060                                         /* mac_rxdv */
2061                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2062                                         /* mac_mdc */
2063                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2064                                         /* mac_rxd1 */
2065                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2066                                         /* mac_rxd0 */
2067                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2068                                         /* mac_txd1 */
2069                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2070                                         /* mac_txd0 */
2071                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2072                                         /* mac_rxd3 */
2073                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2074                                         /* mac_rxd2 */
2075                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2076                                         /* mac_txd3 */
2077                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2078                                         /* mac_txd2 */
2079                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2080                         };
2081
2082                         rmii_pins: rmii-pins {
2083                                 rockchip,pins =
2084                                         /* mac_mdio */
2085                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2086                                         /* mac_txen */
2087                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2088                                         /* mac_clk */
2089                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2090                                         /* mac_rxer */
2091                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2092                                         /* mac_rxdv */
2093                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2094                                         /* mac_mdc */
2095                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2096                                         /* mac_rxd1 */
2097                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2098                                         /* mac_rxd0 */
2099                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2100                                         /* mac_txd1 */
2101                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2102                                         /* mac_txd0 */
2103                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2104                         };
2105                 };
2106
2107                 i2c0 {
2108                         i2c0_xfer: i2c0-xfer {
2109                                 rockchip,pins =
2110                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2111                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2112                         };
2113                 };
2114
2115                 i2c1 {
2116                         i2c1_xfer: i2c1-xfer {
2117                                 rockchip,pins =
2118                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2119                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2120                         };
2121                 };
2122
2123                 i2c2 {
2124                         i2c2_xfer: i2c2-xfer {
2125                                 rockchip,pins =
2126                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2127                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2128                         };
2129                 };
2130
2131                 i2c3 {
2132                         i2c3_xfer: i2c3-xfer {
2133                                 rockchip,pins =
2134                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2135                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2136                         };
2137                 };
2138
2139                 i2c4 {
2140                         i2c4_xfer: i2c4-xfer {
2141                                 rockchip,pins =
2142                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2143                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2144                         };
2145                 };
2146
2147                 i2c5 {
2148                         i2c5_xfer: i2c5-xfer {
2149                                 rockchip,pins =
2150                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2151                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2152                         };
2153                 };
2154
2155                 i2c6 {
2156                         i2c6_xfer: i2c6-xfer {
2157                                 rockchip,pins =
2158                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2159                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2160                         };
2161                 };
2162
2163                 i2c7 {
2164                         i2c7_xfer: i2c7-xfer {
2165                                 rockchip,pins =
2166                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2167                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2168                         };
2169                 };
2170
2171                 i2c8 {
2172                         i2c8_xfer: i2c8-xfer {
2173                                 rockchip,pins =
2174                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2175                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2176                         };
2177                 };
2178
2179                 i2s0 {
2180                         i2s0_2ch_bus: i2s0-2ch-bus {
2181                                 rockchip,pins =
2182                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2183                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2184                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2185                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2186                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2187                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2188                         };
2189
2190                         i2s0_8ch_bus: i2s0-8ch-bus {
2191                                 rockchip,pins =
2192                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2193                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2194                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2195                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2196                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2197                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2198                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2199                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2200                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2201                         };
2202                 };
2203
2204                 i2s1 {
2205                         i2s1_2ch_bus: i2s1-2ch-bus {
2206                                 rockchip,pins =
2207                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2208                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2209                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2210                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2211                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2212                         };
2213                 };
2214
2215                 sdio0 {
2216                         sdio0_bus1: sdio0-bus1 {
2217                                 rockchip,pins =
2218                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2219                         };
2220
2221                         sdio0_bus4: sdio0-bus4 {
2222                                 rockchip,pins =
2223                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2224                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2225                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2226                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2227                         };
2228
2229                         sdio0_cmd: sdio0-cmd {
2230                                 rockchip,pins =
2231                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2232                         };
2233
2234                         sdio0_clk: sdio0-clk {
2235                                 rockchip,pins =
2236                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2237                         };
2238
2239                         sdio0_cd: sdio0-cd {
2240                                 rockchip,pins =
2241                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2242                         };
2243
2244                         sdio0_pwr: sdio0-pwr {
2245                                 rockchip,pins =
2246                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2247                         };
2248
2249                         sdio0_bkpwr: sdio0-bkpwr {
2250                                 rockchip,pins =
2251                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2252                         };
2253
2254                         sdio0_wp: sdio0-wp {
2255                                 rockchip,pins =
2256                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2257                         };
2258
2259                         sdio0_int: sdio0-int {
2260                                 rockchip,pins =
2261                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2262                         };
2263                 };
2264
2265                 sdmmc {
2266                         sdmmc_bus1: sdmmc-bus1 {
2267                                 rockchip,pins =
2268                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2269                         };
2270
2271                         sdmmc_bus4: sdmmc-bus4 {
2272                                 rockchip,pins =
2273                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2274                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2275                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2276                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2277                         };
2278
2279                         sdmmc_clk: sdmmc-clk {
2280                                 rockchip,pins =
2281                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2282                         };
2283
2284                         sdmmc_cmd: sdmmc-cmd {
2285                                 rockchip,pins =
2286                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2287                         };
2288
2289                         sdmmc_cd: sdmmc-cd {
2290                                 rockchip,pins =
2291                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2292                         };
2293
2294                         sdmmc_wp: sdmmc-wp {
2295                                 rockchip,pins =
2296                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2297                         };
2298                 };
2299
2300                 sleep {
2301                         ap_pwroff: ap-pwroff {
2302                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2303                         };
2304
2305                         ddrio_pwroff: ddrio-pwroff {
2306                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2307                         };
2308                 };
2309
2310                 spdif {
2311                         spdif_bus: spdif-bus {
2312                                 rockchip,pins =
2313                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2314                         };
2315
2316                         spdif_bus_1: spdif-bus-1 {
2317                                 rockchip,pins =
2318                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2319                         };
2320                 };
2321
2322                 spi0 {
2323                         spi0_clk: spi0-clk {
2324                                 rockchip,pins =
2325                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2326                         };
2327                         spi0_cs0: spi0-cs0 {
2328                                 rockchip,pins =
2329                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2330                         };
2331                         spi0_cs1: spi0-cs1 {
2332                                 rockchip,pins =
2333                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2334                         };
2335                         spi0_tx: spi0-tx {
2336                                 rockchip,pins =
2337                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2338                         };
2339                         spi0_rx: spi0-rx {
2340                                 rockchip,pins =
2341                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2342                         };
2343                 };
2344
2345                 spi1 {
2346                         spi1_clk: spi1-clk {
2347                                 rockchip,pins =
2348                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2349                         };
2350                         spi1_cs0: spi1-cs0 {
2351                                 rockchip,pins =
2352                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2353                         };
2354                         spi1_rx: spi1-rx {
2355                                 rockchip,pins =
2356                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2357                         };
2358                         spi1_tx: spi1-tx {
2359                                 rockchip,pins =
2360                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2361                         };
2362                 };
2363
2364                 spi2 {
2365                         spi2_clk: spi2-clk {
2366                                 rockchip,pins =
2367                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2368                         };
2369                         spi2_cs0: spi2-cs0 {
2370                                 rockchip,pins =
2371                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2372                         };
2373                         spi2_rx: spi2-rx {
2374                                 rockchip,pins =
2375                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2376                         };
2377                         spi2_tx: spi2-tx {
2378                                 rockchip,pins =
2379                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2380                         };
2381                 };
2382
2383                 spi3 {
2384                         spi3_clk: spi3-clk {
2385                                 rockchip,pins =
2386                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2387                         };
2388                         spi3_cs0: spi3-cs0 {
2389                                 rockchip,pins =
2390                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2391                         };
2392                         spi3_rx: spi3-rx {
2393                                 rockchip,pins =
2394                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2395                         };
2396                         spi3_tx: spi3-tx {
2397                                 rockchip,pins =
2398                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2399                         };
2400                 };
2401
2402                 spi4 {
2403                         spi4_clk: spi4-clk {
2404                                 rockchip,pins =
2405                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2406                         };
2407                         spi4_cs0: spi4-cs0 {
2408                                 rockchip,pins =
2409                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2410                         };
2411                         spi4_rx: spi4-rx {
2412                                 rockchip,pins =
2413                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2414                         };
2415                         spi4_tx: spi4-tx {
2416                                 rockchip,pins =
2417                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2418                         };
2419                 };
2420
2421                 spi5 {
2422                         spi5_clk: spi5-clk {
2423                                 rockchip,pins =
2424                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2425                         };
2426                         spi5_cs0: spi5-cs0 {
2427                                 rockchip,pins =
2428                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2429                         };
2430                         spi5_rx: spi5-rx {
2431                                 rockchip,pins =
2432                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2433                         };
2434                         spi5_tx: spi5-tx {
2435                                 rockchip,pins =
2436                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2437                         };
2438                 };
2439
2440                 testclk {
2441                         test_clkout0: test-clkout0 {
2442                                 rockchip,pins =
2443                                         <0 0 RK_FUNC_1 &pcfg_pull_none>;
2444                         };
2445
2446                         test_clkout1: test-clkout1 {
2447                                 rockchip,pins =
2448                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
2449                         };
2450
2451                         test_clkout2: test-clkout2 {
2452                                 rockchip,pins =
2453                                         <0 8 RK_FUNC_3 &pcfg_pull_none>;
2454                         };
2455                 };
2456
2457                 tsadc {
2458                         otp_gpio: otp-gpio {
2459                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2460                         };
2461
2462                         otp_out: otp-out {
2463                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2464                         };
2465                 };
2466
2467                 uart0 {
2468                         uart0_xfer: uart0-xfer {
2469                                 rockchip,pins =
2470                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2471                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2472                         };
2473
2474                         uart0_cts: uart0-cts {
2475                                 rockchip,pins =
2476                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2477                         };
2478
2479                         uart0_rts: uart0-rts {
2480                                 rockchip,pins =
2481                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2482                         };
2483                 };
2484
2485                 uart1 {
2486                         uart1_xfer: uart1-xfer {
2487                                 rockchip,pins =
2488                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2489                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2490                         };
2491                 };
2492
2493                 uart2a {
2494                         uart2a_xfer: uart2a-xfer {
2495                                 rockchip,pins =
2496                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2497                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2498                         };
2499                 };
2500
2501                 uart2b {
2502                         uart2b_xfer: uart2b-xfer {
2503                                 rockchip,pins =
2504                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2505                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2506                         };
2507                 };
2508
2509                 uart2c {
2510                         uart2c_xfer: uart2c-xfer {
2511                                 rockchip,pins =
2512                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2513                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2514                         };
2515                 };
2516
2517                 uart3 {
2518                         uart3_xfer: uart3-xfer {
2519                                 rockchip,pins =
2520                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2521                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2522                         };
2523
2524                         uart3_cts: uart3-cts {
2525                                 rockchip,pins =
2526                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2527                         };
2528
2529                         uart3_rts: uart3-rts {
2530                                 rockchip,pins =
2531                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2532                         };
2533                 };
2534
2535                 uart4 {
2536                         uart4_xfer: uart4-xfer {
2537                                 rockchip,pins =
2538                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2539                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2540                         };
2541                 };
2542
2543                 uarthdcp {
2544                         uarthdcp_xfer: uarthdcp-xfer {
2545                                 rockchip,pins =
2546                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2547                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2548                         };
2549                 };
2550
2551                 pwm0 {
2552                         pwm0_pin: pwm0-pin {
2553                                 rockchip,pins =
2554                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2555                         };
2556
2557                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2558                                 rockchip,pins =
2559                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
2560                         };
2561
2562                         vop0_pwm_pin: vop0-pwm-pin {
2563                                 rockchip,pins =
2564                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2565                         };
2566
2567                         vop1_pwm_pin: vop1-pwm-pin {
2568                                 rockchip,pins =
2569                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2570                         };
2571                 };
2572
2573                 pwm1 {
2574                         pwm1_pin: pwm1-pin {
2575                                 rockchip,pins =
2576                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2577                         };
2578
2579                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2580                                 rockchip,pins =
2581                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
2582                         };
2583                 };
2584
2585                 pwm2 {
2586                         pwm2_pin: pwm2-pin {
2587                                 rockchip,pins =
2588                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2589                         };
2590
2591                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2592                                 rockchip,pins =
2593                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
2594                         };
2595                 };
2596
2597                 pwm3a {
2598                         pwm3a_pin: pwm3a-pin {
2599                                 rockchip,pins =
2600                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2601                         };
2602                 };
2603
2604                 pwm3b {
2605                         pwm3b_pin: pwm3b-pin {
2606                                 rockchip,pins =
2607                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2608                         };
2609                 };
2610
2611                 hdmi {
2612                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2613                                 rockchip,pins =
2614                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2615                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2616                         };
2617
2618                         hdmi_cec: hdmi-cec {
2619                                 rockchip,pins =
2620                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2621                         };
2622                 };
2623
2624                 pcie {
2625                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2626                                 rockchip,pins =
2627                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2628                         };
2629
2630                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2631                                 rockchip,pins =
2632                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2633                         };
2634                 };
2635
2636         };
2637 };