arm64: dts: rockchip: add Gru Scarlet devicetrees
[muen/linux.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4  */
5
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15         compatible = "rockchip,rk3399";
16
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
20
21         aliases {
22                 ethernet0 = &gmac;
23                 i2c0 = &i2c0;
24                 i2c1 = &i2c1;
25                 i2c2 = &i2c2;
26                 i2c3 = &i2c3;
27                 i2c4 = &i2c4;
28                 i2c5 = &i2c5;
29                 i2c6 = &i2c6;
30                 i2c7 = &i2c7;
31                 i2c8 = &i2c8;
32                 serial0 = &uart0;
33                 serial1 = &uart1;
34                 serial2 = &uart2;
35                 serial3 = &uart3;
36                 serial4 = &uart4;
37         };
38
39         cpus {
40                 #address-cells = <2>;
41                 #size-cells = <0>;
42
43                 cpu-map {
44                         cluster0 {
45                                 core0 {
46                                         cpu = <&cpu_l0>;
47                                 };
48                                 core1 {
49                                         cpu = <&cpu_l1>;
50                                 };
51                                 core2 {
52                                         cpu = <&cpu_l2>;
53                                 };
54                                 core3 {
55                                         cpu = <&cpu_l3>;
56                                 };
57                         };
58
59                         cluster1 {
60                                 core0 {
61                                         cpu = <&cpu_b0>;
62                                 };
63                                 core1 {
64                                         cpu = <&cpu_b1>;
65                                 };
66                         };
67                 };
68
69                 cpu_l0: cpu@0 {
70                         device_type = "cpu";
71                         compatible = "arm,cortex-a53", "arm,armv8";
72                         reg = <0x0 0x0>;
73                         enable-method = "psci";
74                         clocks = <&cru ARMCLKL>;
75                         #cooling-cells = <2>; /* min followed by max */
76                         dynamic-power-coefficient = <100>;
77                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
78                 };
79
80                 cpu_l1: cpu@1 {
81                         device_type = "cpu";
82                         compatible = "arm,cortex-a53", "arm,armv8";
83                         reg = <0x0 0x1>;
84                         enable-method = "psci";
85                         clocks = <&cru ARMCLKL>;
86                         #cooling-cells = <2>; /* min followed by max */
87                         dynamic-power-coefficient = <100>;
88                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
89                 };
90
91                 cpu_l2: cpu@2 {
92                         device_type = "cpu";
93                         compatible = "arm,cortex-a53", "arm,armv8";
94                         reg = <0x0 0x2>;
95                         enable-method = "psci";
96                         clocks = <&cru ARMCLKL>;
97                         #cooling-cells = <2>; /* min followed by max */
98                         dynamic-power-coefficient = <100>;
99                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
100                 };
101
102                 cpu_l3: cpu@3 {
103                         device_type = "cpu";
104                         compatible = "arm,cortex-a53", "arm,armv8";
105                         reg = <0x0 0x3>;
106                         enable-method = "psci";
107                         clocks = <&cru ARMCLKL>;
108                         #cooling-cells = <2>; /* min followed by max */
109                         dynamic-power-coefficient = <100>;
110                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
111                 };
112
113                 cpu_b0: cpu@100 {
114                         device_type = "cpu";
115                         compatible = "arm,cortex-a72", "arm,armv8";
116                         reg = <0x0 0x100>;
117                         enable-method = "psci";
118                         clocks = <&cru ARMCLKB>;
119                         #cooling-cells = <2>; /* min followed by max */
120                         dynamic-power-coefficient = <436>;
121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122                 };
123
124                 cpu_b1: cpu@101 {
125                         device_type = "cpu";
126                         compatible = "arm,cortex-a72", "arm,armv8";
127                         reg = <0x0 0x101>;
128                         enable-method = "psci";
129                         clocks = <&cru ARMCLKB>;
130                         #cooling-cells = <2>; /* min followed by max */
131                         dynamic-power-coefficient = <436>;
132                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
133                 };
134
135                 idle-states {
136                         entry-method = "psci";
137
138                         CPU_SLEEP: cpu-sleep {
139                                 compatible = "arm,idle-state";
140                                 local-timer-stop;
141                                 arm,psci-suspend-param = <0x0010000>;
142                                 entry-latency-us = <120>;
143                                 exit-latency-us = <250>;
144                                 min-residency-us = <900>;
145                         };
146
147                         CLUSTER_SLEEP: cluster-sleep {
148                                 compatible = "arm,idle-state";
149                                 local-timer-stop;
150                                 arm,psci-suspend-param = <0x1010000>;
151                                 entry-latency-us = <400>;
152                                 exit-latency-us = <500>;
153                                 min-residency-us = <2000>;
154                         };
155                 };
156         };
157
158         display-subsystem {
159                 compatible = "rockchip,display-subsystem";
160                 ports = <&vopl_out>, <&vopb_out>;
161         };
162
163         pmu_a53 {
164                 compatible = "arm,cortex-a53-pmu";
165                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
166         };
167
168         pmu_a72 {
169                 compatible = "arm,cortex-a72-pmu";
170                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
171         };
172
173         psci {
174                 compatible = "arm,psci-1.0";
175                 method = "smc";
176         };
177
178         timer {
179                 compatible = "arm,armv8-timer";
180                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
181                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
182                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
183                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
184                 arm,no-tick-in-suspend;
185         };
186
187         xin24m: xin24m {
188                 compatible = "fixed-clock";
189                 clock-frequency = <24000000>;
190                 clock-output-names = "xin24m";
191                 #clock-cells = <0>;
192         };
193
194         amba {
195                 compatible = "simple-bus";
196                 #address-cells = <2>;
197                 #size-cells = <2>;
198                 ranges;
199
200                 dmac_bus: dma-controller@ff6d0000 {
201                         compatible = "arm,pl330", "arm,primecell";
202                         reg = <0x0 0xff6d0000 0x0 0x4000>;
203                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
204                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
205                         #dma-cells = <1>;
206                         clocks = <&cru ACLK_DMAC0_PERILP>;
207                         clock-names = "apb_pclk";
208                 };
209
210                 dmac_peri: dma-controller@ff6e0000 {
211                         compatible = "arm,pl330", "arm,primecell";
212                         reg = <0x0 0xff6e0000 0x0 0x4000>;
213                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
214                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
215                         #dma-cells = <1>;
216                         clocks = <&cru ACLK_DMAC1_PERILP>;
217                         clock-names = "apb_pclk";
218                 };
219         };
220
221         pcie0: pcie@f8000000 {
222                 compatible = "rockchip,rk3399-pcie";
223                 reg = <0x0 0xf8000000 0x0 0x2000000>,
224                       <0x0 0xfd000000 0x0 0x1000000>;
225                 reg-names = "axi-base", "apb-base";
226                 #address-cells = <3>;
227                 #size-cells = <2>;
228                 #interrupt-cells = <1>;
229                 aspm-no-l0s;
230                 bus-range = <0x0 0x1f>;
231                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
232                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
233                 clock-names = "aclk", "aclk-perf",
234                               "hclk", "pm";
235                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
236                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
237                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
238                 interrupt-names = "sys", "legacy", "client";
239                 interrupt-map-mask = <0 0 0 7>;
240                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
241                                 <0 0 0 2 &pcie0_intc 1>,
242                                 <0 0 0 3 &pcie0_intc 2>,
243                                 <0 0 0 4 &pcie0_intc 3>;
244                 linux,pci-domain = <0>;
245                 max-link-speed = <1>;
246                 msi-map = <0x0 &its 0x0 0x1000>;
247                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
248                        <&pcie_phy 2>, <&pcie_phy 3>;
249                 phy-names = "pcie-phy-0", "pcie-phy-1",
250                             "pcie-phy-2", "pcie-phy-3";
251                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
252                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
253                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
254                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
255                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
256                          <&cru SRST_A_PCIE>;
257                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
258                               "pm", "pclk", "aclk";
259                 status = "disabled";
260
261                 pcie0_intc: interrupt-controller {
262                         interrupt-controller;
263                         #address-cells = <0>;
264                         #interrupt-cells = <1>;
265                 };
266         };
267
268         gmac: ethernet@fe300000 {
269                 compatible = "rockchip,rk3399-gmac";
270                 reg = <0x0 0xfe300000 0x0 0x10000>;
271                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
272                 interrupt-names = "macirq";
273                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
274                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
275                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
276                          <&cru PCLK_GMAC>;
277                 clock-names = "stmmaceth", "mac_clk_rx",
278                               "mac_clk_tx", "clk_mac_ref",
279                               "clk_mac_refout", "aclk_mac",
280                               "pclk_mac";
281                 power-domains = <&power RK3399_PD_GMAC>;
282                 resets = <&cru SRST_A_GMAC>;
283                 reset-names = "stmmaceth";
284                 rockchip,grf = <&grf>;
285                 status = "disabled";
286         };
287
288         sdio0: dwmmc@fe310000 {
289                 compatible = "rockchip,rk3399-dw-mshc",
290                              "rockchip,rk3288-dw-mshc";
291                 reg = <0x0 0xfe310000 0x0 0x4000>;
292                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
293                 max-frequency = <150000000>;
294                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
295                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
296                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
297                 fifo-depth = <0x100>;
298                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
299                 resets = <&cru SRST_SDIO0>;
300                 reset-names = "reset";
301                 status = "disabled";
302         };
303
304         sdmmc: dwmmc@fe320000 {
305                 compatible = "rockchip,rk3399-dw-mshc",
306                              "rockchip,rk3288-dw-mshc";
307                 reg = <0x0 0xfe320000 0x0 0x4000>;
308                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
309                 max-frequency = <150000000>;
310                 assigned-clocks = <&cru HCLK_SD>;
311                 assigned-clock-rates = <200000000>;
312                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
313                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
314                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
315                 fifo-depth = <0x100>;
316                 power-domains = <&power RK3399_PD_SD>;
317                 resets = <&cru SRST_SDMMC>;
318                 reset-names = "reset";
319                 status = "disabled";
320         };
321
322         sdhci: sdhci@fe330000 {
323                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
324                 reg = <0x0 0xfe330000 0x0 0x10000>;
325                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
326                 arasan,soc-ctl-syscon = <&grf>;
327                 assigned-clocks = <&cru SCLK_EMMC>;
328                 assigned-clock-rates = <200000000>;
329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
330                 clock-names = "clk_xin", "clk_ahb";
331                 clock-output-names = "emmc_cardclock";
332                 #clock-cells = <0>;
333                 phys = <&emmc_phy>;
334                 phy-names = "phy_arasan";
335                 power-domains = <&power RK3399_PD_EMMC>;
336                 status = "disabled";
337         };
338
339         usb_host0_ehci: usb@fe380000 {
340                 compatible = "generic-ehci";
341                 reg = <0x0 0xfe380000 0x0 0x20000>;
342                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
343                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
344                          <&u2phy0>;
345                 clock-names = "usbhost", "arbiter",
346                               "utmi";
347                 phys = <&u2phy0_host>;
348                 phy-names = "usb";
349                 status = "disabled";
350         };
351
352         usb_host0_ohci: usb@fe3a0000 {
353                 compatible = "generic-ohci";
354                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
357                          <&u2phy0>;
358                 clock-names = "usbhost", "arbiter",
359                               "utmi";
360                 phys = <&u2phy0_host>;
361                 phy-names = "usb";
362                 status = "disabled";
363         };
364
365         usb_host1_ehci: usb@fe3c0000 {
366                 compatible = "generic-ehci";
367                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
368                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
369                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
370                          <&u2phy1>;
371                 clock-names = "usbhost", "arbiter",
372                               "utmi";
373                 phys = <&u2phy1_host>;
374                 phy-names = "usb";
375                 status = "disabled";
376         };
377
378         usb_host1_ohci: usb@fe3e0000 {
379                 compatible = "generic-ohci";
380                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
381                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
382                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
383                          <&u2phy1>;
384                 clock-names = "usbhost", "arbiter",
385                               "utmi";
386                 phys = <&u2phy1_host>;
387                 phy-names = "usb";
388                 status = "disabled";
389         };
390
391         usbdrd3_0: usb@fe800000 {
392                 compatible = "rockchip,rk3399-dwc3";
393                 #address-cells = <2>;
394                 #size-cells = <2>;
395                 ranges;
396                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
397                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
398                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
399                 clock-names = "ref_clk", "suspend_clk",
400                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
401                               "aclk_usb3", "grf_clk";
402                 resets = <&cru SRST_A_USB3_OTG0>;
403                 reset-names = "usb3-otg";
404                 status = "disabled";
405
406                 usbdrd_dwc3_0: dwc3 {
407                         compatible = "snps,dwc3";
408                         reg = <0x0 0xfe800000 0x0 0x100000>;
409                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
410                         dr_mode = "otg";
411                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
412                         phy-names = "usb2-phy", "usb3-phy";
413                         phy_type = "utmi_wide";
414                         snps,dis_enblslpm_quirk;
415                         snps,dis-u2-freeclk-exists-quirk;
416                         snps,dis_u2_susphy_quirk;
417                         snps,dis-del-phy-power-chg-quirk;
418                         snps,dis-tx-ipgap-linecheck-quirk;
419                         power-domains = <&power RK3399_PD_USB3>;
420                         status = "disabled";
421                 };
422         };
423
424         usbdrd3_1: usb@fe900000 {
425                 compatible = "rockchip,rk3399-dwc3";
426                 #address-cells = <2>;
427                 #size-cells = <2>;
428                 ranges;
429                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
430                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
431                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
432                 clock-names = "ref_clk", "suspend_clk",
433                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
434                               "aclk_usb3", "grf_clk";
435                 resets = <&cru SRST_A_USB3_OTG1>;
436                 reset-names = "usb3-otg";
437                 status = "disabled";
438
439                 usbdrd_dwc3_1: dwc3 {
440                         compatible = "snps,dwc3";
441                         reg = <0x0 0xfe900000 0x0 0x100000>;
442                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
443                         dr_mode = "otg";
444                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
445                         phy-names = "usb2-phy", "usb3-phy";
446                         phy_type = "utmi_wide";
447                         snps,dis_enblslpm_quirk;
448                         snps,dis-u2-freeclk-exists-quirk;
449                         snps,dis_u2_susphy_quirk;
450                         snps,dis-del-phy-power-chg-quirk;
451                         snps,dis-tx-ipgap-linecheck-quirk;
452                         power-domains = <&power RK3399_PD_USB3>;
453                         status = "disabled";
454                 };
455         };
456
457         cdn_dp: dp@fec00000 {
458                 compatible = "rockchip,rk3399-cdn-dp";
459                 reg = <0x0 0xfec00000 0x0 0x100000>;
460                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
461                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
462                 assigned-clock-rates = <100000000>, <200000000>;
463                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
464                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
465                 clock-names = "core-clk", "pclk", "spdif", "grf";
466                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
467                 power-domains = <&power RK3399_PD_HDCP>;
468                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
469                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
470                 reset-names = "spdif", "dptx", "apb", "core";
471                 rockchip,grf = <&grf>;
472                 #sound-dai-cells = <1>;
473                 status = "disabled";
474
475                 ports {
476                         dp_in: port {
477                                 #address-cells = <1>;
478                                 #size-cells = <0>;
479
480                                 dp_in_vopb: endpoint@0 {
481                                         reg = <0>;
482                                         remote-endpoint = <&vopb_out_dp>;
483                                 };
484
485                                 dp_in_vopl: endpoint@1 {
486                                         reg = <1>;
487                                         remote-endpoint = <&vopl_out_dp>;
488                                 };
489                         };
490                 };
491         };
492
493         gic: interrupt-controller@fee00000 {
494                 compatible = "arm,gic-v3";
495                 #interrupt-cells = <4>;
496                 #address-cells = <2>;
497                 #size-cells = <2>;
498                 ranges;
499                 interrupt-controller;
500
501                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
502                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
503                       <0x0 0xfff00000 0 0x10000>, /* GICC */
504                       <0x0 0xfff10000 0 0x10000>, /* GICH */
505                       <0x0 0xfff20000 0 0x10000>; /* GICV */
506                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
507                 its: interrupt-controller@fee20000 {
508                         compatible = "arm,gic-v3-its";
509                         msi-controller;
510                         reg = <0x0 0xfee20000 0x0 0x20000>;
511                 };
512
513                 ppi-partitions {
514                         ppi_cluster0: interrupt-partition-0 {
515                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
516                         };
517
518                         ppi_cluster1: interrupt-partition-1 {
519                                 affinity = <&cpu_b0 &cpu_b1>;
520                         };
521                 };
522         };
523
524         saradc: saradc@ff100000 {
525                 compatible = "rockchip,rk3399-saradc";
526                 reg = <0x0 0xff100000 0x0 0x100>;
527                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
528                 #io-channel-cells = <1>;
529                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
530                 clock-names = "saradc", "apb_pclk";
531                 resets = <&cru SRST_P_SARADC>;
532                 reset-names = "saradc-apb";
533                 status = "disabled";
534         };
535
536         i2c1: i2c@ff110000 {
537                 compatible = "rockchip,rk3399-i2c";
538                 reg = <0x0 0xff110000 0x0 0x1000>;
539                 assigned-clocks = <&cru SCLK_I2C1>;
540                 assigned-clock-rates = <200000000>;
541                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
542                 clock-names = "i2c", "pclk";
543                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
544                 pinctrl-names = "default";
545                 pinctrl-0 = <&i2c1_xfer>;
546                 #address-cells = <1>;
547                 #size-cells = <0>;
548                 status = "disabled";
549         };
550
551         i2c2: i2c@ff120000 {
552                 compatible = "rockchip,rk3399-i2c";
553                 reg = <0x0 0xff120000 0x0 0x1000>;
554                 assigned-clocks = <&cru SCLK_I2C2>;
555                 assigned-clock-rates = <200000000>;
556                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
557                 clock-names = "i2c", "pclk";
558                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
559                 pinctrl-names = "default";
560                 pinctrl-0 = <&i2c2_xfer>;
561                 #address-cells = <1>;
562                 #size-cells = <0>;
563                 status = "disabled";
564         };
565
566         i2c3: i2c@ff130000 {
567                 compatible = "rockchip,rk3399-i2c";
568                 reg = <0x0 0xff130000 0x0 0x1000>;
569                 assigned-clocks = <&cru SCLK_I2C3>;
570                 assigned-clock-rates = <200000000>;
571                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
572                 clock-names = "i2c", "pclk";
573                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
574                 pinctrl-names = "default";
575                 pinctrl-0 = <&i2c3_xfer>;
576                 #address-cells = <1>;
577                 #size-cells = <0>;
578                 status = "disabled";
579         };
580
581         i2c5: i2c@ff140000 {
582                 compatible = "rockchip,rk3399-i2c";
583                 reg = <0x0 0xff140000 0x0 0x1000>;
584                 assigned-clocks = <&cru SCLK_I2C5>;
585                 assigned-clock-rates = <200000000>;
586                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
587                 clock-names = "i2c", "pclk";
588                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
589                 pinctrl-names = "default";
590                 pinctrl-0 = <&i2c5_xfer>;
591                 #address-cells = <1>;
592                 #size-cells = <0>;
593                 status = "disabled";
594         };
595
596         i2c6: i2c@ff150000 {
597                 compatible = "rockchip,rk3399-i2c";
598                 reg = <0x0 0xff150000 0x0 0x1000>;
599                 assigned-clocks = <&cru SCLK_I2C6>;
600                 assigned-clock-rates = <200000000>;
601                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
602                 clock-names = "i2c", "pclk";
603                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
604                 pinctrl-names = "default";
605                 pinctrl-0 = <&i2c6_xfer>;
606                 #address-cells = <1>;
607                 #size-cells = <0>;
608                 status = "disabled";
609         };
610
611         i2c7: i2c@ff160000 {
612                 compatible = "rockchip,rk3399-i2c";
613                 reg = <0x0 0xff160000 0x0 0x1000>;
614                 assigned-clocks = <&cru SCLK_I2C7>;
615                 assigned-clock-rates = <200000000>;
616                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
617                 clock-names = "i2c", "pclk";
618                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
619                 pinctrl-names = "default";
620                 pinctrl-0 = <&i2c7_xfer>;
621                 #address-cells = <1>;
622                 #size-cells = <0>;
623                 status = "disabled";
624         };
625
626         uart0: serial@ff180000 {
627                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
628                 reg = <0x0 0xff180000 0x0 0x100>;
629                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
630                 clock-names = "baudclk", "apb_pclk";
631                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
632                 reg-shift = <2>;
633                 reg-io-width = <4>;
634                 pinctrl-names = "default";
635                 pinctrl-0 = <&uart0_xfer>;
636                 status = "disabled";
637         };
638
639         uart1: serial@ff190000 {
640                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641                 reg = <0x0 0xff190000 0x0 0x100>;
642                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
643                 clock-names = "baudclk", "apb_pclk";
644                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
645                 reg-shift = <2>;
646                 reg-io-width = <4>;
647                 pinctrl-names = "default";
648                 pinctrl-0 = <&uart1_xfer>;
649                 status = "disabled";
650         };
651
652         uart2: serial@ff1a0000 {
653                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654                 reg = <0x0 0xff1a0000 0x0 0x100>;
655                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
656                 clock-names = "baudclk", "apb_pclk";
657                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
658                 reg-shift = <2>;
659                 reg-io-width = <4>;
660                 pinctrl-names = "default";
661                 pinctrl-0 = <&uart2c_xfer>;
662                 status = "disabled";
663         };
664
665         uart3: serial@ff1b0000 {
666                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
667                 reg = <0x0 0xff1b0000 0x0 0x100>;
668                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
669                 clock-names = "baudclk", "apb_pclk";
670                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
671                 reg-shift = <2>;
672                 reg-io-width = <4>;
673                 pinctrl-names = "default";
674                 pinctrl-0 = <&uart3_xfer>;
675                 status = "disabled";
676         };
677
678         spi0: spi@ff1c0000 {
679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680                 reg = <0x0 0xff1c0000 0x0 0x1000>;
681                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
682                 clock-names = "spiclk", "apb_pclk";
683                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
684                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
685                 dma-names = "tx", "rx";
686                 pinctrl-names = "default";
687                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
688                 #address-cells = <1>;
689                 #size-cells = <0>;
690                 status = "disabled";
691         };
692
693         spi1: spi@ff1d0000 {
694                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
695                 reg = <0x0 0xff1d0000 0x0 0x1000>;
696                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
697                 clock-names = "spiclk", "apb_pclk";
698                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
699                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
700                 dma-names = "tx", "rx";
701                 pinctrl-names = "default";
702                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
703                 #address-cells = <1>;
704                 #size-cells = <0>;
705                 status = "disabled";
706         };
707
708         spi2: spi@ff1e0000 {
709                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
710                 reg = <0x0 0xff1e0000 0x0 0x1000>;
711                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
712                 clock-names = "spiclk", "apb_pclk";
713                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
714                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
715                 dma-names = "tx", "rx";
716                 pinctrl-names = "default";
717                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
718                 #address-cells = <1>;
719                 #size-cells = <0>;
720                 status = "disabled";
721         };
722
723         spi4: spi@ff1f0000 {
724                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
725                 reg = <0x0 0xff1f0000 0x0 0x1000>;
726                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
727                 clock-names = "spiclk", "apb_pclk";
728                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
729                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
730                 dma-names = "tx", "rx";
731                 pinctrl-names = "default";
732                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
733                 #address-cells = <1>;
734                 #size-cells = <0>;
735                 status = "disabled";
736         };
737
738         spi5: spi@ff200000 {
739                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
740                 reg = <0x0 0xff200000 0x0 0x1000>;
741                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
742                 clock-names = "spiclk", "apb_pclk";
743                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
744                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
745                 dma-names = "tx", "rx";
746                 pinctrl-names = "default";
747                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
748                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
749                 #address-cells = <1>;
750                 #size-cells = <0>;
751                 status = "disabled";
752         };
753
754         thermal_zones: thermal-zones {
755                 cpu_thermal: cpu {
756                         polling-delay-passive = <100>;
757                         polling-delay = <1000>;
758
759                         thermal-sensors = <&tsadc 0>;
760
761                         trips {
762                                 cpu_alert0: cpu_alert0 {
763                                         temperature = <70000>;
764                                         hysteresis = <2000>;
765                                         type = "passive";
766                                 };
767                                 cpu_alert1: cpu_alert1 {
768                                         temperature = <75000>;
769                                         hysteresis = <2000>;
770                                         type = "passive";
771                                 };
772                                 cpu_crit: cpu_crit {
773                                         temperature = <95000>;
774                                         hysteresis = <2000>;
775                                         type = "critical";
776                                 };
777                         };
778
779                         cooling-maps {
780                                 map0 {
781                                         trip = <&cpu_alert0>;
782                                         cooling-device =
783                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
784                                 };
785                                 map1 {
786                                         trip = <&cpu_alert1>;
787                                         cooling-device =
788                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
789                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
790                                 };
791                         };
792                 };
793
794                 gpu_thermal: gpu {
795                         polling-delay-passive = <100>;
796                         polling-delay = <1000>;
797
798                         thermal-sensors = <&tsadc 1>;
799
800                         trips {
801                                 gpu_alert0: gpu_alert0 {
802                                         temperature = <75000>;
803                                         hysteresis = <2000>;
804                                         type = "passive";
805                                 };
806                                 gpu_crit: gpu_crit {
807                                         temperature = <95000>;
808                                         hysteresis = <2000>;
809                                         type = "critical";
810                                 };
811                         };
812
813                         cooling-maps {
814                                 map0 {
815                                         trip = <&gpu_alert0>;
816                                         cooling-device =
817                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
818                                 };
819                         };
820                 };
821         };
822
823         tsadc: tsadc@ff260000 {
824                 compatible = "rockchip,rk3399-tsadc";
825                 reg = <0x0 0xff260000 0x0 0x100>;
826                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
827                 assigned-clocks = <&cru SCLK_TSADC>;
828                 assigned-clock-rates = <750000>;
829                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
830                 clock-names = "tsadc", "apb_pclk";
831                 resets = <&cru SRST_TSADC>;
832                 reset-names = "tsadc-apb";
833                 rockchip,grf = <&grf>;
834                 rockchip,hw-tshut-temp = <95000>;
835                 pinctrl-names = "init", "default", "sleep";
836                 pinctrl-0 = <&otp_gpio>;
837                 pinctrl-1 = <&otp_out>;
838                 pinctrl-2 = <&otp_gpio>;
839                 #thermal-sensor-cells = <1>;
840                 status = "disabled";
841         };
842
843         qos_emmc: qos@ffa58000 {
844                 compatible = "syscon";
845                 reg = <0x0 0xffa58000 0x0 0x20>;
846         };
847
848         qos_gmac: qos@ffa5c000 {
849                 compatible = "syscon";
850                 reg = <0x0 0xffa5c000 0x0 0x20>;
851         };
852
853         qos_pcie: qos@ffa60080 {
854                 compatible = "syscon";
855                 reg = <0x0 0xffa60080 0x0 0x20>;
856         };
857
858         qos_usb_host0: qos@ffa60100 {
859                 compatible = "syscon";
860                 reg = <0x0 0xffa60100 0x0 0x20>;
861         };
862
863         qos_usb_host1: qos@ffa60180 {
864                 compatible = "syscon";
865                 reg = <0x0 0xffa60180 0x0 0x20>;
866         };
867
868         qos_usb_otg0: qos@ffa70000 {
869                 compatible = "syscon";
870                 reg = <0x0 0xffa70000 0x0 0x20>;
871         };
872
873         qos_usb_otg1: qos@ffa70080 {
874                 compatible = "syscon";
875                 reg = <0x0 0xffa70080 0x0 0x20>;
876         };
877
878         qos_sd: qos@ffa74000 {
879                 compatible = "syscon";
880                 reg = <0x0 0xffa74000 0x0 0x20>;
881         };
882
883         qos_sdioaudio: qos@ffa76000 {
884                 compatible = "syscon";
885                 reg = <0x0 0xffa76000 0x0 0x20>;
886         };
887
888         qos_hdcp: qos@ffa90000 {
889                 compatible = "syscon";
890                 reg = <0x0 0xffa90000 0x0 0x20>;
891         };
892
893         qos_iep: qos@ffa98000 {
894                 compatible = "syscon";
895                 reg = <0x0 0xffa98000 0x0 0x20>;
896         };
897
898         qos_isp0_m0: qos@ffaa0000 {
899                 compatible = "syscon";
900                 reg = <0x0 0xffaa0000 0x0 0x20>;
901         };
902
903         qos_isp0_m1: qos@ffaa0080 {
904                 compatible = "syscon";
905                 reg = <0x0 0xffaa0080 0x0 0x20>;
906         };
907
908         qos_isp1_m0: qos@ffaa8000 {
909                 compatible = "syscon";
910                 reg = <0x0 0xffaa8000 0x0 0x20>;
911         };
912
913         qos_isp1_m1: qos@ffaa8080 {
914                 compatible = "syscon";
915                 reg = <0x0 0xffaa8080 0x0 0x20>;
916         };
917
918         qos_rga_r: qos@ffab0000 {
919                 compatible = "syscon";
920                 reg = <0x0 0xffab0000 0x0 0x20>;
921         };
922
923         qos_rga_w: qos@ffab0080 {
924                 compatible = "syscon";
925                 reg = <0x0 0xffab0080 0x0 0x20>;
926         };
927
928         qos_video_m0: qos@ffab8000 {
929                 compatible = "syscon";
930                 reg = <0x0 0xffab8000 0x0 0x20>;
931         };
932
933         qos_video_m1_r: qos@ffac0000 {
934                 compatible = "syscon";
935                 reg = <0x0 0xffac0000 0x0 0x20>;
936         };
937
938         qos_video_m1_w: qos@ffac0080 {
939                 compatible = "syscon";
940                 reg = <0x0 0xffac0080 0x0 0x20>;
941         };
942
943         qos_vop_big_r: qos@ffac8000 {
944                 compatible = "syscon";
945                 reg = <0x0 0xffac8000 0x0 0x20>;
946         };
947
948         qos_vop_big_w: qos@ffac8080 {
949                 compatible = "syscon";
950                 reg = <0x0 0xffac8080 0x0 0x20>;
951         };
952
953         qos_vop_little: qos@ffad0000 {
954                 compatible = "syscon";
955                 reg = <0x0 0xffad0000 0x0 0x20>;
956         };
957
958         qos_perihp: qos@ffad8080 {
959                 compatible = "syscon";
960                 reg = <0x0 0xffad8080 0x0 0x20>;
961         };
962
963         qos_gpu: qos@ffae0000 {
964                 compatible = "syscon";
965                 reg = <0x0 0xffae0000 0x0 0x20>;
966         };
967
968         pmu: power-management@ff310000 {
969                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
970                 reg = <0x0 0xff310000 0x0 0x1000>;
971
972                 /*
973                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
974                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
975                  * Some of the power domains are grouped together for every
976                  * voltage domain.
977                  * The detail contents as below.
978                  */
979                 power: power-controller {
980                         compatible = "rockchip,rk3399-power-controller";
981                         #power-domain-cells = <1>;
982                         #address-cells = <1>;
983                         #size-cells = <0>;
984
985                         /* These power domains are grouped by VD_CENTER */
986                         pd_iep@RK3399_PD_IEP {
987                                 reg = <RK3399_PD_IEP>;
988                                 clocks = <&cru ACLK_IEP>,
989                                          <&cru HCLK_IEP>;
990                                 pm_qos = <&qos_iep>;
991                         };
992                         pd_rga@RK3399_PD_RGA {
993                                 reg = <RK3399_PD_RGA>;
994                                 clocks = <&cru ACLK_RGA>,
995                                          <&cru HCLK_RGA>;
996                                 pm_qos = <&qos_rga_r>,
997                                          <&qos_rga_w>;
998                         };
999                         pd_vcodec@RK3399_PD_VCODEC {
1000                                 reg = <RK3399_PD_VCODEC>;
1001                                 clocks = <&cru ACLK_VCODEC>,
1002                                          <&cru HCLK_VCODEC>;
1003                                 pm_qos = <&qos_video_m0>;
1004                         };
1005                         pd_vdu@RK3399_PD_VDU {
1006                                 reg = <RK3399_PD_VDU>;
1007                                 clocks = <&cru ACLK_VDU>,
1008                                          <&cru HCLK_VDU>;
1009                                 pm_qos = <&qos_video_m1_r>,
1010                                          <&qos_video_m1_w>;
1011                         };
1012
1013                         /* These power domains are grouped by VD_GPU */
1014                         pd_gpu@RK3399_PD_GPU {
1015                                 reg = <RK3399_PD_GPU>;
1016                                 clocks = <&cru ACLK_GPU>;
1017                                 pm_qos = <&qos_gpu>;
1018                         };
1019
1020                         /* These power domains are grouped by VD_LOGIC */
1021                         pd_edp@RK3399_PD_EDP {
1022                                 reg = <RK3399_PD_EDP>;
1023                                 clocks = <&cru PCLK_EDP_CTRL>;
1024                         };
1025                         pd_emmc@RK3399_PD_EMMC {
1026                                 reg = <RK3399_PD_EMMC>;
1027                                 clocks = <&cru ACLK_EMMC>;
1028                                 pm_qos = <&qos_emmc>;
1029                         };
1030                         pd_gmac@RK3399_PD_GMAC {
1031                                 reg = <RK3399_PD_GMAC>;
1032                                 clocks = <&cru ACLK_GMAC>,
1033                                          <&cru PCLK_GMAC>;
1034                                 pm_qos = <&qos_gmac>;
1035                         };
1036                         pd_sd@RK3399_PD_SD {
1037                                 reg = <RK3399_PD_SD>;
1038                                 clocks = <&cru HCLK_SDMMC>,
1039                                          <&cru SCLK_SDMMC>;
1040                                 pm_qos = <&qos_sd>;
1041                         };
1042                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1043                                 reg = <RK3399_PD_SDIOAUDIO>;
1044                                 clocks = <&cru HCLK_SDIO>;
1045                                 pm_qos = <&qos_sdioaudio>;
1046                         };
1047                         pd_usb3@RK3399_PD_USB3 {
1048                                 reg = <RK3399_PD_USB3>;
1049                                 clocks = <&cru ACLK_USB3>;
1050                                 pm_qos = <&qos_usb_otg0>,
1051                                          <&qos_usb_otg1>;
1052                         };
1053                         pd_vio@RK3399_PD_VIO {
1054                                 reg = <RK3399_PD_VIO>;
1055                                 #address-cells = <1>;
1056                                 #size-cells = <0>;
1057
1058                                 pd_hdcp@RK3399_PD_HDCP {
1059                                         reg = <RK3399_PD_HDCP>;
1060                                         clocks = <&cru ACLK_HDCP>,
1061                                                  <&cru HCLK_HDCP>,
1062                                                  <&cru PCLK_HDCP>;
1063                                         pm_qos = <&qos_hdcp>;
1064                                 };
1065                                 pd_isp0@RK3399_PD_ISP0 {
1066                                         reg = <RK3399_PD_ISP0>;
1067                                         clocks = <&cru ACLK_ISP0>,
1068                                                  <&cru HCLK_ISP0>;
1069                                         pm_qos = <&qos_isp0_m0>,
1070                                                  <&qos_isp0_m1>;
1071                                 };
1072                                 pd_isp1@RK3399_PD_ISP1 {
1073                                         reg = <RK3399_PD_ISP1>;
1074                                         clocks = <&cru ACLK_ISP1>,
1075                                                  <&cru HCLK_ISP1>;
1076                                         pm_qos = <&qos_isp1_m0>,
1077                                                  <&qos_isp1_m1>;
1078                                 };
1079                                 pd_tcpc0@RK3399_PD_TCPC0 {
1080                                         reg = <RK3399_PD_TCPD0>;
1081                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1082                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1083                                 };
1084                                 pd_tcpc1@RK3399_PD_TCPC1 {
1085                                         reg = <RK3399_PD_TCPD1>;
1086                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1087                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1088                                 };
1089                                 pd_vo@RK3399_PD_VO {
1090                                         reg = <RK3399_PD_VO>;
1091                                         #address-cells = <1>;
1092                                         #size-cells = <0>;
1093
1094                                         pd_vopb@RK3399_PD_VOPB {
1095                                                 reg = <RK3399_PD_VOPB>;
1096                                                 clocks = <&cru ACLK_VOP0>,
1097                                                          <&cru HCLK_VOP0>;
1098                                                 pm_qos = <&qos_vop_big_r>,
1099                                                          <&qos_vop_big_w>;
1100                                         };
1101                                         pd_vopl@RK3399_PD_VOPL {
1102                                                 reg = <RK3399_PD_VOPL>;
1103                                                 clocks = <&cru ACLK_VOP1>,
1104                                                          <&cru HCLK_VOP1>;
1105                                                 pm_qos = <&qos_vop_little>;
1106                                         };
1107                                 };
1108                         };
1109                 };
1110         };
1111
1112         pmugrf: syscon@ff320000 {
1113                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1114                 reg = <0x0 0xff320000 0x0 0x1000>;
1115                 #address-cells = <1>;
1116                 #size-cells = <1>;
1117
1118                 pmu_io_domains: io-domains {
1119                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1120                         status = "disabled";
1121                 };
1122         };
1123
1124         spi3: spi@ff350000 {
1125                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1126                 reg = <0x0 0xff350000 0x0 0x1000>;
1127                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1128                 clock-names = "spiclk", "apb_pclk";
1129                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1130                 pinctrl-names = "default";
1131                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1132                 #address-cells = <1>;
1133                 #size-cells = <0>;
1134                 status = "disabled";
1135         };
1136
1137         uart4: serial@ff370000 {
1138                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1139                 reg = <0x0 0xff370000 0x0 0x100>;
1140                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1141                 clock-names = "baudclk", "apb_pclk";
1142                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1143                 reg-shift = <2>;
1144                 reg-io-width = <4>;
1145                 pinctrl-names = "default";
1146                 pinctrl-0 = <&uart4_xfer>;
1147                 status = "disabled";
1148         };
1149
1150         i2c0: i2c@ff3c0000 {
1151                 compatible = "rockchip,rk3399-i2c";
1152                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1153                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1154                 assigned-clock-rates = <200000000>;
1155                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1156                 clock-names = "i2c", "pclk";
1157                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1158                 pinctrl-names = "default";
1159                 pinctrl-0 = <&i2c0_xfer>;
1160                 #address-cells = <1>;
1161                 #size-cells = <0>;
1162                 status = "disabled";
1163         };
1164
1165         i2c4: i2c@ff3d0000 {
1166                 compatible = "rockchip,rk3399-i2c";
1167                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1168                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1169                 assigned-clock-rates = <200000000>;
1170                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1171                 clock-names = "i2c", "pclk";
1172                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1173                 pinctrl-names = "default";
1174                 pinctrl-0 = <&i2c4_xfer>;
1175                 #address-cells = <1>;
1176                 #size-cells = <0>;
1177                 status = "disabled";
1178         };
1179
1180         i2c8: i2c@ff3e0000 {
1181                 compatible = "rockchip,rk3399-i2c";
1182                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1183                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1184                 assigned-clock-rates = <200000000>;
1185                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1186                 clock-names = "i2c", "pclk";
1187                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1188                 pinctrl-names = "default";
1189                 pinctrl-0 = <&i2c8_xfer>;
1190                 #address-cells = <1>;
1191                 #size-cells = <0>;
1192                 status = "disabled";
1193         };
1194
1195         pwm0: pwm@ff420000 {
1196                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1197                 reg = <0x0 0xff420000 0x0 0x10>;
1198                 #pwm-cells = <3>;
1199                 pinctrl-names = "default";
1200                 pinctrl-0 = <&pwm0_pin>;
1201                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1202                 clock-names = "pwm";
1203                 status = "disabled";
1204         };
1205
1206         pwm1: pwm@ff420010 {
1207                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1208                 reg = <0x0 0xff420010 0x0 0x10>;
1209                 #pwm-cells = <3>;
1210                 pinctrl-names = "default";
1211                 pinctrl-0 = <&pwm1_pin>;
1212                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1213                 clock-names = "pwm";
1214                 status = "disabled";
1215         };
1216
1217         pwm2: pwm@ff420020 {
1218                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1219                 reg = <0x0 0xff420020 0x0 0x10>;
1220                 #pwm-cells = <3>;
1221                 pinctrl-names = "default";
1222                 pinctrl-0 = <&pwm2_pin>;
1223                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1224                 clock-names = "pwm";
1225                 status = "disabled";
1226         };
1227
1228         pwm3: pwm@ff420030 {
1229                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1230                 reg = <0x0 0xff420030 0x0 0x10>;
1231                 #pwm-cells = <3>;
1232                 pinctrl-names = "default";
1233                 pinctrl-0 = <&pwm3a_pin>;
1234                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1235                 clock-names = "pwm";
1236                 status = "disabled";
1237         };
1238
1239         vpu_mmu: iommu@ff650800 {
1240                 compatible = "rockchip,iommu";
1241                 reg = <0x0 0xff650800 0x0 0x40>;
1242                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1243                 interrupt-names = "vpu_mmu";
1244                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1245                 clock-names = "aclk", "iface";
1246                 #iommu-cells = <0>;
1247                 status = "disabled";
1248         };
1249
1250         vdec_mmu: iommu@ff660480 {
1251                 compatible = "rockchip,iommu";
1252                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1253                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1254                 interrupt-names = "vdec_mmu";
1255                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1256                 clock-names = "aclk", "iface";
1257                 #iommu-cells = <0>;
1258                 status = "disabled";
1259         };
1260
1261         iep_mmu: iommu@ff670800 {
1262                 compatible = "rockchip,iommu";
1263                 reg = <0x0 0xff670800 0x0 0x40>;
1264                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1265                 interrupt-names = "iep_mmu";
1266                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1267                 clock-names = "aclk", "iface";
1268                 #iommu-cells = <0>;
1269                 status = "disabled";
1270         };
1271
1272         rga: rga@ff680000 {
1273                 compatible = "rockchip,rk3399-rga";
1274                 reg = <0x0 0xff680000 0x0 0x10000>;
1275                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1276                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1277                 clock-names = "aclk", "hclk", "sclk";
1278                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1279                 reset-names = "core", "axi", "ahb";
1280                 power-domains = <&power RK3399_PD_RGA>;
1281         };
1282
1283         efuse0: efuse@ff690000 {
1284                 compatible = "rockchip,rk3399-efuse";
1285                 reg = <0x0 0xff690000 0x0 0x80>;
1286                 #address-cells = <1>;
1287                 #size-cells = <1>;
1288                 clocks = <&cru PCLK_EFUSE1024NS>;
1289                 clock-names = "pclk_efuse";
1290
1291                 /* Data cells */
1292                 cpu_id: cpu-id@7 {
1293                         reg = <0x07 0x10>;
1294                 };
1295                 cpub_leakage: cpu-leakage@17 {
1296                         reg = <0x17 0x1>;
1297                 };
1298                 gpu_leakage: gpu-leakage@18 {
1299                         reg = <0x18 0x1>;
1300                 };
1301                 center_leakage: center-leakage@19 {
1302                         reg = <0x19 0x1>;
1303                 };
1304                 cpul_leakage: cpu-leakage@1a {
1305                         reg = <0x1a 0x1>;
1306                 };
1307                 logic_leakage: logic-leakage@1b {
1308                         reg = <0x1b 0x1>;
1309                 };
1310                 wafer_info: wafer-info@1c {
1311                         reg = <0x1c 0x1>;
1312                 };
1313         };
1314
1315         pmucru: pmu-clock-controller@ff750000 {
1316                 compatible = "rockchip,rk3399-pmucru";
1317                 reg = <0x0 0xff750000 0x0 0x1000>;
1318                 rockchip,grf = <&pmugrf>;
1319                 #clock-cells = <1>;
1320                 #reset-cells = <1>;
1321                 assigned-clocks = <&pmucru PLL_PPLL>;
1322                 assigned-clock-rates = <676000000>;
1323         };
1324
1325         cru: clock-controller@ff760000 {
1326                 compatible = "rockchip,rk3399-cru";
1327                 reg = <0x0 0xff760000 0x0 0x1000>;
1328                 rockchip,grf = <&grf>;
1329                 #clock-cells = <1>;
1330                 #reset-cells = <1>;
1331                 assigned-clocks =
1332                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1333                         <&cru PLL_NPLL>,
1334                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1335                         <&cru PCLK_PERIHP>,
1336                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1337                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1338                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1339                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1340                         <&cru ACLK_GIC_PRE>,
1341                         <&cru PCLK_DDR>;
1342                 assigned-clock-rates =
1343                          <594000000>,  <800000000>,
1344                         <1000000000>,
1345                          <150000000>,   <75000000>,
1346                           <37500000>,
1347                          <100000000>,  <100000000>,
1348                           <50000000>, <600000000>,
1349                          <100000000>,   <50000000>,
1350                          <400000000>, <400000000>,
1351                          <200000000>,
1352                          <200000000>;
1353         };
1354
1355         grf: syscon@ff770000 {
1356                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1357                 reg = <0x0 0xff770000 0x0 0x10000>;
1358                 #address-cells = <1>;
1359                 #size-cells = <1>;
1360
1361                 io_domains: io-domains {
1362                         compatible = "rockchip,rk3399-io-voltage-domain";
1363                         status = "disabled";
1364                 };
1365
1366                 u2phy0: usb2-phy@e450 {
1367                         compatible = "rockchip,rk3399-usb2phy";
1368                         reg = <0xe450 0x10>;
1369                         clocks = <&cru SCLK_USB2PHY0_REF>;
1370                         clock-names = "phyclk";
1371                         #clock-cells = <0>;
1372                         clock-output-names = "clk_usbphy0_480m";
1373                         status = "disabled";
1374
1375                         u2phy0_host: host-port {
1376                                 #phy-cells = <0>;
1377                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1378                                 interrupt-names = "linestate";
1379                                 status = "disabled";
1380                         };
1381
1382                         u2phy0_otg: otg-port {
1383                                 #phy-cells = <0>;
1384                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1385                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1386                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1387                                 interrupt-names = "otg-bvalid", "otg-id",
1388                                                   "linestate";
1389                                 status = "disabled";
1390                         };
1391                 };
1392
1393                 u2phy1: usb2-phy@e460 {
1394                         compatible = "rockchip,rk3399-usb2phy";
1395                         reg = <0xe460 0x10>;
1396                         clocks = <&cru SCLK_USB2PHY1_REF>;
1397                         clock-names = "phyclk";
1398                         #clock-cells = <0>;
1399                         clock-output-names = "clk_usbphy1_480m";
1400                         status = "disabled";
1401
1402                         u2phy1_host: host-port {
1403                                 #phy-cells = <0>;
1404                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1405                                 interrupt-names = "linestate";
1406                                 status = "disabled";
1407                         };
1408
1409                         u2phy1_otg: otg-port {
1410                                 #phy-cells = <0>;
1411                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1412                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1413                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1414                                 interrupt-names = "otg-bvalid", "otg-id",
1415                                                   "linestate";
1416                                 status = "disabled";
1417                         };
1418                 };
1419
1420                 emmc_phy: phy@f780 {
1421                         compatible = "rockchip,rk3399-emmc-phy";
1422                         reg = <0xf780 0x24>;
1423                         clocks = <&sdhci>;
1424                         clock-names = "emmcclk";
1425                         #phy-cells = <0>;
1426                         status = "disabled";
1427                 };
1428
1429                 pcie_phy: pcie-phy {
1430                         compatible = "rockchip,rk3399-pcie-phy";
1431                         clocks = <&cru SCLK_PCIEPHY_REF>;
1432                         clock-names = "refclk";
1433                         #phy-cells = <1>;
1434                         resets = <&cru SRST_PCIEPHY>;
1435                         reset-names = "phy";
1436                         status = "disabled";
1437                 };
1438         };
1439
1440         tcphy0: phy@ff7c0000 {
1441                 compatible = "rockchip,rk3399-typec-phy";
1442                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1443                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1444                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1445                 clock-names = "tcpdcore", "tcpdphy-ref";
1446                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1447                 assigned-clock-rates = <50000000>;
1448                 power-domains = <&power RK3399_PD_TCPD0>;
1449                 resets = <&cru SRST_UPHY0>,
1450                          <&cru SRST_UPHY0_PIPE_L00>,
1451                          <&cru SRST_P_UPHY0_TCPHY>;
1452                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1453                 rockchip,grf = <&grf>;
1454                 status = "disabled";
1455
1456                 tcphy0_dp: dp-port {
1457                         #phy-cells = <0>;
1458                 };
1459
1460                 tcphy0_usb3: usb3-port {
1461                         #phy-cells = <0>;
1462                 };
1463         };
1464
1465         tcphy1: phy@ff800000 {
1466                 compatible = "rockchip,rk3399-typec-phy";
1467                 reg = <0x0 0xff800000 0x0 0x40000>;
1468                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1469                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1470                 clock-names = "tcpdcore", "tcpdphy-ref";
1471                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1472                 assigned-clock-rates = <50000000>;
1473                 power-domains = <&power RK3399_PD_TCPD1>;
1474                 resets = <&cru SRST_UPHY1>,
1475                          <&cru SRST_UPHY1_PIPE_L00>,
1476                          <&cru SRST_P_UPHY1_TCPHY>;
1477                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1478                 rockchip,grf = <&grf>;
1479                 status = "disabled";
1480
1481                 tcphy1_dp: dp-port {
1482                         #phy-cells = <0>;
1483                 };
1484
1485                 tcphy1_usb3: usb3-port {
1486                         #phy-cells = <0>;
1487                 };
1488         };
1489
1490         watchdog@ff848000 {
1491                 compatible = "snps,dw-wdt";
1492                 reg = <0x0 0xff848000 0x0 0x100>;
1493                 clocks = <&cru PCLK_WDT>;
1494                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1495         };
1496
1497         rktimer: rktimer@ff850000 {
1498                 compatible = "rockchip,rk3399-timer";
1499                 reg = <0x0 0xff850000 0x0 0x1000>;
1500                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1501                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1502                 clock-names = "pclk", "timer";
1503         };
1504
1505         spdif: spdif@ff870000 {
1506                 compatible = "rockchip,rk3399-spdif";
1507                 reg = <0x0 0xff870000 0x0 0x1000>;
1508                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1509                 dmas = <&dmac_bus 7>;
1510                 dma-names = "tx";
1511                 clock-names = "mclk", "hclk";
1512                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1513                 pinctrl-names = "default";
1514                 pinctrl-0 = <&spdif_bus>;
1515                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1516                 #sound-dai-cells = <0>;
1517                 status = "disabled";
1518         };
1519
1520         i2s0: i2s@ff880000 {
1521                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1522                 reg = <0x0 0xff880000 0x0 0x1000>;
1523                 rockchip,grf = <&grf>;
1524                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1525                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1526                 dma-names = "tx", "rx";
1527                 clock-names = "i2s_clk", "i2s_hclk";
1528                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1529                 pinctrl-names = "default";
1530                 pinctrl-0 = <&i2s0_8ch_bus>;
1531                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1532                 #sound-dai-cells = <0>;
1533                 status = "disabled";
1534         };
1535
1536         i2s1: i2s@ff890000 {
1537                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1538                 reg = <0x0 0xff890000 0x0 0x1000>;
1539                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1540                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1541                 dma-names = "tx", "rx";
1542                 clock-names = "i2s_clk", "i2s_hclk";
1543                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1544                 pinctrl-names = "default";
1545                 pinctrl-0 = <&i2s1_2ch_bus>;
1546                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1547                 #sound-dai-cells = <0>;
1548                 status = "disabled";
1549         };
1550
1551         i2s2: i2s@ff8a0000 {
1552                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1553                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1554                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1555                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1556                 dma-names = "tx", "rx";
1557                 clock-names = "i2s_clk", "i2s_hclk";
1558                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1559                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1560                 #sound-dai-cells = <0>;
1561                 status = "disabled";
1562         };
1563
1564         vopl: vop@ff8f0000 {
1565                 compatible = "rockchip,rk3399-vop-lit";
1566                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1567                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1568                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1569                 assigned-clock-rates = <400000000>, <100000000>;
1570                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1571                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1572                 iommus = <&vopl_mmu>;
1573                 power-domains = <&power RK3399_PD_VOPL>;
1574                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1575                 reset-names = "axi", "ahb", "dclk";
1576                 status = "disabled";
1577
1578                 vopl_out: port {
1579                         #address-cells = <1>;
1580                         #size-cells = <0>;
1581
1582                         vopl_out_mipi: endpoint@0 {
1583                                 reg = <0>;
1584                                 remote-endpoint = <&mipi_in_vopl>;
1585                         };
1586
1587                         vopl_out_edp: endpoint@1 {
1588                                 reg = <1>;
1589                                 remote-endpoint = <&edp_in_vopl>;
1590                         };
1591
1592                         vopl_out_hdmi: endpoint@2 {
1593                                 reg = <2>;
1594                                 remote-endpoint = <&hdmi_in_vopl>;
1595                         };
1596
1597                         vopl_out_mipi1: endpoint@3 {
1598                                 reg = <3>;
1599                                 remote-endpoint = <&mipi1_in_vopl>;
1600                         };
1601
1602                         vopl_out_dp: endpoint@4 {
1603                                 reg = <4>;
1604                                 remote-endpoint = <&dp_in_vopl>;
1605                         };
1606                 };
1607         };
1608
1609         vopl_mmu: iommu@ff8f3f00 {
1610                 compatible = "rockchip,iommu";
1611                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1612                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1613                 interrupt-names = "vopl_mmu";
1614                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1615                 clock-names = "aclk", "iface";
1616                 power-domains = <&power RK3399_PD_VOPL>;
1617                 #iommu-cells = <0>;
1618                 status = "disabled";
1619         };
1620
1621         vopb: vop@ff900000 {
1622                 compatible = "rockchip,rk3399-vop-big";
1623                 reg = <0x0 0xff900000 0x0 0x3efc>;
1624                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1625                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1626                 assigned-clock-rates = <400000000>, <100000000>;
1627                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1628                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1629                 iommus = <&vopb_mmu>;
1630                 power-domains = <&power RK3399_PD_VOPB>;
1631                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1632                 reset-names = "axi", "ahb", "dclk";
1633                 status = "disabled";
1634
1635                 vopb_out: port {
1636                         #address-cells = <1>;
1637                         #size-cells = <0>;
1638
1639                         vopb_out_edp: endpoint@0 {
1640                                 reg = <0>;
1641                                 remote-endpoint = <&edp_in_vopb>;
1642                         };
1643
1644                         vopb_out_mipi: endpoint@1 {
1645                                 reg = <1>;
1646                                 remote-endpoint = <&mipi_in_vopb>;
1647                         };
1648
1649                         vopb_out_hdmi: endpoint@2 {
1650                                 reg = <2>;
1651                                 remote-endpoint = <&hdmi_in_vopb>;
1652                         };
1653
1654                         vopb_out_mipi1: endpoint@3 {
1655                                 reg = <3>;
1656                                 remote-endpoint = <&mipi1_in_vopb>;
1657                         };
1658
1659                         vopb_out_dp: endpoint@4 {
1660                                 reg = <4>;
1661                                 remote-endpoint = <&dp_in_vopb>;
1662                         };
1663                 };
1664         };
1665
1666         vopb_mmu: iommu@ff903f00 {
1667                 compatible = "rockchip,iommu";
1668                 reg = <0x0 0xff903f00 0x0 0x100>;
1669                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1670                 interrupt-names = "vopb_mmu";
1671                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1672                 clock-names = "aclk", "iface";
1673                 power-domains = <&power RK3399_PD_VOPB>;
1674                 #iommu-cells = <0>;
1675                 status = "disabled";
1676         };
1677
1678         isp0_mmu: iommu@ff914000 {
1679                 compatible = "rockchip,iommu";
1680                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1681                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1682                 interrupt-names = "isp0_mmu";
1683                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1684                 clock-names = "aclk", "iface";
1685                 #iommu-cells = <0>;
1686                 rockchip,disable-mmu-reset;
1687                 status = "disabled";
1688         };
1689
1690         isp1_mmu: iommu@ff924000 {
1691                 compatible = "rockchip,iommu";
1692                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1693                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1694                 interrupt-names = "isp1_mmu";
1695                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1696                 clock-names = "aclk", "iface";
1697                 #iommu-cells = <0>;
1698                 rockchip,disable-mmu-reset;
1699                 status = "disabled";
1700         };
1701
1702         hdmi_sound: hdmi-sound {
1703                 compatible = "simple-audio-card";
1704                 simple-audio-card,format = "i2s";
1705                 simple-audio-card,mclk-fs = <256>;
1706                 simple-audio-card,name = "hdmi-sound";
1707                 status = "disabled";
1708
1709                 simple-audio-card,cpu {
1710                         sound-dai = <&i2s2>;
1711                 };
1712                 simple-audio-card,codec {
1713                         sound-dai = <&hdmi>;
1714                 };
1715         };
1716
1717         hdmi: hdmi@ff940000 {
1718                 compatible = "rockchip,rk3399-dw-hdmi";
1719                 reg = <0x0 0xff940000 0x0 0x20000>;
1720                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1721                 clocks = <&cru PCLK_HDMI_CTRL>,
1722                          <&cru SCLK_HDMI_SFR>,
1723                          <&cru PLL_VPLL>,
1724                          <&cru PCLK_VIO_GRF>,
1725                          <&cru SCLK_HDMI_CEC>;
1726                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1727                 power-domains = <&power RK3399_PD_HDCP>;
1728                 reg-io-width = <4>;
1729                 rockchip,grf = <&grf>;
1730                 #sound-dai-cells = <0>;
1731                 status = "disabled";
1732
1733                 ports {
1734                         hdmi_in: port {
1735                                 #address-cells = <1>;
1736                                 #size-cells = <0>;
1737
1738                                 hdmi_in_vopb: endpoint@0 {
1739                                         reg = <0>;
1740                                         remote-endpoint = <&vopb_out_hdmi>;
1741                                 };
1742                                 hdmi_in_vopl: endpoint@1 {
1743                                         reg = <1>;
1744                                         remote-endpoint = <&vopl_out_hdmi>;
1745                                 };
1746                         };
1747                 };
1748         };
1749
1750         mipi_dsi: mipi@ff960000 {
1751                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1752                 reg = <0x0 0xff960000 0x0 0x8000>;
1753                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1754                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1755                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1756                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1757                 power-domains = <&power RK3399_PD_VIO>;
1758                 resets = <&cru SRST_P_MIPI_DSI0>;
1759                 reset-names = "apb";
1760                 rockchip,grf = <&grf>;
1761                 #address-cells = <1>;
1762                 #size-cells = <0>;
1763                 status = "disabled";
1764
1765                 ports {
1766                         #address-cells = <1>;
1767                         #size-cells = <0>;
1768
1769                         mipi_in: port@0 {
1770                                 reg = <0>;
1771                                 #address-cells = <1>;
1772                                 #size-cells = <0>;
1773
1774                                 mipi_in_vopb: endpoint@0 {
1775                                         reg = <0>;
1776                                         remote-endpoint = <&vopb_out_mipi>;
1777                                 };
1778                                 mipi_in_vopl: endpoint@1 {
1779                                         reg = <1>;
1780                                         remote-endpoint = <&vopl_out_mipi>;
1781                                 };
1782                         };
1783                 };
1784         };
1785
1786         mipi_dsi1: mipi@ff968000 {
1787                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1788                 reg = <0x0 0xff968000 0x0 0x8000>;
1789                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1790                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1791                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1792                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1793                 power-domains = <&power RK3399_PD_VIO>;
1794                 resets = <&cru SRST_P_MIPI_DSI1>;
1795                 reset-names = "apb";
1796                 rockchip,grf = <&grf>;
1797                 #address-cells = <1>;
1798                 #size-cells = <0>;
1799                 status = "disabled";
1800
1801                 ports {
1802                         #address-cells = <1>;
1803                         #size-cells = <0>;
1804
1805                         mipi1_in: port@0 {
1806                                 reg = <0>;
1807                                 #address-cells = <1>;
1808                                 #size-cells = <0>;
1809
1810                                 mipi1_in_vopb: endpoint@0 {
1811                                         reg = <0>;
1812                                         remote-endpoint = <&vopb_out_mipi1>;
1813                                 };
1814
1815                                 mipi1_in_vopl: endpoint@1 {
1816                                         reg = <1>;
1817                                         remote-endpoint = <&vopl_out_mipi1>;
1818                                 };
1819                         };
1820                 };
1821         };
1822
1823         edp: edp@ff970000 {
1824                 compatible = "rockchip,rk3399-edp";
1825                 reg = <0x0 0xff970000 0x0 0x8000>;
1826                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1827                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1828                 clock-names = "dp", "pclk", "grf";
1829                 pinctrl-names = "default";
1830                 pinctrl-0 = <&edp_hpd>;
1831                 power-domains = <&power RK3399_PD_EDP>;
1832                 resets = <&cru SRST_P_EDP_CTRL>;
1833                 reset-names = "dp";
1834                 rockchip,grf = <&grf>;
1835                 status = "disabled";
1836
1837                 ports {
1838                         #address-cells = <1>;
1839                         #size-cells = <0>;
1840                         edp_in: port@0 {
1841                                 reg = <0>;
1842                                 #address-cells = <1>;
1843                                 #size-cells = <0>;
1844
1845                                 edp_in_vopb: endpoint@0 {
1846                                         reg = <0>;
1847                                         remote-endpoint = <&vopb_out_edp>;
1848                                 };
1849
1850                                 edp_in_vopl: endpoint@1 {
1851                                         reg = <1>;
1852                                         remote-endpoint = <&vopl_out_edp>;
1853                                 };
1854                         };
1855                 };
1856         };
1857
1858         gpu: gpu@ff9a0000 {
1859                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1860                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1861                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1862                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1863                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1864                 interrupt-names = "gpu", "job", "mmu";
1865                 clocks = <&cru ACLK_GPU>;
1866                 power-domains = <&power RK3399_PD_GPU>;
1867                 status = "disabled";
1868         };
1869
1870         pinctrl: pinctrl {
1871                 compatible = "rockchip,rk3399-pinctrl";
1872                 rockchip,grf = <&grf>;
1873                 rockchip,pmu = <&pmugrf>;
1874                 #address-cells = <2>;
1875                 #size-cells = <2>;
1876                 ranges;
1877
1878                 gpio0: gpio0@ff720000 {
1879                         compatible = "rockchip,gpio-bank";
1880                         reg = <0x0 0xff720000 0x0 0x100>;
1881                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1882                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1883
1884                         gpio-controller;
1885                         #gpio-cells = <0x2>;
1886
1887                         interrupt-controller;
1888                         #interrupt-cells = <0x2>;
1889                 };
1890
1891                 gpio1: gpio1@ff730000 {
1892                         compatible = "rockchip,gpio-bank";
1893                         reg = <0x0 0xff730000 0x0 0x100>;
1894                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1895                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1896
1897                         gpio-controller;
1898                         #gpio-cells = <0x2>;
1899
1900                         interrupt-controller;
1901                         #interrupt-cells = <0x2>;
1902                 };
1903
1904                 gpio2: gpio2@ff780000 {
1905                         compatible = "rockchip,gpio-bank";
1906                         reg = <0x0 0xff780000 0x0 0x100>;
1907                         clocks = <&cru PCLK_GPIO2>;
1908                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1909
1910                         gpio-controller;
1911                         #gpio-cells = <0x2>;
1912
1913                         interrupt-controller;
1914                         #interrupt-cells = <0x2>;
1915                 };
1916
1917                 gpio3: gpio3@ff788000 {
1918                         compatible = "rockchip,gpio-bank";
1919                         reg = <0x0 0xff788000 0x0 0x100>;
1920                         clocks = <&cru PCLK_GPIO3>;
1921                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1922
1923                         gpio-controller;
1924                         #gpio-cells = <0x2>;
1925
1926                         interrupt-controller;
1927                         #interrupt-cells = <0x2>;
1928                 };
1929
1930                 gpio4: gpio4@ff790000 {
1931                         compatible = "rockchip,gpio-bank";
1932                         reg = <0x0 0xff790000 0x0 0x100>;
1933                         clocks = <&cru PCLK_GPIO4>;
1934                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1935
1936                         gpio-controller;
1937                         #gpio-cells = <0x2>;
1938
1939                         interrupt-controller;
1940                         #interrupt-cells = <0x2>;
1941                 };
1942
1943                 pcfg_pull_up: pcfg-pull-up {
1944                         bias-pull-up;
1945                 };
1946
1947                 pcfg_pull_down: pcfg-pull-down {
1948                         bias-pull-down;
1949                 };
1950
1951                 pcfg_pull_none: pcfg-pull-none {
1952                         bias-disable;
1953                 };
1954
1955                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1956                         bias-disable;
1957                         drive-strength = <12>;
1958                 };
1959
1960                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1961                         bias-disable;
1962                         drive-strength = <13>;
1963                 };
1964
1965                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1966                         bias-disable;
1967                         drive-strength = <18>;
1968                 };
1969
1970                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1971                         bias-disable;
1972                         drive-strength = <20>;
1973                 };
1974
1975                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1976                         bias-pull-up;
1977                         drive-strength = <2>;
1978                 };
1979
1980                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1981                         bias-pull-up;
1982                         drive-strength = <8>;
1983                 };
1984
1985                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1986                         bias-pull-up;
1987                         drive-strength = <18>;
1988                 };
1989
1990                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1991                         bias-pull-up;
1992                         drive-strength = <20>;
1993                 };
1994
1995                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1996                         bias-pull-down;
1997                         drive-strength = <4>;
1998                 };
1999
2000                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2001                         bias-pull-down;
2002                         drive-strength = <8>;
2003                 };
2004
2005                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2006                         bias-pull-down;
2007                         drive-strength = <12>;
2008                 };
2009
2010                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2011                         bias-pull-down;
2012                         drive-strength = <18>;
2013                 };
2014
2015                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2016                         bias-pull-down;
2017                         drive-strength = <20>;
2018                 };
2019
2020                 pcfg_output_high: pcfg-output-high {
2021                         output-high;
2022                 };
2023
2024                 pcfg_output_low: pcfg-output-low {
2025                         output-low;
2026                 };
2027
2028                 clock {
2029                         clk_32k: clk-32k {
2030                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
2031                         };
2032                 };
2033
2034                 edp {
2035                         edp_hpd: edp-hpd {
2036                                 rockchip,pins =
2037                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2038                         };
2039                 };
2040
2041                 gmac {
2042                         rgmii_pins: rgmii-pins {
2043                                 rockchip,pins =
2044                                         /* mac_txclk */
2045                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2046                                         /* mac_rxclk */
2047                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2048                                         /* mac_mdio */
2049                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2050                                         /* mac_txen */
2051                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2052                                         /* mac_clk */
2053                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2054                                         /* mac_rxdv */
2055                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2056                                         /* mac_mdc */
2057                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2058                                         /* mac_rxd1 */
2059                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2060                                         /* mac_rxd0 */
2061                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2062                                         /* mac_txd1 */
2063                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2064                                         /* mac_txd0 */
2065                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2066                                         /* mac_rxd3 */
2067                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2068                                         /* mac_rxd2 */
2069                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2070                                         /* mac_txd3 */
2071                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2072                                         /* mac_txd2 */
2073                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2074                         };
2075
2076                         rmii_pins: rmii-pins {
2077                                 rockchip,pins =
2078                                         /* mac_mdio */
2079                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2080                                         /* mac_txen */
2081                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2082                                         /* mac_clk */
2083                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2084                                         /* mac_rxer */
2085                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2086                                         /* mac_rxdv */
2087                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2088                                         /* mac_mdc */
2089                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2090                                         /* mac_rxd1 */
2091                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2092                                         /* mac_rxd0 */
2093                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2094                                         /* mac_txd1 */
2095                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2096                                         /* mac_txd0 */
2097                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2098                         };
2099                 };
2100
2101                 i2c0 {
2102                         i2c0_xfer: i2c0-xfer {
2103                                 rockchip,pins =
2104                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2105                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2106                         };
2107                 };
2108
2109                 i2c1 {
2110                         i2c1_xfer: i2c1-xfer {
2111                                 rockchip,pins =
2112                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2113                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2114                         };
2115                 };
2116
2117                 i2c2 {
2118                         i2c2_xfer: i2c2-xfer {
2119                                 rockchip,pins =
2120                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2121                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2122                         };
2123                 };
2124
2125                 i2c3 {
2126                         i2c3_xfer: i2c3-xfer {
2127                                 rockchip,pins =
2128                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2129                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2130                         };
2131                 };
2132
2133                 i2c4 {
2134                         i2c4_xfer: i2c4-xfer {
2135                                 rockchip,pins =
2136                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2137                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2138                         };
2139                 };
2140
2141                 i2c5 {
2142                         i2c5_xfer: i2c5-xfer {
2143                                 rockchip,pins =
2144                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2145                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2146                         };
2147                 };
2148
2149                 i2c6 {
2150                         i2c6_xfer: i2c6-xfer {
2151                                 rockchip,pins =
2152                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2153                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2154                         };
2155                 };
2156
2157                 i2c7 {
2158                         i2c7_xfer: i2c7-xfer {
2159                                 rockchip,pins =
2160                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2161                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2162                         };
2163                 };
2164
2165                 i2c8 {
2166                         i2c8_xfer: i2c8-xfer {
2167                                 rockchip,pins =
2168                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2169                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2170                         };
2171                 };
2172
2173                 i2s0 {
2174                         i2s0_2ch_bus: i2s0-2ch-bus {
2175                                 rockchip,pins =
2176                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2177                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2178                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2179                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2180                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2181                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2182                         };
2183
2184                         i2s0_8ch_bus: i2s0-8ch-bus {
2185                                 rockchip,pins =
2186                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2187                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2188                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2189                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2190                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2191                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2192                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2193                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2194                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2195                         };
2196                 };
2197
2198                 i2s1 {
2199                         i2s1_2ch_bus: i2s1-2ch-bus {
2200                                 rockchip,pins =
2201                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2202                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2203                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2204                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2205                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2206                         };
2207                 };
2208
2209                 sdio0 {
2210                         sdio0_bus1: sdio0-bus1 {
2211                                 rockchip,pins =
2212                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2213                         };
2214
2215                         sdio0_bus4: sdio0-bus4 {
2216                                 rockchip,pins =
2217                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2218                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2219                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2220                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2221                         };
2222
2223                         sdio0_cmd: sdio0-cmd {
2224                                 rockchip,pins =
2225                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2226                         };
2227
2228                         sdio0_clk: sdio0-clk {
2229                                 rockchip,pins =
2230                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2231                         };
2232
2233                         sdio0_cd: sdio0-cd {
2234                                 rockchip,pins =
2235                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2236                         };
2237
2238                         sdio0_pwr: sdio0-pwr {
2239                                 rockchip,pins =
2240                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2241                         };
2242
2243                         sdio0_bkpwr: sdio0-bkpwr {
2244                                 rockchip,pins =
2245                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2246                         };
2247
2248                         sdio0_wp: sdio0-wp {
2249                                 rockchip,pins =
2250                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2251                         };
2252
2253                         sdio0_int: sdio0-int {
2254                                 rockchip,pins =
2255                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2256                         };
2257                 };
2258
2259                 sdmmc {
2260                         sdmmc_bus1: sdmmc-bus1 {
2261                                 rockchip,pins =
2262                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2263                         };
2264
2265                         sdmmc_bus4: sdmmc-bus4 {
2266                                 rockchip,pins =
2267                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2268                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2269                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2270                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2271                         };
2272
2273                         sdmmc_clk: sdmmc-clk {
2274                                 rockchip,pins =
2275                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2276                         };
2277
2278                         sdmmc_cmd: sdmmc-cmd {
2279                                 rockchip,pins =
2280                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2281                         };
2282
2283                         sdmmc_cd: sdmmc-cd {
2284                                 rockchip,pins =
2285                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2286                         };
2287
2288                         sdmmc_wp: sdmmc-wp {
2289                                 rockchip,pins =
2290                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2291                         };
2292                 };
2293
2294                 sleep {
2295                         ap_pwroff: ap-pwroff {
2296                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2297                         };
2298
2299                         ddrio_pwroff: ddrio-pwroff {
2300                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2301                         };
2302                 };
2303
2304                 spdif {
2305                         spdif_bus: spdif-bus {
2306                                 rockchip,pins =
2307                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2308                         };
2309
2310                         spdif_bus_1: spdif-bus-1 {
2311                                 rockchip,pins =
2312                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2313                         };
2314                 };
2315
2316                 spi0 {
2317                         spi0_clk: spi0-clk {
2318                                 rockchip,pins =
2319                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2320                         };
2321                         spi0_cs0: spi0-cs0 {
2322                                 rockchip,pins =
2323                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2324                         };
2325                         spi0_cs1: spi0-cs1 {
2326                                 rockchip,pins =
2327                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2328                         };
2329                         spi0_tx: spi0-tx {
2330                                 rockchip,pins =
2331                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2332                         };
2333                         spi0_rx: spi0-rx {
2334                                 rockchip,pins =
2335                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2336                         };
2337                 };
2338
2339                 spi1 {
2340                         spi1_clk: spi1-clk {
2341                                 rockchip,pins =
2342                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2343                         };
2344                         spi1_cs0: spi1-cs0 {
2345                                 rockchip,pins =
2346                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2347                         };
2348                         spi1_rx: spi1-rx {
2349                                 rockchip,pins =
2350                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2351                         };
2352                         spi1_tx: spi1-tx {
2353                                 rockchip,pins =
2354                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2355                         };
2356                 };
2357
2358                 spi2 {
2359                         spi2_clk: spi2-clk {
2360                                 rockchip,pins =
2361                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2362                         };
2363                         spi2_cs0: spi2-cs0 {
2364                                 rockchip,pins =
2365                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2366                         };
2367                         spi2_rx: spi2-rx {
2368                                 rockchip,pins =
2369                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2370                         };
2371                         spi2_tx: spi2-tx {
2372                                 rockchip,pins =
2373                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2374                         };
2375                 };
2376
2377                 spi3 {
2378                         spi3_clk: spi3-clk {
2379                                 rockchip,pins =
2380                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2381                         };
2382                         spi3_cs0: spi3-cs0 {
2383                                 rockchip,pins =
2384                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2385                         };
2386                         spi3_rx: spi3-rx {
2387                                 rockchip,pins =
2388                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2389                         };
2390                         spi3_tx: spi3-tx {
2391                                 rockchip,pins =
2392                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2393                         };
2394                 };
2395
2396                 spi4 {
2397                         spi4_clk: spi4-clk {
2398                                 rockchip,pins =
2399                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2400                         };
2401                         spi4_cs0: spi4-cs0 {
2402                                 rockchip,pins =
2403                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2404                         };
2405                         spi4_rx: spi4-rx {
2406                                 rockchip,pins =
2407                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2408                         };
2409                         spi4_tx: spi4-tx {
2410                                 rockchip,pins =
2411                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2412                         };
2413                 };
2414
2415                 spi5 {
2416                         spi5_clk: spi5-clk {
2417                                 rockchip,pins =
2418                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2419                         };
2420                         spi5_cs0: spi5-cs0 {
2421                                 rockchip,pins =
2422                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2423                         };
2424                         spi5_rx: spi5-rx {
2425                                 rockchip,pins =
2426                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2427                         };
2428                         spi5_tx: spi5-tx {
2429                                 rockchip,pins =
2430                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2431                         };
2432                 };
2433
2434                 testclk {
2435                         test_clkout0: test-clkout0 {
2436                                 rockchip,pins =
2437                                         <0 0 RK_FUNC_1 &pcfg_pull_none>;
2438                         };
2439
2440                         test_clkout1: test-clkout1 {
2441                                 rockchip,pins =
2442                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
2443                         };
2444
2445                         test_clkout2: test-clkout2 {
2446                                 rockchip,pins =
2447                                         <0 8 RK_FUNC_3 &pcfg_pull_none>;
2448                         };
2449                 };
2450
2451                 tsadc {
2452                         otp_gpio: otp-gpio {
2453                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2454                         };
2455
2456                         otp_out: otp-out {
2457                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2458                         };
2459                 };
2460
2461                 uart0 {
2462                         uart0_xfer: uart0-xfer {
2463                                 rockchip,pins =
2464                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2465                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2466                         };
2467
2468                         uart0_cts: uart0-cts {
2469                                 rockchip,pins =
2470                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2471                         };
2472
2473                         uart0_rts: uart0-rts {
2474                                 rockchip,pins =
2475                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2476                         };
2477                 };
2478
2479                 uart1 {
2480                         uart1_xfer: uart1-xfer {
2481                                 rockchip,pins =
2482                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2483                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2484                         };
2485                 };
2486
2487                 uart2a {
2488                         uart2a_xfer: uart2a-xfer {
2489                                 rockchip,pins =
2490                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2491                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2492                         };
2493                 };
2494
2495                 uart2b {
2496                         uart2b_xfer: uart2b-xfer {
2497                                 rockchip,pins =
2498                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2499                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2500                         };
2501                 };
2502
2503                 uart2c {
2504                         uart2c_xfer: uart2c-xfer {
2505                                 rockchip,pins =
2506                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2507                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2508                         };
2509                 };
2510
2511                 uart3 {
2512                         uart3_xfer: uart3-xfer {
2513                                 rockchip,pins =
2514                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2515                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2516                         };
2517
2518                         uart3_cts: uart3-cts {
2519                                 rockchip,pins =
2520                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2521                         };
2522
2523                         uart3_rts: uart3-rts {
2524                                 rockchip,pins =
2525                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2526                         };
2527                 };
2528
2529                 uart4 {
2530                         uart4_xfer: uart4-xfer {
2531                                 rockchip,pins =
2532                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2533                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2534                         };
2535                 };
2536
2537                 uarthdcp {
2538                         uarthdcp_xfer: uarthdcp-xfer {
2539                                 rockchip,pins =
2540                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2541                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2542                         };
2543                 };
2544
2545                 pwm0 {
2546                         pwm0_pin: pwm0-pin {
2547                                 rockchip,pins =
2548                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2549                         };
2550
2551                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2552                                 rockchip,pins =
2553                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
2554                         };
2555
2556                         vop0_pwm_pin: vop0-pwm-pin {
2557                                 rockchip,pins =
2558                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2559                         };
2560
2561                         vop1_pwm_pin: vop1-pwm-pin {
2562                                 rockchip,pins =
2563                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2564                         };
2565                 };
2566
2567                 pwm1 {
2568                         pwm1_pin: pwm1-pin {
2569                                 rockchip,pins =
2570                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2571                         };
2572
2573                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2574                                 rockchip,pins =
2575                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
2576                         };
2577                 };
2578
2579                 pwm2 {
2580                         pwm2_pin: pwm2-pin {
2581                                 rockchip,pins =
2582                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2583                         };
2584
2585                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2586                                 rockchip,pins =
2587                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
2588                         };
2589                 };
2590
2591                 pwm3a {
2592                         pwm3a_pin: pwm3a-pin {
2593                                 rockchip,pins =
2594                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2595                         };
2596                 };
2597
2598                 pwm3b {
2599                         pwm3b_pin: pwm3b-pin {
2600                                 rockchip,pins =
2601                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2602                         };
2603                 };
2604
2605                 hdmi {
2606                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2607                                 rockchip,pins =
2608                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2609                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2610                         };
2611
2612                         hdmi_cec: hdmi-cec {
2613                                 rockchip,pins =
2614                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2615                         };
2616                 };
2617
2618                 pcie {
2619                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2620                                 rockchip,pins =
2621                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2622                         };
2623
2624                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2625                                 rockchip,pins =
2626                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2627                         };
2628                 };
2629
2630         };
2631 };