Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64...
[muen/linux.git] / arch / arm64 / kernel / cpu_errata.c
1 /*
2  * Contains CPU specific errata definitions
3  *
4  * Copyright (C) 2014 ARM Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/arm-smccc.h>
20 #include <linux/psci.h>
21 #include <linux/types.h>
22 #include <asm/cpu.h>
23 #include <asm/cputype.h>
24 #include <asm/cpufeature.h>
25
26 static bool __maybe_unused
27 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
28 {
29         const struct arm64_midr_revidr *fix;
30         u32 midr = read_cpuid_id(), revidr;
31
32         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
33         if (!is_midr_in_range(midr, &entry->midr_range))
34                 return false;
35
36         midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
37         revidr = read_cpuid(REVIDR_EL1);
38         for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
39                 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
40                         return false;
41
42         return true;
43 }
44
45 static bool __maybe_unused
46 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
47                             int scope)
48 {
49         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50         return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
51 }
52
53 static bool __maybe_unused
54 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
55 {
56         u32 model;
57
58         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
59
60         model = read_cpuid_id();
61         model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
62                  MIDR_ARCHITECTURE_MASK;
63
64         return model == entry->midr_range.model;
65 }
66
67 static bool
68 has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
69                                 int scope)
70 {
71         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
72         return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
73                 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
74 }
75
76 static void
77 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
78 {
79         /* Clear SCTLR_EL1.UCT */
80         config_sctlr_el1(SCTLR_EL1_UCT, 0);
81 }
82
83 atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
84
85 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
86 #include <asm/mmu_context.h>
87 #include <asm/cacheflush.h>
88
89 DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
90
91 #ifdef CONFIG_KVM_INDIRECT_VECTORS
92 extern char __smccc_workaround_1_smc_start[];
93 extern char __smccc_workaround_1_smc_end[];
94
95 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
96                                 const char *hyp_vecs_end)
97 {
98         void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
99         int i;
100
101         for (i = 0; i < SZ_2K; i += 0x80)
102                 memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
103
104         flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
105 }
106
107 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
108                                       const char *hyp_vecs_start,
109                                       const char *hyp_vecs_end)
110 {
111         static DEFINE_SPINLOCK(bp_lock);
112         int cpu, slot = -1;
113
114         spin_lock(&bp_lock);
115         for_each_possible_cpu(cpu) {
116                 if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
117                         slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
118                         break;
119                 }
120         }
121
122         if (slot == -1) {
123                 slot = atomic_inc_return(&arm64_el2_vector_last_slot);
124                 BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
125                 __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
126         }
127
128         __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
129         __this_cpu_write(bp_hardening_data.fn, fn);
130         spin_unlock(&bp_lock);
131 }
132 #else
133 #define __smccc_workaround_1_smc_start          NULL
134 #define __smccc_workaround_1_smc_end            NULL
135
136 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
137                                       const char *hyp_vecs_start,
138                                       const char *hyp_vecs_end)
139 {
140         __this_cpu_write(bp_hardening_data.fn, fn);
141 }
142 #endif  /* CONFIG_KVM_INDIRECT_VECTORS */
143
144 static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
145                                      bp_hardening_cb_t fn,
146                                      const char *hyp_vecs_start,
147                                      const char *hyp_vecs_end)
148 {
149         u64 pfr0;
150
151         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
152                 return;
153
154         pfr0 = read_cpuid(ID_AA64PFR0_EL1);
155         if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
156                 return;
157
158         __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
159 }
160
161 #include <uapi/linux/psci.h>
162 #include <linux/arm-smccc.h>
163 #include <linux/psci.h>
164
165 static void call_smc_arch_workaround_1(void)
166 {
167         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
168 }
169
170 static void call_hvc_arch_workaround_1(void)
171 {
172         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
173 }
174
175 static void qcom_link_stack_sanitization(void)
176 {
177         u64 tmp;
178
179         asm volatile("mov       %0, x30         \n"
180                      ".rept     16              \n"
181                      "bl        . + 4           \n"
182                      ".endr                     \n"
183                      "mov       x30, %0         \n"
184                      : "=&r" (tmp));
185 }
186
187 static void
188 enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
189 {
190         bp_hardening_cb_t cb;
191         void *smccc_start, *smccc_end;
192         struct arm_smccc_res res;
193         u32 midr = read_cpuid_id();
194
195         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
196                 return;
197
198         if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
199                 return;
200
201         switch (psci_ops.conduit) {
202         case PSCI_CONDUIT_HVC:
203                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
204                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
205                 if ((int)res.a0 < 0)
206                         return;
207                 cb = call_hvc_arch_workaround_1;
208                 /* This is a guest, no need to patch KVM vectors */
209                 smccc_start = NULL;
210                 smccc_end = NULL;
211                 break;
212
213         case PSCI_CONDUIT_SMC:
214                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
215                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
216                 if ((int)res.a0 < 0)
217                         return;
218                 cb = call_smc_arch_workaround_1;
219                 smccc_start = __smccc_workaround_1_smc_start;
220                 smccc_end = __smccc_workaround_1_smc_end;
221                 break;
222
223         default:
224                 return;
225         }
226
227         if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
228             ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
229                 cb = qcom_link_stack_sanitization;
230
231         install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
232
233         return;
234 }
235 #endif  /* CONFIG_HARDEN_BRANCH_PREDICTOR */
236
237 #ifdef CONFIG_ARM64_SSBD
238 DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
239
240 int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
241
242 static const struct ssbd_options {
243         const char      *str;
244         int             state;
245 } ssbd_options[] = {
246         { "force-on",   ARM64_SSBD_FORCE_ENABLE, },
247         { "force-off",  ARM64_SSBD_FORCE_DISABLE, },
248         { "kernel",     ARM64_SSBD_KERNEL, },
249 };
250
251 static int __init ssbd_cfg(char *buf)
252 {
253         int i;
254
255         if (!buf || !buf[0])
256                 return -EINVAL;
257
258         for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
259                 int len = strlen(ssbd_options[i].str);
260
261                 if (strncmp(buf, ssbd_options[i].str, len))
262                         continue;
263
264                 ssbd_state = ssbd_options[i].state;
265                 return 0;
266         }
267
268         return -EINVAL;
269 }
270 early_param("ssbd", ssbd_cfg);
271
272 void __init arm64_update_smccc_conduit(struct alt_instr *alt,
273                                        __le32 *origptr, __le32 *updptr,
274                                        int nr_inst)
275 {
276         u32 insn;
277
278         BUG_ON(nr_inst != 1);
279
280         switch (psci_ops.conduit) {
281         case PSCI_CONDUIT_HVC:
282                 insn = aarch64_insn_get_hvc_value();
283                 break;
284         case PSCI_CONDUIT_SMC:
285                 insn = aarch64_insn_get_smc_value();
286                 break;
287         default:
288                 return;
289         }
290
291         *updptr = cpu_to_le32(insn);
292 }
293
294 void __init arm64_enable_wa2_handling(struct alt_instr *alt,
295                                       __le32 *origptr, __le32 *updptr,
296                                       int nr_inst)
297 {
298         BUG_ON(nr_inst != 1);
299         /*
300          * Only allow mitigation on EL1 entry/exit and guest
301          * ARCH_WORKAROUND_2 handling if the SSBD state allows it to
302          * be flipped.
303          */
304         if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
305                 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
306 }
307
308 void arm64_set_ssbd_mitigation(bool state)
309 {
310         switch (psci_ops.conduit) {
311         case PSCI_CONDUIT_HVC:
312                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
313                 break;
314
315         case PSCI_CONDUIT_SMC:
316                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
317                 break;
318
319         default:
320                 WARN_ON_ONCE(1);
321                 break;
322         }
323 }
324
325 static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
326                                     int scope)
327 {
328         struct arm_smccc_res res;
329         bool required = true;
330         s32 val;
331
332         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
333
334         if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
335                 ssbd_state = ARM64_SSBD_UNKNOWN;
336                 return false;
337         }
338
339         switch (psci_ops.conduit) {
340         case PSCI_CONDUIT_HVC:
341                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
342                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
343                 break;
344
345         case PSCI_CONDUIT_SMC:
346                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
347                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
348                 break;
349
350         default:
351                 ssbd_state = ARM64_SSBD_UNKNOWN;
352                 return false;
353         }
354
355         val = (s32)res.a0;
356
357         switch (val) {
358         case SMCCC_RET_NOT_SUPPORTED:
359                 ssbd_state = ARM64_SSBD_UNKNOWN;
360                 return false;
361
362         case SMCCC_RET_NOT_REQUIRED:
363                 pr_info_once("%s mitigation not required\n", entry->desc);
364                 ssbd_state = ARM64_SSBD_MITIGATED;
365                 return false;
366
367         case SMCCC_RET_SUCCESS:
368                 required = true;
369                 break;
370
371         case 1: /* Mitigation not required on this CPU */
372                 required = false;
373                 break;
374
375         default:
376                 WARN_ON(1);
377                 return false;
378         }
379
380         switch (ssbd_state) {
381         case ARM64_SSBD_FORCE_DISABLE:
382                 pr_info_once("%s disabled from command-line\n", entry->desc);
383                 arm64_set_ssbd_mitigation(false);
384                 required = false;
385                 break;
386
387         case ARM64_SSBD_KERNEL:
388                 if (required) {
389                         __this_cpu_write(arm64_ssbd_callback_required, 1);
390                         arm64_set_ssbd_mitigation(true);
391                 }
392                 break;
393
394         case ARM64_SSBD_FORCE_ENABLE:
395                 pr_info_once("%s forced from command-line\n", entry->desc);
396                 arm64_set_ssbd_mitigation(true);
397                 required = true;
398                 break;
399
400         default:
401                 WARN_ON(1);
402                 break;
403         }
404
405         return required;
406 }
407 #endif  /* CONFIG_ARM64_SSBD */
408
409 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)       \
410         .matches = is_affected_midr_range,                      \
411         .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
412
413 #define CAP_MIDR_ALL_VERSIONS(model)                                    \
414         .matches = is_affected_midr_range,                              \
415         .midr_range = MIDR_ALL_VERSIONS(model)
416
417 #define MIDR_FIXED(rev, revidr_mask) \
418         .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
419
420 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)            \
421         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                         \
422         CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
423
424 #define CAP_MIDR_RANGE_LIST(list)                               \
425         .matches = is_affected_midr_range_list,                 \
426         .midr_range_list = list
427
428 /* Errata affecting a range of revisions of  given model variant */
429 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)      \
430         ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
431
432 /* Errata affecting a single variant/revision of a model */
433 #define ERRATA_MIDR_REV(model, var, rev)        \
434         ERRATA_MIDR_RANGE(model, var, rev, var, rev)
435
436 /* Errata affecting all variants/revisions of a given a model */
437 #define ERRATA_MIDR_ALL_VERSIONS(model)                         \
438         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
439         CAP_MIDR_ALL_VERSIONS(model)
440
441 /* Errata affecting a list of midr ranges, with same work around */
442 #define ERRATA_MIDR_RANGE_LIST(midr_list)                       \
443         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
444         CAP_MIDR_RANGE_LIST(midr_list)
445
446 /*
447  * Generic helper for handling capabilties with multiple (match,enable) pairs
448  * of call backs, sharing the same capability bit.
449  * Iterate over each entry to see if at least one matches.
450  */
451 static bool __maybe_unused
452 multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
453 {
454         const struct arm64_cpu_capabilities *caps;
455
456         for (caps = entry->match_list; caps->matches; caps++)
457                 if (caps->matches(caps, scope))
458                         return true;
459
460         return false;
461 }
462
463 /*
464  * Take appropriate action for all matching entries in the shared capability
465  * entry.
466  */
467 static void __maybe_unused
468 multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
469 {
470         const struct arm64_cpu_capabilities *caps;
471
472         for (caps = entry->match_list; caps->matches; caps++)
473                 if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
474                     caps->cpu_enable)
475                         caps->cpu_enable(caps);
476 }
477
478 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
479
480 /*
481  * List of CPUs where we need to issue a psci call to
482  * harden the branch predictor.
483  */
484 static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
485         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
486         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
487         MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
488         MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
489         MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
490         MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
491         MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
492         MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
493         MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
494         {},
495 };
496
497 #endif
498
499 #ifdef CONFIG_HARDEN_EL2_VECTORS
500
501 static const struct midr_range arm64_harden_el2_vectors[] = {
502         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
503         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
504         {},
505 };
506
507 #endif
508
509 const struct arm64_cpu_capabilities arm64_errata[] = {
510 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
511         defined(CONFIG_ARM64_ERRATUM_827319) || \
512         defined(CONFIG_ARM64_ERRATUM_824069)
513         {
514         /* Cortex-A53 r0p[012] */
515                 .desc = "ARM errata 826319, 827319, 824069",
516                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
517                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
518                 .cpu_enable = cpu_enable_cache_maint_trap,
519         },
520 #endif
521 #ifdef CONFIG_ARM64_ERRATUM_819472
522         {
523         /* Cortex-A53 r0p[01] */
524                 .desc = "ARM errata 819472",
525                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
526                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
527                 .cpu_enable = cpu_enable_cache_maint_trap,
528         },
529 #endif
530 #ifdef CONFIG_ARM64_ERRATUM_832075
531         {
532         /* Cortex-A57 r0p0 - r1p2 */
533                 .desc = "ARM erratum 832075",
534                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
535                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
536                                   0, 0,
537                                   1, 2),
538         },
539 #endif
540 #ifdef CONFIG_ARM64_ERRATUM_834220
541         {
542         /* Cortex-A57 r0p0 - r1p2 */
543                 .desc = "ARM erratum 834220",
544                 .capability = ARM64_WORKAROUND_834220,
545                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
546                                   0, 0,
547                                   1, 2),
548         },
549 #endif
550 #ifdef CONFIG_ARM64_ERRATUM_843419
551         {
552         /* Cortex-A53 r0p[01234] */
553                 .desc = "ARM erratum 843419",
554                 .capability = ARM64_WORKAROUND_843419,
555                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
556                 MIDR_FIXED(0x4, BIT(8)),
557         },
558 #endif
559 #ifdef CONFIG_ARM64_ERRATUM_845719
560         {
561         /* Cortex-A53 r0p[01234] */
562                 .desc = "ARM erratum 845719",
563                 .capability = ARM64_WORKAROUND_845719,
564                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
565         },
566 #endif
567 #ifdef CONFIG_CAVIUM_ERRATUM_23154
568         {
569         /* Cavium ThunderX, pass 1.x */
570                 .desc = "Cavium erratum 23154",
571                 .capability = ARM64_WORKAROUND_CAVIUM_23154,
572                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
573         },
574 #endif
575 #ifdef CONFIG_CAVIUM_ERRATUM_27456
576         {
577         /* Cavium ThunderX, T88 pass 1.x - 2.1 */
578                 .desc = "Cavium erratum 27456",
579                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
580                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
581                                   0, 0,
582                                   1, 1),
583         },
584         {
585         /* Cavium ThunderX, T81 pass 1.0 */
586                 .desc = "Cavium erratum 27456",
587                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
588                 ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
589         },
590 #endif
591 #ifdef CONFIG_CAVIUM_ERRATUM_30115
592         {
593         /* Cavium ThunderX, T88 pass 1.x - 2.2 */
594                 .desc = "Cavium erratum 30115",
595                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
596                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
597                                       0, 0,
598                                       1, 2),
599         },
600         {
601         /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
602                 .desc = "Cavium erratum 30115",
603                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
604                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
605         },
606         {
607         /* Cavium ThunderX, T83 pass 1.0 */
608                 .desc = "Cavium erratum 30115",
609                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
610                 ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
611         },
612 #endif
613         {
614                 .desc = "Mismatched cache line size",
615                 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
616                 .matches = has_mismatched_cache_line_size,
617                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
618                 .cpu_enable = cpu_enable_trap_ctr_access,
619         },
620 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
621         {
622                 .desc = "Qualcomm Technologies Falkor erratum 1003",
623                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
624                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
625         },
626         {
627                 .desc = "Qualcomm Technologies Kryo erratum 1003",
628                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
629                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
630                 .midr_range.model = MIDR_QCOM_KRYO,
631                 .matches = is_kryo_midr,
632         },
633 #endif
634 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
635         {
636                 .desc = "Qualcomm Technologies Falkor erratum 1009",
637                 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
638                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
639         },
640 #endif
641 #ifdef CONFIG_ARM64_ERRATUM_858921
642         {
643         /* Cortex-A73 all versions */
644                 .desc = "ARM erratum 858921",
645                 .capability = ARM64_WORKAROUND_858921,
646                 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
647         },
648 #endif
649 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
650         {
651                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
652                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
653                 .cpu_enable = enable_smccc_arch_workaround_1,
654                 ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
655         },
656 #endif
657 #ifdef CONFIG_HARDEN_EL2_VECTORS
658         {
659                 .desc = "EL2 vector hardening",
660                 .capability = ARM64_HARDEN_EL2_VECTORS,
661                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
662                 ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
663         },
664 #endif
665 #ifdef CONFIG_ARM64_SSBD
666         {
667                 .desc = "Speculative Store Bypass Disable",
668                 .capability = ARM64_SSBD,
669                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
670                 .matches = has_ssbd_mitigation,
671         },
672 #endif
673         {
674         }
675 };