arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
[muen/linux.git] / arch / arm64 / kernel / cpufeature.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Contains CPU feature definitions
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  *
7  * A note for the weary kernel hacker: the code here is confusing and hard to
8  * follow! That's partly because it's solving a nasty problem, but also because
9  * there's a little bit of over-abstraction that tends to obscure what's going
10  * on behind a maze of helper functions and macros.
11  *
12  * The basic problem is that hardware folks have started gluing together CPUs
13  * with distinct architectural features; in some cases even creating SoCs where
14  * user-visible instructions are available only on a subset of the available
15  * cores. We try to address this by snapshotting the feature registers of the
16  * boot CPU and comparing these with the feature registers of each secondary
17  * CPU when bringing them up. If there is a mismatch, then we update the
18  * snapshot state to indicate the lowest-common denominator of the feature,
19  * known as the "safe" value. This snapshot state can be queried to view the
20  * "sanitised" value of a feature register.
21  *
22  * The sanitised register values are used to decide which capabilities we
23  * have in the system. These may be in the form of traditional "hwcaps"
24  * advertised to userspace or internal "cpucaps" which are used to configure
25  * things like alternative patching and static keys. While a feature mismatch
26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27  * may prevent a CPU from being onlined at all.
28  *
29  * Some implementation details worth remembering:
30  *
31  * - Mismatched features are *always* sanitised to a "safe" value, which
32  *   usually indicates that the feature is not supported.
33  *
34  * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35  *   warning when onlining an offending CPU and the kernel will be tainted
36  *   with TAINT_CPU_OUT_OF_SPEC.
37  *
38  * - Features marked as FTR_VISIBLE have their sanitised value visible to
39  *   userspace. FTR_VISIBLE features in registers that are only visible
40  *   to EL0 by trapping *must* have a corresponding HWCAP so that late
41  *   onlining of CPUs cannot lead to features disappearing at runtime.
42  *
43  * - A "feature" is typically a 4-bit register field. A "capability" is the
44  *   high-level description derived from the sanitised field value.
45  *
46  * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47  *   scheme for fields in ID registers") to understand when feature fields
48  *   may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49  *
50  * - KVM exposes its own view of the feature registers to guest operating
51  *   systems regardless of FTR_VISIBLE. This is typically driven from the
52  *   sanitised register values to allow virtual CPUs to be migrated between
53  *   arbitrary physical CPUs, but some features not present on the host are
54  *   also advertised and emulated. Look at sys_reg_descs[] for the gory
55  *   details.
56  *
57  * - If the arm64_ftr_bits[] for a register has a missing field, then this
58  *   field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59  *   This is stronger than FTR_HIDDEN and can be used to hide features from
60  *   KVM guests.
61  */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/types.h>
71 #include <linux/mm.h>
72 #include <linux/cpu.h>
73 #include <asm/cpu.h>
74 #include <asm/cpufeature.h>
75 #include <asm/cpu_ops.h>
76 #include <asm/fpsimd.h>
77 #include <asm/mmu_context.h>
78 #include <asm/processor.h>
79 #include <asm/sysreg.h>
80 #include <asm/traps.h>
81 #include <asm/virt.h>
82
83 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
84 static unsigned long elf_hwcap __read_mostly;
85
86 #ifdef CONFIG_COMPAT
87 #define COMPAT_ELF_HWCAP_DEFAULT        \
88                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
89                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
90                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
91                                  COMPAT_HWCAP_LPAE)
92 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
93 unsigned int compat_elf_hwcap2 __read_mostly;
94 #endif
95
96 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
97 EXPORT_SYMBOL(cpu_hwcaps);
98 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
99
100 /* Need also bit for ARM64_CB_PATCH */
101 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
102
103 bool arm64_use_ng_mappings = false;
104 EXPORT_SYMBOL(arm64_use_ng_mappings);
105
106 /*
107  * Flag to indicate if we have computed the system wide
108  * capabilities based on the boot time active CPUs. This
109  * will be used to determine if a new booting CPU should
110  * go through the verification process to make sure that it
111  * supports the system capabilities, without using a hotplug
112  * notifier. This is also used to decide if we could use
113  * the fast path for checking constant CPU caps.
114  */
115 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
116 EXPORT_SYMBOL(arm64_const_caps_ready);
117 static inline void finalize_system_capabilities(void)
118 {
119         static_branch_enable(&arm64_const_caps_ready);
120 }
121
122 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
123 {
124         /* file-wide pr_fmt adds "CPU features: " prefix */
125         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
126         return 0;
127 }
128
129 static struct notifier_block cpu_hwcaps_notifier = {
130         .notifier_call = dump_cpu_hwcaps
131 };
132
133 static int __init register_cpu_hwcaps_dumper(void)
134 {
135         atomic_notifier_chain_register(&panic_notifier_list,
136                                        &cpu_hwcaps_notifier);
137         return 0;
138 }
139 __initcall(register_cpu_hwcaps_dumper);
140
141 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
142 EXPORT_SYMBOL(cpu_hwcap_keys);
143
144 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
145         {                                               \
146                 .sign = SIGNED,                         \
147                 .visible = VISIBLE,                     \
148                 .strict = STRICT,                       \
149                 .type = TYPE,                           \
150                 .shift = SHIFT,                         \
151                 .width = WIDTH,                         \
152                 .safe_val = SAFE_VAL,                   \
153         }
154
155 /* Define a feature with unsigned values */
156 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
158
159 /* Define a feature with a signed value */
160 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
161         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
162
163 #define ARM64_FTR_END                                   \
164         {                                               \
165                 .width = 0,                             \
166         }
167
168 /* meta feature for alternatives */
169 static bool __maybe_unused
170 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
171
172 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
173
174 static bool __system_matches_cap(unsigned int n);
175
176 /*
177  * NOTE: Any changes to the visibility of features should be kept in
178  * sync with the documentation of the CPU feature register ABI.
179  */
180 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
181         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
182         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
183         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
184         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
185         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
187         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
188         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
189         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
191         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
192         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
193         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
194         ARM64_FTR_END,
195 };
196
197 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
198         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
199         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
200         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
204         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
205                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
206         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
207                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
208         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
209         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
210         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
211         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
212                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
213         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
214                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
215         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
216         ARM64_FTR_END,
217 };
218
219 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
222         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
224         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
225                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
228         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
229         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
234         ARM64_FTR_END,
235 };
236
237 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
239         ARM64_FTR_END,
240 };
241
242 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
243         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
244                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
245         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
246                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
247         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
248                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
249         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
250                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
251         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
252                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
253         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
254                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
255         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
256                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
257         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
258                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
259         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
260                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
261         ARM64_FTR_END,
262 };
263
264 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
265         /*
266          * We already refuse to boot CPUs that don't support our configured
267          * page size, so we can only detect mismatches for a page size other
268          * than the one we're currently using. Unfortunately, SoCs like this
269          * exist in the wild so, even though we don't like it, we'll have to go
270          * along with it and treat them as non-strict.
271          */
272         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
273         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
275
276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
277         /* Linux shouldn't care about secure memory */
278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
281         /*
282          * Differing PARange is fine as long as all peripherals and memory are mapped
283          * within the minimum PARange of all CPUs
284          */
285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
286         ARM64_FTR_END,
287 };
288
289 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
296         ARM64_FTR_END,
297 };
298
299 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
302         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
308         ARM64_FTR_END,
309 };
310
311 static const struct arm64_ftr_bits ftr_ctr[] = {
312         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
313         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
314         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
315         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
316         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
317         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
318         /*
319          * Linux can handle differing I-cache policies. Userspace JITs will
320          * make use of *minLine.
321          * If we have differing I-cache policies, report it as the weakest - VIPT.
322          */
323         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
324         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
325         ARM64_FTR_END,
326 };
327
328 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
329         .name           = "SYS_CTR_EL0",
330         .ftr_bits       = ftr_ctr
331 };
332
333 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
334         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
339         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
342         ARM64_FTR_END,
343 };
344
345 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
346         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0),
347         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
351         /*
352          * We can instantiate multiple PMU instances with different levels
353          * of support.
354          */
355         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
358         ARM64_FTR_END,
359 };
360
361 static const struct arm64_ftr_bits ftr_mvfr2[] = {
362         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
363         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
364         ARM64_FTR_END,
365 };
366
367 static const struct arm64_ftr_bits ftr_dczid[] = {
368         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
369         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
370         ARM64_FTR_END,
371 };
372
373 static const struct arm64_ftr_bits ftr_id_isar0[] = {
374         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
375         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
376         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
377         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
378         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
379         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
380         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
381         ARM64_FTR_END,
382 };
383
384 static const struct arm64_ftr_bits ftr_id_isar5[] = {
385         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
386         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
387         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
388         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
389         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
390         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
391         ARM64_FTR_END,
392 };
393
394 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
395         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
396         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
397         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
398         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
399         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
400         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
401         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
402         /*
403          * SpecSEI = 1 indicates that the PE might generate an SError on an
404          * external abort on speculative read. It is safe to assume that an
405          * SError might be generated than it will not be. Hence it has been
406          * classified as FTR_HIGHER_SAFE.
407          */
408         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
409         ARM64_FTR_END,
410 };
411
412 static const struct arm64_ftr_bits ftr_id_isar4[] = {
413         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
414         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
415         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
416         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
417         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
418         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
419         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
420         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
421         ARM64_FTR_END,
422 };
423
424 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
425         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
426         ARM64_FTR_END,
427 };
428
429 static const struct arm64_ftr_bits ftr_id_isar6[] = {
430         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
431         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
432         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
433         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
434         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
435         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
436         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
437         ARM64_FTR_END,
438 };
439
440 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
441         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
442         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
443         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
444         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
445         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
446         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
447         ARM64_FTR_END,
448 };
449
450 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
451         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
452         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
453         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
454         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
455         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
456         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
457         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
458         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
459         ARM64_FTR_END,
460 };
461
462 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
463         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
464         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
465         ARM64_FTR_END,
466 };
467
468 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
469         /* [31:28] TraceFilt */
470         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
471         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
472         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
473         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
474         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
475         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
476         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
477         ARM64_FTR_END,
478 };
479
480 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
481         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
482         ARM64_FTR_END,
483 };
484
485 static const struct arm64_ftr_bits ftr_zcr[] = {
486         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
487                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
488         ARM64_FTR_END,
489 };
490
491 /*
492  * Common ftr bits for a 32bit register with all hidden, strict
493  * attributes, with 4bit feature fields and a default safe value of
494  * 0. Covers the following 32bit registers:
495  * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
496  */
497 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
498         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
499         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
500         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
501         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
502         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
503         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
504         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
505         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
506         ARM64_FTR_END,
507 };
508
509 /* Table for a single 32bit feature value */
510 static const struct arm64_ftr_bits ftr_single32[] = {
511         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
512         ARM64_FTR_END,
513 };
514
515 static const struct arm64_ftr_bits ftr_raz[] = {
516         ARM64_FTR_END,
517 };
518
519 #define ARM64_FTR_REG(id, table) {              \
520         .sys_id = id,                           \
521         .reg =  &(struct arm64_ftr_reg){        \
522                 .name = #id,                    \
523                 .ftr_bits = &((table)[0]),      \
524         }}
525
526 static const struct __ftr_reg_entry {
527         u32                     sys_id;
528         struct arm64_ftr_reg    *reg;
529 } arm64_ftr_regs[] = {
530
531         /* Op1 = 0, CRn = 0, CRm = 1 */
532         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
533         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
534         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
535         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
536         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
537         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
538         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
539
540         /* Op1 = 0, CRn = 0, CRm = 2 */
541         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
542         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
543         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
544         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
545         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
546         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
547         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
548         ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
549
550         /* Op1 = 0, CRn = 0, CRm = 3 */
551         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
552         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
553         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
554         ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
555         ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
556         ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
557
558         /* Op1 = 0, CRn = 0, CRm = 4 */
559         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
560         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
561         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
562
563         /* Op1 = 0, CRn = 0, CRm = 5 */
564         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
565         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
566
567         /* Op1 = 0, CRn = 0, CRm = 6 */
568         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
569         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
570
571         /* Op1 = 0, CRn = 0, CRm = 7 */
572         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
573         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
574         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
575
576         /* Op1 = 0, CRn = 1, CRm = 2 */
577         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
578
579         /* Op1 = 3, CRn = 0, CRm = 0 */
580         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
581         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
582
583         /* Op1 = 3, CRn = 14, CRm = 0 */
584         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
585 };
586
587 static int search_cmp_ftr_reg(const void *id, const void *regp)
588 {
589         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
590 }
591
592 /*
593  * get_arm64_ftr_reg - Lookup a feature register entry using its
594  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
595  * ascending order of sys_id , we use binary search to find a matching
596  * entry.
597  *
598  * returns - Upon success,  matching ftr_reg entry for id.
599  *         - NULL on failure. It is upto the caller to decide
600  *           the impact of a failure.
601  */
602 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
603 {
604         const struct __ftr_reg_entry *ret;
605
606         ret = bsearch((const void *)(unsigned long)sys_id,
607                         arm64_ftr_regs,
608                         ARRAY_SIZE(arm64_ftr_regs),
609                         sizeof(arm64_ftr_regs[0]),
610                         search_cmp_ftr_reg);
611         if (ret)
612                 return ret->reg;
613         return NULL;
614 }
615
616 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
617                                s64 ftr_val)
618 {
619         u64 mask = arm64_ftr_mask(ftrp);
620
621         reg &= ~mask;
622         reg |= (ftr_val << ftrp->shift) & mask;
623         return reg;
624 }
625
626 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
627                                 s64 cur)
628 {
629         s64 ret = 0;
630
631         switch (ftrp->type) {
632         case FTR_EXACT:
633                 ret = ftrp->safe_val;
634                 break;
635         case FTR_LOWER_SAFE:
636                 ret = new < cur ? new : cur;
637                 break;
638         case FTR_HIGHER_OR_ZERO_SAFE:
639                 if (!cur || !new)
640                         break;
641                 /* Fallthrough */
642         case FTR_HIGHER_SAFE:
643                 ret = new > cur ? new : cur;
644                 break;
645         default:
646                 BUG();
647         }
648
649         return ret;
650 }
651
652 static void __init sort_ftr_regs(void)
653 {
654         int i;
655
656         /* Check that the array is sorted so that we can do the binary search */
657         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
658                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
659 }
660
661 /*
662  * Initialise the CPU feature register from Boot CPU values.
663  * Also initiliases the strict_mask for the register.
664  * Any bits that are not covered by an arm64_ftr_bits entry are considered
665  * RES0 for the system-wide value, and must strictly match.
666  */
667 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
668 {
669         u64 val = 0;
670         u64 strict_mask = ~0x0ULL;
671         u64 user_mask = 0;
672         u64 valid_mask = 0;
673
674         const struct arm64_ftr_bits *ftrp;
675         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
676
677         BUG_ON(!reg);
678
679         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
680                 u64 ftr_mask = arm64_ftr_mask(ftrp);
681                 s64 ftr_new = arm64_ftr_value(ftrp, new);
682
683                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
684
685                 valid_mask |= ftr_mask;
686                 if (!ftrp->strict)
687                         strict_mask &= ~ftr_mask;
688                 if (ftrp->visible)
689                         user_mask |= ftr_mask;
690                 else
691                         reg->user_val = arm64_ftr_set_value(ftrp,
692                                                             reg->user_val,
693                                                             ftrp->safe_val);
694         }
695
696         val &= valid_mask;
697
698         reg->sys_val = val;
699         reg->strict_mask = strict_mask;
700         reg->user_mask = user_mask;
701 }
702
703 extern const struct arm64_cpu_capabilities arm64_errata[];
704 static const struct arm64_cpu_capabilities arm64_features[];
705
706 static void __init
707 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
708 {
709         for (; caps->matches; caps++) {
710                 if (WARN(caps->capability >= ARM64_NCAPS,
711                         "Invalid capability %d\n", caps->capability))
712                         continue;
713                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
714                         "Duplicate entry for capability %d\n",
715                         caps->capability))
716                         continue;
717                 cpu_hwcaps_ptrs[caps->capability] = caps;
718         }
719 }
720
721 static void __init init_cpu_hwcaps_indirect_list(void)
722 {
723         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
724         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
725 }
726
727 static void __init setup_boot_cpu_capabilities(void);
728
729 void __init init_cpu_features(struct cpuinfo_arm64 *info)
730 {
731         /* Before we start using the tables, make sure it is sorted */
732         sort_ftr_regs();
733
734         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
735         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
736         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
737         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
738         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
739         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
740         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
741         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
742         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
743         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
744         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
745         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
746         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
747
748         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
749                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
750                 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
751                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
752                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
753                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
754                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
755                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
756                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
757                 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
758                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
759                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
760                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
761                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
762                 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
763                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
764                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
765                 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
766                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
767                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
768                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
769         }
770
771         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
772                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
773                 sve_init_vq_map();
774         }
775
776         /*
777          * Initialize the indirect array of CPU hwcaps capabilities pointers
778          * before we handle the boot CPU below.
779          */
780         init_cpu_hwcaps_indirect_list();
781
782         /*
783          * Detect and enable early CPU capabilities based on the boot CPU,
784          * after we have initialised the CPU feature infrastructure.
785          */
786         setup_boot_cpu_capabilities();
787 }
788
789 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
790 {
791         const struct arm64_ftr_bits *ftrp;
792
793         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
794                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
795                 s64 ftr_new = arm64_ftr_value(ftrp, new);
796
797                 if (ftr_cur == ftr_new)
798                         continue;
799                 /* Find a safe value */
800                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
801                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
802         }
803
804 }
805
806 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
807 {
808         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
809
810         BUG_ON(!regp);
811         update_cpu_ftr_reg(regp, val);
812         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
813                 return 0;
814         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
815                         regp->name, boot, cpu, val);
816         return 1;
817 }
818
819 static void relax_cpu_ftr_reg(u32 sys_id, int field)
820 {
821         const struct arm64_ftr_bits *ftrp;
822         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
823
824         if (WARN_ON(!regp))
825                 return;
826
827         for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
828                 if (ftrp->shift == field) {
829                         regp->strict_mask &= ~arm64_ftr_mask(ftrp);
830                         break;
831                 }
832         }
833
834         /* Bogus field? */
835         WARN_ON(!ftrp->width);
836 }
837
838 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
839                                      struct cpuinfo_arm64 *boot)
840 {
841         int taint = 0;
842         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
843
844         /*
845          * If we don't have AArch32 at all then skip the checks entirely
846          * as the register values may be UNKNOWN and we're not going to be
847          * using them for anything.
848          */
849         if (!id_aa64pfr0_32bit_el0(pfr0))
850                 return taint;
851
852         /*
853          * If we don't have AArch32 at EL1, then relax the strictness of
854          * EL1-dependent register fields to avoid spurious sanity check fails.
855          */
856         if (!id_aa64pfr0_32bit_el1(pfr0)) {
857                 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
858                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
859                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
860                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
861                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
862                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
863         }
864
865         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
866                                       info->reg_id_dfr0, boot->reg_id_dfr0);
867         taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
868                                       info->reg_id_dfr1, boot->reg_id_dfr1);
869         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
870                                       info->reg_id_isar0, boot->reg_id_isar0);
871         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
872                                       info->reg_id_isar1, boot->reg_id_isar1);
873         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
874                                       info->reg_id_isar2, boot->reg_id_isar2);
875         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
876                                       info->reg_id_isar3, boot->reg_id_isar3);
877         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
878                                       info->reg_id_isar4, boot->reg_id_isar4);
879         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
880                                       info->reg_id_isar5, boot->reg_id_isar5);
881         taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
882                                       info->reg_id_isar6, boot->reg_id_isar6);
883
884         /*
885          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
886          * ACTLR formats could differ across CPUs and therefore would have to
887          * be trapped for virtualization anyway.
888          */
889         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
890                                       info->reg_id_mmfr0, boot->reg_id_mmfr0);
891         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
892                                       info->reg_id_mmfr1, boot->reg_id_mmfr1);
893         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
894                                       info->reg_id_mmfr2, boot->reg_id_mmfr2);
895         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
896                                       info->reg_id_mmfr3, boot->reg_id_mmfr3);
897         taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
898                                       info->reg_id_mmfr5, boot->reg_id_mmfr5);
899         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
900                                       info->reg_id_pfr0, boot->reg_id_pfr0);
901         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
902                                       info->reg_id_pfr1, boot->reg_id_pfr1);
903         taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
904                                       info->reg_id_pfr2, boot->reg_id_pfr2);
905         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
906                                       info->reg_mvfr0, boot->reg_mvfr0);
907         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
908                                       info->reg_mvfr1, boot->reg_mvfr1);
909         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
910                                       info->reg_mvfr2, boot->reg_mvfr2);
911
912         return taint;
913 }
914
915 /*
916  * Update system wide CPU feature registers with the values from a
917  * non-boot CPU. Also performs SANITY checks to make sure that there
918  * aren't any insane variations from that of the boot CPU.
919  */
920 void update_cpu_features(int cpu,
921                          struct cpuinfo_arm64 *info,
922                          struct cpuinfo_arm64 *boot)
923 {
924         int taint = 0;
925
926         /*
927          * The kernel can handle differing I-cache policies, but otherwise
928          * caches should look identical. Userspace JITs will make use of
929          * *minLine.
930          */
931         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
932                                       info->reg_ctr, boot->reg_ctr);
933
934         /*
935          * Userspace may perform DC ZVA instructions. Mismatched block sizes
936          * could result in too much or too little memory being zeroed if a
937          * process is preempted and migrated between CPUs.
938          */
939         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
940                                       info->reg_dczid, boot->reg_dczid);
941
942         /* If different, timekeeping will be broken (especially with KVM) */
943         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
944                                       info->reg_cntfrq, boot->reg_cntfrq);
945
946         /*
947          * The kernel uses self-hosted debug features and expects CPUs to
948          * support identical debug features. We presently need CTX_CMPs, WRPs,
949          * and BRPs to be identical.
950          * ID_AA64DFR1 is currently RES0.
951          */
952         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
953                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
954         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
955                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
956         /*
957          * Even in big.LITTLE, processors should be identical instruction-set
958          * wise.
959          */
960         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
961                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
962         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
963                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
964
965         /*
966          * Differing PARange support is fine as long as all peripherals and
967          * memory are mapped within the minimum PARange of all CPUs.
968          * Linux should not care about secure memory.
969          */
970         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
971                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
972         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
973                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
974         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
975                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
976
977         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
978                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
979         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
980                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
981
982         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
983                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
984
985         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
986                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
987                                         info->reg_zcr, boot->reg_zcr);
988
989                 /* Probe vector lengths, unless we already gave up on SVE */
990                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
991                     !system_capabilities_finalized())
992                         sve_update_vq_map();
993         }
994
995         /*
996          * This relies on a sanitised view of the AArch64 ID registers
997          * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
998          */
999         taint |= update_32bit_cpu_features(cpu, info, boot);
1000
1001         /*
1002          * Mismatched CPU features are a recipe for disaster. Don't even
1003          * pretend to support them.
1004          */
1005         if (taint) {
1006                 pr_warn_once("Unsupported CPU feature variation detected.\n");
1007                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1008         }
1009 }
1010
1011 u64 read_sanitised_ftr_reg(u32 id)
1012 {
1013         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1014
1015         /* We shouldn't get a request for an unsupported register */
1016         BUG_ON(!regp);
1017         return regp->sys_val;
1018 }
1019
1020 #define read_sysreg_case(r)     \
1021         case r:         return read_sysreg_s(r)
1022
1023 /*
1024  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1025  * Read the system register on the current CPU
1026  */
1027 static u64 __read_sysreg_by_encoding(u32 sys_id)
1028 {
1029         switch (sys_id) {
1030         read_sysreg_case(SYS_ID_PFR0_EL1);
1031         read_sysreg_case(SYS_ID_PFR1_EL1);
1032         read_sysreg_case(SYS_ID_PFR2_EL1);
1033         read_sysreg_case(SYS_ID_DFR0_EL1);
1034         read_sysreg_case(SYS_ID_DFR1_EL1);
1035         read_sysreg_case(SYS_ID_MMFR0_EL1);
1036         read_sysreg_case(SYS_ID_MMFR1_EL1);
1037         read_sysreg_case(SYS_ID_MMFR2_EL1);
1038         read_sysreg_case(SYS_ID_MMFR3_EL1);
1039         read_sysreg_case(SYS_ID_MMFR5_EL1);
1040         read_sysreg_case(SYS_ID_ISAR0_EL1);
1041         read_sysreg_case(SYS_ID_ISAR1_EL1);
1042         read_sysreg_case(SYS_ID_ISAR2_EL1);
1043         read_sysreg_case(SYS_ID_ISAR3_EL1);
1044         read_sysreg_case(SYS_ID_ISAR4_EL1);
1045         read_sysreg_case(SYS_ID_ISAR5_EL1);
1046         read_sysreg_case(SYS_ID_ISAR6_EL1);
1047         read_sysreg_case(SYS_MVFR0_EL1);
1048         read_sysreg_case(SYS_MVFR1_EL1);
1049         read_sysreg_case(SYS_MVFR2_EL1);
1050
1051         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1052         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1053         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1054         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1055         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1056         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1057         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1058         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1059         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1060         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1061
1062         read_sysreg_case(SYS_CNTFRQ_EL0);
1063         read_sysreg_case(SYS_CTR_EL0);
1064         read_sysreg_case(SYS_DCZID_EL0);
1065
1066         default:
1067                 BUG();
1068                 return 0;
1069         }
1070 }
1071
1072 #include <linux/irqchip/arm-gic-v3.h>
1073
1074 static bool
1075 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1076 {
1077         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1078
1079         return val >= entry->min_field_value;
1080 }
1081
1082 static bool
1083 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1084 {
1085         u64 val;
1086
1087         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1088         if (scope == SCOPE_SYSTEM)
1089                 val = read_sanitised_ftr_reg(entry->sys_reg);
1090         else
1091                 val = __read_sysreg_by_encoding(entry->sys_reg);
1092
1093         return feature_matches(val, entry);
1094 }
1095
1096 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1097 {
1098         bool has_sre;
1099
1100         if (!has_cpuid_feature(entry, scope))
1101                 return false;
1102
1103         has_sre = gic_enable_sre();
1104         if (!has_sre)
1105                 pr_warn_once("%s present but disabled by higher exception level\n",
1106                              entry->desc);
1107
1108         return has_sre;
1109 }
1110
1111 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1112 {
1113         u32 midr = read_cpuid_id();
1114
1115         /* Cavium ThunderX pass 1.x and 2.x */
1116         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1117                 MIDR_CPU_VAR_REV(0, 0),
1118                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1119 }
1120
1121 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1122 {
1123         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1124
1125         return cpuid_feature_extract_signed_field(pfr0,
1126                                         ID_AA64PFR0_FP_SHIFT) < 0;
1127 }
1128
1129 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1130                           int scope)
1131 {
1132         u64 ctr;
1133
1134         if (scope == SCOPE_SYSTEM)
1135                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1136         else
1137                 ctr = read_cpuid_effective_cachetype();
1138
1139         return ctr & BIT(CTR_IDC_SHIFT);
1140 }
1141
1142 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1143 {
1144         /*
1145          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1146          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1147          * to the CTR_EL0 on this CPU and emulate it with the real/safe
1148          * value.
1149          */
1150         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1151                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1152 }
1153
1154 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1155                           int scope)
1156 {
1157         u64 ctr;
1158
1159         if (scope == SCOPE_SYSTEM)
1160                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1161         else
1162                 ctr = read_cpuid_cachetype();
1163
1164         return ctr & BIT(CTR_DIC_SHIFT);
1165 }
1166
1167 static bool __maybe_unused
1168 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1169 {
1170         /*
1171          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1172          * may share TLB entries with a CPU stuck in the crashed
1173          * kernel.
1174          */
1175          if (is_kdump_kernel())
1176                 return false;
1177
1178         return has_cpuid_feature(entry, scope);
1179 }
1180
1181 /*
1182  * This check is triggered during the early boot before the cpufeature
1183  * is initialised. Checking the status on the local CPU allows the boot
1184  * CPU to detect the need for non-global mappings and thus avoiding a
1185  * pagetable re-write after all the CPUs are booted. This check will be
1186  * anyway run on individual CPUs, allowing us to get the consistent
1187  * state once the SMP CPUs are up and thus make the switch to non-global
1188  * mappings if required.
1189  */
1190 bool kaslr_requires_kpti(void)
1191 {
1192         if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1193                 return false;
1194
1195         /*
1196          * E0PD does a similar job to KPTI so can be used instead
1197          * where available.
1198          */
1199         if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1200                 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1201                 if (cpuid_feature_extract_unsigned_field(mmfr2,
1202                                                 ID_AA64MMFR2_E0PD_SHIFT))
1203                         return false;
1204         }
1205
1206         /*
1207          * Systems affected by Cavium erratum 24756 are incompatible
1208          * with KPTI.
1209          */
1210         if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1211                 extern const struct midr_range cavium_erratum_27456_cpus[];
1212
1213                 if (is_midr_in_range_list(read_cpuid_id(),
1214                                           cavium_erratum_27456_cpus))
1215                         return false;
1216         }
1217
1218         return kaslr_offset() > 0;
1219 }
1220
1221 static bool __meltdown_safe = true;
1222 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1223
1224 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1225                                 int scope)
1226 {
1227         /* List of CPUs that are not vulnerable and don't need KPTI */
1228         static const struct midr_range kpti_safe_list[] = {
1229                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1230                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1231                 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1232                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1233                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1234                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1235                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1236                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1237                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1238                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1239                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1240                 { /* sentinel */ }
1241         };
1242         char const *str = "kpti command line option";
1243         bool meltdown_safe;
1244
1245         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1246
1247         /* Defer to CPU feature registers */
1248         if (has_cpuid_feature(entry, scope))
1249                 meltdown_safe = true;
1250
1251         if (!meltdown_safe)
1252                 __meltdown_safe = false;
1253
1254         /*
1255          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1256          * ThunderX leads to apparent I-cache corruption of kernel text, which
1257          * ends as well as you might imagine. Don't even try.
1258          */
1259         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1260                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1261                 __kpti_forced = -1;
1262         }
1263
1264         /* Useful for KASLR robustness */
1265         if (kaslr_requires_kpti()) {
1266                 if (!__kpti_forced) {
1267                         str = "KASLR";
1268                         __kpti_forced = 1;
1269                 }
1270         }
1271
1272         if (cpu_mitigations_off() && !__kpti_forced) {
1273                 str = "mitigations=off";
1274                 __kpti_forced = -1;
1275         }
1276
1277         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1278                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1279                 return false;
1280         }
1281
1282         /* Forced? */
1283         if (__kpti_forced) {
1284                 pr_info_once("kernel page table isolation forced %s by %s\n",
1285                              __kpti_forced > 0 ? "ON" : "OFF", str);
1286                 return __kpti_forced > 0;
1287         }
1288
1289         return !meltdown_safe;
1290 }
1291
1292 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1293 static void
1294 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1295 {
1296         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1297         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1298         kpti_remap_fn *remap_fn;
1299
1300         int cpu = smp_processor_id();
1301
1302         /*
1303          * We don't need to rewrite the page-tables if either we've done
1304          * it already or we have KASLR enabled and therefore have not
1305          * created any global mappings at all.
1306          */
1307         if (arm64_use_ng_mappings)
1308                 return;
1309
1310         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1311
1312         cpu_install_idmap();
1313         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1314         cpu_uninstall_idmap();
1315
1316         if (!cpu)
1317                 arm64_use_ng_mappings = true;
1318
1319         return;
1320 }
1321 #else
1322 static void
1323 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1324 {
1325 }
1326 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1327
1328 static int __init parse_kpti(char *str)
1329 {
1330         bool enabled;
1331         int ret = strtobool(str, &enabled);
1332
1333         if (ret)
1334                 return ret;
1335
1336         __kpti_forced = enabled ? 1 : -1;
1337         return 0;
1338 }
1339 early_param("kpti", parse_kpti);
1340
1341 #ifdef CONFIG_ARM64_HW_AFDBM
1342 static inline void __cpu_enable_hw_dbm(void)
1343 {
1344         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1345
1346         write_sysreg(tcr, tcr_el1);
1347         isb();
1348 }
1349
1350 static bool cpu_has_broken_dbm(void)
1351 {
1352         /* List of CPUs which have broken DBM support. */
1353         static const struct midr_range cpus[] = {
1354 #ifdef CONFIG_ARM64_ERRATUM_1024718
1355                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1356 #endif
1357                 {},
1358         };
1359
1360         return is_midr_in_range_list(read_cpuid_id(), cpus);
1361 }
1362
1363 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1364 {
1365         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1366                !cpu_has_broken_dbm();
1367 }
1368
1369 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1370 {
1371         if (cpu_can_use_dbm(cap))
1372                 __cpu_enable_hw_dbm();
1373 }
1374
1375 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1376                        int __unused)
1377 {
1378         static bool detected = false;
1379         /*
1380          * DBM is a non-conflicting feature. i.e, the kernel can safely
1381          * run a mix of CPUs with and without the feature. So, we
1382          * unconditionally enable the capability to allow any late CPU
1383          * to use the feature. We only enable the control bits on the
1384          * CPU, if it actually supports.
1385          *
1386          * We have to make sure we print the "feature" detection only
1387          * when at least one CPU actually uses it. So check if this CPU
1388          * can actually use it and print the message exactly once.
1389          *
1390          * This is safe as all CPUs (including secondary CPUs - due to the
1391          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1392          * goes through the "matches" check exactly once. Also if a CPU
1393          * matches the criteria, it is guaranteed that the CPU will turn
1394          * the DBM on, as the capability is unconditionally enabled.
1395          */
1396         if (!detected && cpu_can_use_dbm(cap)) {
1397                 detected = true;
1398                 pr_info("detected: Hardware dirty bit management\n");
1399         }
1400
1401         return true;
1402 }
1403
1404 #endif
1405
1406 #ifdef CONFIG_ARM64_AMU_EXTN
1407
1408 /*
1409  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1410  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1411  * information regarding all the events that it supports. When a CPU bit is
1412  * set in the cpumask, the user of this feature can only rely on the presence
1413  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1414  * counters are enabled or access to these counters is enabled by code
1415  * executed at higher exception levels (firmware).
1416  */
1417 static struct cpumask amu_cpus __read_mostly;
1418
1419 bool cpu_has_amu_feat(int cpu)
1420 {
1421         return cpumask_test_cpu(cpu, &amu_cpus);
1422 }
1423
1424 /* Initialize the use of AMU counters for frequency invariance */
1425 extern void init_cpu_freq_invariance_counters(void);
1426
1427 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1428 {
1429         if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1430                 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1431                         smp_processor_id());
1432                 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1433                 init_cpu_freq_invariance_counters();
1434         }
1435 }
1436
1437 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1438                     int __unused)
1439 {
1440         /*
1441          * The AMU extension is a non-conflicting feature: the kernel can
1442          * safely run a mix of CPUs with and without support for the
1443          * activity monitors extension. Therefore, unconditionally enable
1444          * the capability to allow any late CPU to use the feature.
1445          *
1446          * With this feature unconditionally enabled, the cpu_enable
1447          * function will be called for all CPUs that match the criteria,
1448          * including secondary and hotplugged, marking this feature as
1449          * present on that respective CPU. The enable function will also
1450          * print a detection message.
1451          */
1452
1453         return true;
1454 }
1455 #endif
1456
1457 #ifdef CONFIG_ARM64_VHE
1458 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1459 {
1460         return is_kernel_in_hyp_mode();
1461 }
1462
1463 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1464 {
1465         /*
1466          * Copy register values that aren't redirected by hardware.
1467          *
1468          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1469          * this value to tpidr_el2 before we patch the code. Once we've done
1470          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1471          * do anything here.
1472          */
1473         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1474                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1475 }
1476 #endif
1477
1478 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1479 {
1480         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1481
1482         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1483         WARN_ON(val & (7 << 27 | 7 << 21));
1484 }
1485
1486 #ifdef CONFIG_ARM64_SSBD
1487 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1488 {
1489         if (user_mode(regs))
1490                 return 1;
1491
1492         if (instr & BIT(PSTATE_Imm_shift))
1493                 regs->pstate |= PSR_SSBS_BIT;
1494         else
1495                 regs->pstate &= ~PSR_SSBS_BIT;
1496
1497         arm64_skip_faulting_instruction(regs, 4);
1498         return 0;
1499 }
1500
1501 static struct undef_hook ssbs_emulation_hook = {
1502         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1503         .instr_val      = 0xd500401f | PSTATE_SSBS,
1504         .fn             = ssbs_emulation_handler,
1505 };
1506
1507 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1508 {
1509         static bool undef_hook_registered = false;
1510         static DEFINE_RAW_SPINLOCK(hook_lock);
1511
1512         raw_spin_lock(&hook_lock);
1513         if (!undef_hook_registered) {
1514                 register_undef_hook(&ssbs_emulation_hook);
1515                 undef_hook_registered = true;
1516         }
1517         raw_spin_unlock(&hook_lock);
1518
1519         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1520                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1521                 arm64_set_ssbd_mitigation(false);
1522         } else {
1523                 arm64_set_ssbd_mitigation(true);
1524         }
1525 }
1526 #endif /* CONFIG_ARM64_SSBD */
1527
1528 #ifdef CONFIG_ARM64_PAN
1529 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1530 {
1531         /*
1532          * We modify PSTATE. This won't work from irq context as the PSTATE
1533          * is discarded once we return from the exception.
1534          */
1535         WARN_ON_ONCE(in_interrupt());
1536
1537         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1538         asm(SET_PSTATE_PAN(1));
1539 }
1540 #endif /* CONFIG_ARM64_PAN */
1541
1542 #ifdef CONFIG_ARM64_RAS_EXTN
1543 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1544 {
1545         /* Firmware may have left a deferred SError in this register. */
1546         write_sysreg_s(0, SYS_DISR_EL1);
1547 }
1548 #endif /* CONFIG_ARM64_RAS_EXTN */
1549
1550 #ifdef CONFIG_ARM64_PTR_AUTH
1551 static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
1552                              int __unused)
1553 {
1554         return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
1555                __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF);
1556 }
1557
1558 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1559                              int __unused)
1560 {
1561         return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1562                __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1563 }
1564 #endif /* CONFIG_ARM64_PTR_AUTH */
1565
1566 #ifdef CONFIG_ARM64_E0PD
1567 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1568 {
1569         if (this_cpu_has_cap(ARM64_HAS_E0PD))
1570                 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1571 }
1572 #endif /* CONFIG_ARM64_E0PD */
1573
1574 #ifdef CONFIG_ARM64_PSEUDO_NMI
1575 static bool enable_pseudo_nmi;
1576
1577 static int __init early_enable_pseudo_nmi(char *p)
1578 {
1579         return strtobool(p, &enable_pseudo_nmi);
1580 }
1581 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1582
1583 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1584                                    int scope)
1585 {
1586         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1587 }
1588 #endif
1589
1590 /* Internal helper functions to match cpu capability type */
1591 static bool
1592 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1593 {
1594         return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1595 }
1596
1597 static bool
1598 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1599 {
1600         return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1601 }
1602
1603 static bool
1604 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1605 {
1606         return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1607 }
1608
1609 static const struct arm64_cpu_capabilities arm64_features[] = {
1610         {
1611                 .desc = "GIC system register CPU interface",
1612                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1613                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1614                 .matches = has_useable_gicv3_cpuif,
1615                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1616                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1617                 .sign = FTR_UNSIGNED,
1618                 .min_field_value = 1,
1619         },
1620 #ifdef CONFIG_ARM64_PAN
1621         {
1622                 .desc = "Privileged Access Never",
1623                 .capability = ARM64_HAS_PAN,
1624                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1625                 .matches = has_cpuid_feature,
1626                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1627                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1628                 .sign = FTR_UNSIGNED,
1629                 .min_field_value = 1,
1630                 .cpu_enable = cpu_enable_pan,
1631         },
1632 #endif /* CONFIG_ARM64_PAN */
1633 #ifdef CONFIG_ARM64_LSE_ATOMICS
1634         {
1635                 .desc = "LSE atomic instructions",
1636                 .capability = ARM64_HAS_LSE_ATOMICS,
1637                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1638                 .matches = has_cpuid_feature,
1639                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1640                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1641                 .sign = FTR_UNSIGNED,
1642                 .min_field_value = 2,
1643         },
1644 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1645         {
1646                 .desc = "Software prefetching using PRFM",
1647                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1648                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1649                 .matches = has_no_hw_prefetch,
1650         },
1651 #ifdef CONFIG_ARM64_UAO
1652         {
1653                 .desc = "User Access Override",
1654                 .capability = ARM64_HAS_UAO,
1655                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1656                 .matches = has_cpuid_feature,
1657                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1658                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1659                 .min_field_value = 1,
1660                 /*
1661                  * We rely on stop_machine() calling uao_thread_switch() to set
1662                  * UAO immediately after patching.
1663                  */
1664         },
1665 #endif /* CONFIG_ARM64_UAO */
1666 #ifdef CONFIG_ARM64_PAN
1667         {
1668                 .capability = ARM64_ALT_PAN_NOT_UAO,
1669                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1670                 .matches = cpufeature_pan_not_uao,
1671         },
1672 #endif /* CONFIG_ARM64_PAN */
1673 #ifdef CONFIG_ARM64_VHE
1674         {
1675                 .desc = "Virtualization Host Extensions",
1676                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1677                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1678                 .matches = runs_at_el2,
1679                 .cpu_enable = cpu_copy_el2regs,
1680         },
1681 #endif  /* CONFIG_ARM64_VHE */
1682         {
1683                 .desc = "32-bit EL0 Support",
1684                 .capability = ARM64_HAS_32BIT_EL0,
1685                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1686                 .matches = has_cpuid_feature,
1687                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1688                 .sign = FTR_UNSIGNED,
1689                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1690                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1691         },
1692 #ifdef CONFIG_KVM
1693         {
1694                 .desc = "32-bit EL1 Support",
1695                 .capability = ARM64_HAS_32BIT_EL1,
1696                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1697                 .matches = has_cpuid_feature,
1698                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1699                 .sign = FTR_UNSIGNED,
1700                 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1701                 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1702         },
1703 #endif
1704         {
1705                 .desc = "Kernel page table isolation (KPTI)",
1706                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1707                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1708                 /*
1709                  * The ID feature fields below are used to indicate that
1710                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1711                  * more details.
1712                  */
1713                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1714                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1715                 .min_field_value = 1,
1716                 .matches = unmap_kernel_at_el0,
1717                 .cpu_enable = kpti_install_ng_mappings,
1718         },
1719         {
1720                 /* FP/SIMD is not implemented */
1721                 .capability = ARM64_HAS_NO_FPSIMD,
1722                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1723                 .min_field_value = 0,
1724                 .matches = has_no_fpsimd,
1725         },
1726 #ifdef CONFIG_ARM64_PMEM
1727         {
1728                 .desc = "Data cache clean to Point of Persistence",
1729                 .capability = ARM64_HAS_DCPOP,
1730                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1731                 .matches = has_cpuid_feature,
1732                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1733                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1734                 .min_field_value = 1,
1735         },
1736         {
1737                 .desc = "Data cache clean to Point of Deep Persistence",
1738                 .capability = ARM64_HAS_DCPODP,
1739                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1740                 .matches = has_cpuid_feature,
1741                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1742                 .sign = FTR_UNSIGNED,
1743                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1744                 .min_field_value = 2,
1745         },
1746 #endif
1747 #ifdef CONFIG_ARM64_SVE
1748         {
1749                 .desc = "Scalable Vector Extension",
1750                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1751                 .capability = ARM64_SVE,
1752                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1753                 .sign = FTR_UNSIGNED,
1754                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1755                 .min_field_value = ID_AA64PFR0_SVE,
1756                 .matches = has_cpuid_feature,
1757                 .cpu_enable = sve_kernel_enable,
1758         },
1759 #endif /* CONFIG_ARM64_SVE */
1760 #ifdef CONFIG_ARM64_RAS_EXTN
1761         {
1762                 .desc = "RAS Extension Support",
1763                 .capability = ARM64_HAS_RAS_EXTN,
1764                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1765                 .matches = has_cpuid_feature,
1766                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1767                 .sign = FTR_UNSIGNED,
1768                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1769                 .min_field_value = ID_AA64PFR0_RAS_V1,
1770                 .cpu_enable = cpu_clear_disr,
1771         },
1772 #endif /* CONFIG_ARM64_RAS_EXTN */
1773 #ifdef CONFIG_ARM64_AMU_EXTN
1774         {
1775                 /*
1776                  * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1777                  * Therefore, don't provide .desc as we don't want the detection
1778                  * message to be shown until at least one CPU is detected to
1779                  * support the feature.
1780                  */
1781                 .capability = ARM64_HAS_AMU_EXTN,
1782                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1783                 .matches = has_amu,
1784                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1785                 .sign = FTR_UNSIGNED,
1786                 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1787                 .min_field_value = ID_AA64PFR0_AMU,
1788                 .cpu_enable = cpu_amu_enable,
1789         },
1790 #endif /* CONFIG_ARM64_AMU_EXTN */
1791         {
1792                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1793                 .capability = ARM64_HAS_CACHE_IDC,
1794                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1795                 .matches = has_cache_idc,
1796                 .cpu_enable = cpu_emulate_effective_ctr,
1797         },
1798         {
1799                 .desc = "Instruction cache invalidation not required for I/D coherence",
1800                 .capability = ARM64_HAS_CACHE_DIC,
1801                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1802                 .matches = has_cache_dic,
1803         },
1804         {
1805                 .desc = "Stage-2 Force Write-Back",
1806                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1807                 .capability = ARM64_HAS_STAGE2_FWB,
1808                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1809                 .sign = FTR_UNSIGNED,
1810                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1811                 .min_field_value = 1,
1812                 .matches = has_cpuid_feature,
1813                 .cpu_enable = cpu_has_fwb,
1814         },
1815 #ifdef CONFIG_ARM64_HW_AFDBM
1816         {
1817                 /*
1818                  * Since we turn this on always, we don't want the user to
1819                  * think that the feature is available when it may not be.
1820                  * So hide the description.
1821                  *
1822                  * .desc = "Hardware pagetable Dirty Bit Management",
1823                  *
1824                  */
1825                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1826                 .capability = ARM64_HW_DBM,
1827                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1828                 .sign = FTR_UNSIGNED,
1829                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1830                 .min_field_value = 2,
1831                 .matches = has_hw_dbm,
1832                 .cpu_enable = cpu_enable_hw_dbm,
1833         },
1834 #endif
1835         {
1836                 .desc = "CRC32 instructions",
1837                 .capability = ARM64_HAS_CRC32,
1838                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1839                 .matches = has_cpuid_feature,
1840                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1841                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1842                 .min_field_value = 1,
1843         },
1844 #ifdef CONFIG_ARM64_SSBD
1845         {
1846                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1847                 .capability = ARM64_SSBS,
1848                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1849                 .matches = has_cpuid_feature,
1850                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1851                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1852                 .sign = FTR_UNSIGNED,
1853                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1854                 .cpu_enable = cpu_enable_ssbs,
1855         },
1856 #endif
1857 #ifdef CONFIG_ARM64_CNP
1858         {
1859                 .desc = "Common not Private translations",
1860                 .capability = ARM64_HAS_CNP,
1861                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1862                 .matches = has_useable_cnp,
1863                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1864                 .sign = FTR_UNSIGNED,
1865                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1866                 .min_field_value = 1,
1867                 .cpu_enable = cpu_enable_cnp,
1868         },
1869 #endif
1870         {
1871                 .desc = "Speculation barrier (SB)",
1872                 .capability = ARM64_HAS_SB,
1873                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1874                 .matches = has_cpuid_feature,
1875                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1876                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1877                 .sign = FTR_UNSIGNED,
1878                 .min_field_value = 1,
1879         },
1880 #ifdef CONFIG_ARM64_PTR_AUTH
1881         {
1882                 .desc = "Address authentication (architected algorithm)",
1883                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1884                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1885                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1886                 .sign = FTR_UNSIGNED,
1887                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1888                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1889                 .matches = has_cpuid_feature,
1890         },
1891         {
1892                 .desc = "Address authentication (IMP DEF algorithm)",
1893                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1894                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1895                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1896                 .sign = FTR_UNSIGNED,
1897                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1898                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1899                 .matches = has_cpuid_feature,
1900         },
1901         {
1902                 .capability = ARM64_HAS_ADDRESS_AUTH,
1903                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1904                 .matches = has_address_auth,
1905         },
1906         {
1907                 .desc = "Generic authentication (architected algorithm)",
1908                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1909                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1910                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1911                 .sign = FTR_UNSIGNED,
1912                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1913                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1914                 .matches = has_cpuid_feature,
1915         },
1916         {
1917                 .desc = "Generic authentication (IMP DEF algorithm)",
1918                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1919                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1920                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1921                 .sign = FTR_UNSIGNED,
1922                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1923                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1924                 .matches = has_cpuid_feature,
1925         },
1926         {
1927                 .capability = ARM64_HAS_GENERIC_AUTH,
1928                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1929                 .matches = has_generic_auth,
1930         },
1931 #endif /* CONFIG_ARM64_PTR_AUTH */
1932 #ifdef CONFIG_ARM64_PSEUDO_NMI
1933         {
1934                 /*
1935                  * Depends on having GICv3
1936                  */
1937                 .desc = "IRQ priority masking",
1938                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1939                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1940                 .matches = can_use_gic_priorities,
1941                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1942                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1943                 .sign = FTR_UNSIGNED,
1944                 .min_field_value = 1,
1945         },
1946 #endif
1947 #ifdef CONFIG_ARM64_E0PD
1948         {
1949                 .desc = "E0PD",
1950                 .capability = ARM64_HAS_E0PD,
1951                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1952                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1953                 .sign = FTR_UNSIGNED,
1954                 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1955                 .matches = has_cpuid_feature,
1956                 .min_field_value = 1,
1957                 .cpu_enable = cpu_enable_e0pd,
1958         },
1959 #endif
1960 #ifdef CONFIG_ARCH_RANDOM
1961         {
1962                 .desc = "Random Number Generator",
1963                 .capability = ARM64_HAS_RNG,
1964                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1965                 .matches = has_cpuid_feature,
1966                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1967                 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1968                 .sign = FTR_UNSIGNED,
1969                 .min_field_value = 1,
1970         },
1971 #endif
1972         {},
1973 };
1974
1975 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1976                 .matches = has_cpuid_feature,                                   \
1977                 .sys_reg = reg,                                                 \
1978                 .field_pos = field,                                             \
1979                 .sign = s,                                                      \
1980                 .min_field_value = min_value,
1981
1982 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1983                 .desc = name,                                                   \
1984                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1985                 .hwcap_type = cap_type,                                         \
1986                 .hwcap = cap,                                                   \
1987
1988 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1989         {                                                                       \
1990                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1991                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1992         }
1993
1994 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1995         {                                                                       \
1996                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1997                 .matches = cpucap_multi_entry_cap_matches,                      \
1998                 .match_list = list,                                             \
1999         }
2000
2001 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
2002         {                                                                       \
2003                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2004                 .matches = match,                                               \
2005         }
2006
2007 #ifdef CONFIG_ARM64_PTR_AUTH
2008 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2009         {
2010                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2011                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2012         },
2013         {
2014                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2015                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2016         },
2017         {},
2018 };
2019
2020 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2021         {
2022                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2023                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2024         },
2025         {
2026                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2027                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2028         },
2029         {},
2030 };
2031 #endif
2032
2033 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2034         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2035         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2036         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2037         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2038         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2039         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2040         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2041         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2042         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2043         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2044         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2045         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2046         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2047         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2048         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2049         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2050         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2051         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2052         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2053         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2054         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2055         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2056         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2057         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2058         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2059         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2060         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2061         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2062         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2063         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2064         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2065         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2066         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2067 #ifdef CONFIG_ARM64_SVE
2068         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2069         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2070         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2071         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2072         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2073         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2074         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2075         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2076         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2077         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2078         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2079 #endif
2080         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2081 #ifdef CONFIG_ARM64_PTR_AUTH
2082         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2083         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2084 #endif
2085         {},
2086 };
2087
2088 #ifdef CONFIG_COMPAT
2089 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2090 {
2091         /*
2092          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2093          * in line with that of arm32 as in vfp_init(). We make sure that the
2094          * check is future proof, by making sure value is non-zero.
2095          */
2096         u32 mvfr1;
2097
2098         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2099         if (scope == SCOPE_SYSTEM)
2100                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2101         else
2102                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2103
2104         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2105                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2106                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2107 }
2108 #endif
2109
2110 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2111 #ifdef CONFIG_COMPAT
2112         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2113         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2114         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2115         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2116         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2117         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2118         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2119         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2120         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2121         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2122 #endif
2123         {},
2124 };
2125
2126 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2127 {
2128         switch (cap->hwcap_type) {
2129         case CAP_HWCAP:
2130                 cpu_set_feature(cap->hwcap);
2131                 break;
2132 #ifdef CONFIG_COMPAT
2133         case CAP_COMPAT_HWCAP:
2134                 compat_elf_hwcap |= (u32)cap->hwcap;
2135                 break;
2136         case CAP_COMPAT_HWCAP2:
2137                 compat_elf_hwcap2 |= (u32)cap->hwcap;
2138                 break;
2139 #endif
2140         default:
2141                 WARN_ON(1);
2142                 break;
2143         }
2144 }
2145
2146 /* Check if we have a particular HWCAP enabled */
2147 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2148 {
2149         bool rc;
2150
2151         switch (cap->hwcap_type) {
2152         case CAP_HWCAP:
2153                 rc = cpu_have_feature(cap->hwcap);
2154                 break;
2155 #ifdef CONFIG_COMPAT
2156         case CAP_COMPAT_HWCAP:
2157                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2158                 break;
2159         case CAP_COMPAT_HWCAP2:
2160                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2161                 break;
2162 #endif
2163         default:
2164                 WARN_ON(1);
2165                 rc = false;
2166         }
2167
2168         return rc;
2169 }
2170
2171 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2172 {
2173         /* We support emulation of accesses to CPU ID feature registers */
2174         cpu_set_named_feature(CPUID);
2175         for (; hwcaps->matches; hwcaps++)
2176                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2177                         cap_set_elf_hwcap(hwcaps);
2178 }
2179
2180 static void update_cpu_capabilities(u16 scope_mask)
2181 {
2182         int i;
2183         const struct arm64_cpu_capabilities *caps;
2184
2185         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2186         for (i = 0; i < ARM64_NCAPS; i++) {
2187                 caps = cpu_hwcaps_ptrs[i];
2188                 if (!caps || !(caps->type & scope_mask) ||
2189                     cpus_have_cap(caps->capability) ||
2190                     !caps->matches(caps, cpucap_default_scope(caps)))
2191                         continue;
2192
2193                 if (caps->desc)
2194                         pr_info("detected: %s\n", caps->desc);
2195                 cpus_set_cap(caps->capability);
2196
2197                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2198                         set_bit(caps->capability, boot_capabilities);
2199         }
2200 }
2201
2202 /*
2203  * Enable all the available capabilities on this CPU. The capabilities
2204  * with BOOT_CPU scope are handled separately and hence skipped here.
2205  */
2206 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2207 {
2208         int i;
2209         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2210
2211         for_each_available_cap(i) {
2212                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2213
2214                 if (WARN_ON(!cap))
2215                         continue;
2216
2217                 if (!(cap->type & non_boot_scope))
2218                         continue;
2219
2220                 if (cap->cpu_enable)
2221                         cap->cpu_enable(cap);
2222         }
2223         return 0;
2224 }
2225
2226 /*
2227  * Run through the enabled capabilities and enable() it on all active
2228  * CPUs
2229  */
2230 static void __init enable_cpu_capabilities(u16 scope_mask)
2231 {
2232         int i;
2233         const struct arm64_cpu_capabilities *caps;
2234         bool boot_scope;
2235
2236         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2237         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2238
2239         for (i = 0; i < ARM64_NCAPS; i++) {
2240                 unsigned int num;
2241
2242                 caps = cpu_hwcaps_ptrs[i];
2243                 if (!caps || !(caps->type & scope_mask))
2244                         continue;
2245                 num = caps->capability;
2246                 if (!cpus_have_cap(num))
2247                         continue;
2248
2249                 /* Ensure cpus_have_const_cap(num) works */
2250                 static_branch_enable(&cpu_hwcap_keys[num]);
2251
2252                 if (boot_scope && caps->cpu_enable)
2253                         /*
2254                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
2255                          * before any secondary CPU boots. Thus, each secondary
2256                          * will enable the capability as appropriate via
2257                          * check_local_cpu_capabilities(). The only exception is
2258                          * the boot CPU, for which the capability must be
2259                          * enabled here. This approach avoids costly
2260                          * stop_machine() calls for this case.
2261                          */
2262                         caps->cpu_enable(caps);
2263         }
2264
2265         /*
2266          * For all non-boot scope capabilities, use stop_machine()
2267          * as it schedules the work allowing us to modify PSTATE,
2268          * instead of on_each_cpu() which uses an IPI, giving us a
2269          * PSTATE that disappears when we return.
2270          */
2271         if (!boot_scope)
2272                 stop_machine(cpu_enable_non_boot_scope_capabilities,
2273                              NULL, cpu_online_mask);
2274 }
2275
2276 /*
2277  * Run through the list of capabilities to check for conflicts.
2278  * If the system has already detected a capability, take necessary
2279  * action on this CPU.
2280  */
2281 static void verify_local_cpu_caps(u16 scope_mask)
2282 {
2283         int i;
2284         bool cpu_has_cap, system_has_cap;
2285         const struct arm64_cpu_capabilities *caps;
2286
2287         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2288
2289         for (i = 0; i < ARM64_NCAPS; i++) {
2290                 caps = cpu_hwcaps_ptrs[i];
2291                 if (!caps || !(caps->type & scope_mask))
2292                         continue;
2293
2294                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2295                 system_has_cap = cpus_have_cap(caps->capability);
2296
2297                 if (system_has_cap) {
2298                         /*
2299                          * Check if the new CPU misses an advertised feature,
2300                          * which is not safe to miss.
2301                          */
2302                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2303                                 break;
2304                         /*
2305                          * We have to issue cpu_enable() irrespective of
2306                          * whether the CPU has it or not, as it is enabeld
2307                          * system wide. It is upto the call back to take
2308                          * appropriate action on this CPU.
2309                          */
2310                         if (caps->cpu_enable)
2311                                 caps->cpu_enable(caps);
2312                 } else {
2313                         /*
2314                          * Check if the CPU has this capability if it isn't
2315                          * safe to have when the system doesn't.
2316                          */
2317                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2318                                 break;
2319                 }
2320         }
2321
2322         if (i < ARM64_NCAPS) {
2323                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2324                         smp_processor_id(), caps->capability,
2325                         caps->desc, system_has_cap, cpu_has_cap);
2326
2327                 if (cpucap_panic_on_conflict(caps))
2328                         cpu_panic_kernel();
2329                 else
2330                         cpu_die_early();
2331         }
2332 }
2333
2334 /*
2335  * Check for CPU features that are used in early boot
2336  * based on the Boot CPU value.
2337  */
2338 static void check_early_cpu_features(void)
2339 {
2340         verify_cpu_asid_bits();
2341
2342         verify_local_cpu_caps(SCOPE_BOOT_CPU);
2343 }
2344
2345 static void
2346 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2347 {
2348
2349         for (; caps->matches; caps++)
2350                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2351                         pr_crit("CPU%d: missing HWCAP: %s\n",
2352                                         smp_processor_id(), caps->desc);
2353                         cpu_die_early();
2354                 }
2355 }
2356
2357 static void verify_sve_features(void)
2358 {
2359         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2360         u64 zcr = read_zcr_features();
2361
2362         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2363         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2364
2365         if (len < safe_len || sve_verify_vq_map()) {
2366                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2367                         smp_processor_id());
2368                 cpu_die_early();
2369         }
2370
2371         /* Add checks on other ZCR bits here if necessary */
2372 }
2373
2374 static void verify_hyp_capabilities(void)
2375 {
2376         u64 safe_mmfr1, mmfr0, mmfr1;
2377         int parange, ipa_max;
2378         unsigned int safe_vmid_bits, vmid_bits;
2379
2380         if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST))
2381                 return;
2382
2383         safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2384         mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2385         mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2386
2387         /* Verify VMID bits */
2388         safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2389         vmid_bits = get_vmid_bits(mmfr1);
2390         if (vmid_bits < safe_vmid_bits) {
2391                 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2392                 cpu_die_early();
2393         }
2394
2395         /* Verify IPA range */
2396         parange = cpuid_feature_extract_unsigned_field(mmfr0,
2397                                 ID_AA64MMFR0_PARANGE_SHIFT);
2398         ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2399         if (ipa_max < get_kvm_ipa_limit()) {
2400                 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2401                 cpu_die_early();
2402         }
2403 }
2404
2405 /*
2406  * Run through the enabled system capabilities and enable() it on this CPU.
2407  * The capabilities were decided based on the available CPUs at the boot time.
2408  * Any new CPU should match the system wide status of the capability. If the
2409  * new CPU doesn't have a capability which the system now has enabled, we
2410  * cannot do anything to fix it up and could cause unexpected failures. So
2411  * we park the CPU.
2412  */
2413 static void verify_local_cpu_capabilities(void)
2414 {
2415         /*
2416          * The capabilities with SCOPE_BOOT_CPU are checked from
2417          * check_early_cpu_features(), as they need to be verified
2418          * on all secondary CPUs.
2419          */
2420         verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2421
2422         verify_local_elf_hwcaps(arm64_elf_hwcaps);
2423
2424         if (system_supports_32bit_el0())
2425                 verify_local_elf_hwcaps(compat_elf_hwcaps);
2426
2427         if (system_supports_sve())
2428                 verify_sve_features();
2429
2430         if (is_hyp_mode_available())
2431                 verify_hyp_capabilities();
2432 }
2433
2434 void check_local_cpu_capabilities(void)
2435 {
2436         /*
2437          * All secondary CPUs should conform to the early CPU features
2438          * in use by the kernel based on boot CPU.
2439          */
2440         check_early_cpu_features();
2441
2442         /*
2443          * If we haven't finalised the system capabilities, this CPU gets
2444          * a chance to update the errata work arounds and local features.
2445          * Otherwise, this CPU should verify that it has all the system
2446          * advertised capabilities.
2447          */
2448         if (!system_capabilities_finalized())
2449                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2450         else
2451                 verify_local_cpu_capabilities();
2452 }
2453
2454 static void __init setup_boot_cpu_capabilities(void)
2455 {
2456         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2457         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2458         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2459         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2460 }
2461
2462 bool this_cpu_has_cap(unsigned int n)
2463 {
2464         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2465                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2466
2467                 if (cap)
2468                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2469         }
2470
2471         return false;
2472 }
2473
2474 /*
2475  * This helper function is used in a narrow window when,
2476  * - The system wide safe registers are set with all the SMP CPUs and,
2477  * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2478  * In all other cases cpus_have_{const_}cap() should be used.
2479  */
2480 static bool __system_matches_cap(unsigned int n)
2481 {
2482         if (n < ARM64_NCAPS) {
2483                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2484
2485                 if (cap)
2486                         return cap->matches(cap, SCOPE_SYSTEM);
2487         }
2488         return false;
2489 }
2490
2491 void cpu_set_feature(unsigned int num)
2492 {
2493         WARN_ON(num >= MAX_CPU_FEATURES);
2494         elf_hwcap |= BIT(num);
2495 }
2496 EXPORT_SYMBOL_GPL(cpu_set_feature);
2497
2498 bool cpu_have_feature(unsigned int num)
2499 {
2500         WARN_ON(num >= MAX_CPU_FEATURES);
2501         return elf_hwcap & BIT(num);
2502 }
2503 EXPORT_SYMBOL_GPL(cpu_have_feature);
2504
2505 unsigned long cpu_get_elf_hwcap(void)
2506 {
2507         /*
2508          * We currently only populate the first 32 bits of AT_HWCAP. Please
2509          * note that for userspace compatibility we guarantee that bits 62
2510          * and 63 will always be returned as 0.
2511          */
2512         return lower_32_bits(elf_hwcap);
2513 }
2514
2515 unsigned long cpu_get_elf_hwcap2(void)
2516 {
2517         return upper_32_bits(elf_hwcap);
2518 }
2519
2520 static void __init setup_system_capabilities(void)
2521 {
2522         /*
2523          * We have finalised the system-wide safe feature
2524          * registers, finalise the capabilities that depend
2525          * on it. Also enable all the available capabilities,
2526          * that are not enabled already.
2527          */
2528         update_cpu_capabilities(SCOPE_SYSTEM);
2529         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2530 }
2531
2532 void __init setup_cpu_features(void)
2533 {
2534         u32 cwg;
2535
2536         setup_system_capabilities();
2537         setup_elf_hwcaps(arm64_elf_hwcaps);
2538
2539         if (system_supports_32bit_el0())
2540                 setup_elf_hwcaps(compat_elf_hwcaps);
2541
2542         if (system_uses_ttbr0_pan())
2543                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2544
2545         sve_setup();
2546         minsigstksz_setup();
2547
2548         /* Advertise that we have computed the system capabilities */
2549         finalize_system_capabilities();
2550
2551         /*
2552          * Check for sane CTR_EL0.CWG value.
2553          */
2554         cwg = cache_type_cwg();
2555         if (!cwg)
2556                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2557                         ARCH_DMA_MINALIGN);
2558 }
2559
2560 static bool __maybe_unused
2561 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2562 {
2563         return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
2564 }
2565
2566 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2567 {
2568         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2569 }
2570
2571 /*
2572  * We emulate only the following system register space.
2573  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2574  * See Table C5-6 System instruction encodings for System register accesses,
2575  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2576  */
2577 static inline bool __attribute_const__ is_emulated(u32 id)
2578 {
2579         return (sys_reg_Op0(id) == 0x3 &&
2580                 sys_reg_CRn(id) == 0x0 &&
2581                 sys_reg_Op1(id) == 0x0 &&
2582                 (sys_reg_CRm(id) == 0 ||
2583                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2584 }
2585
2586 /*
2587  * With CRm == 0, reg should be one of :
2588  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2589  */
2590 static inline int emulate_id_reg(u32 id, u64 *valp)
2591 {
2592         switch (id) {
2593         case SYS_MIDR_EL1:
2594                 *valp = read_cpuid_id();
2595                 break;
2596         case SYS_MPIDR_EL1:
2597                 *valp = SYS_MPIDR_SAFE_VAL;
2598                 break;
2599         case SYS_REVIDR_EL1:
2600                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2601                 *valp = 0;
2602                 break;
2603         default:
2604                 return -EINVAL;
2605         }
2606
2607         return 0;
2608 }
2609
2610 static int emulate_sys_reg(u32 id, u64 *valp)
2611 {
2612         struct arm64_ftr_reg *regp;
2613
2614         if (!is_emulated(id))
2615                 return -EINVAL;
2616
2617         if (sys_reg_CRm(id) == 0)
2618                 return emulate_id_reg(id, valp);
2619
2620         regp = get_arm64_ftr_reg(id);
2621         if (regp)
2622                 *valp = arm64_ftr_reg_user_value(regp);
2623         else
2624                 /*
2625                  * The untracked registers are either IMPLEMENTATION DEFINED
2626                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2627                  */
2628                 *valp = 0;
2629         return 0;
2630 }
2631
2632 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2633 {
2634         int rc;
2635         u64 val;
2636
2637         rc = emulate_sys_reg(sys_reg, &val);
2638         if (!rc) {
2639                 pt_regs_write_reg(regs, rt, val);
2640                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2641         }
2642         return rc;
2643 }
2644
2645 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2646 {
2647         u32 sys_reg, rt;
2648
2649         /*
2650          * sys_reg values are defined as used in mrs/msr instruction.
2651          * shift the imm value to get the encoding.
2652          */
2653         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2654         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2655         return do_emulate_mrs(regs, sys_reg, rt);
2656 }
2657
2658 static struct undef_hook mrs_hook = {
2659         .instr_mask = 0xfff00000,
2660         .instr_val  = 0xd5300000,
2661         .pstate_mask = PSR_AA32_MODE_MASK,
2662         .pstate_val = PSR_MODE_EL0t,
2663         .fn = emulate_mrs,
2664 };
2665
2666 static int __init enable_mrs_emulation(void)
2667 {
2668         register_undef_hook(&mrs_hook);
2669         return 0;
2670 }
2671
2672 core_initcall(enable_mrs_emulation);
2673
2674 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2675                           char *buf)
2676 {
2677         if (__meltdown_safe)
2678                 return sprintf(buf, "Not affected\n");
2679
2680         if (arm64_kernel_unmapped_at_el0())
2681                 return sprintf(buf, "Mitigation: PTI\n");
2682
2683         return sprintf(buf, "Vulnerable\n");
2684 }