976cb87b59be221109d91a50ee3069b54efac066
[muen/linux.git] / arch / arm64 / kernel / cpufeature.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Contains CPU feature definitions
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  *
7  * A note for the weary kernel hacker: the code here is confusing and hard to
8  * follow! That's partly because it's solving a nasty problem, but also because
9  * there's a little bit of over-abstraction that tends to obscure what's going
10  * on behind a maze of helper functions and macros.
11  *
12  * The basic problem is that hardware folks have started gluing together CPUs
13  * with distinct architectural features; in some cases even creating SoCs where
14  * user-visible instructions are available only on a subset of the available
15  * cores. We try to address this by snapshotting the feature registers of the
16  * boot CPU and comparing these with the feature registers of each secondary
17  * CPU when bringing them up. If there is a mismatch, then we update the
18  * snapshot state to indicate the lowest-common denominator of the feature,
19  * known as the "safe" value. This snapshot state can be queried to view the
20  * "sanitised" value of a feature register.
21  *
22  * The sanitised register values are used to decide which capabilities we
23  * have in the system. These may be in the form of traditional "hwcaps"
24  * advertised to userspace or internal "cpucaps" which are used to configure
25  * things like alternative patching and static keys. While a feature mismatch
26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27  * may prevent a CPU from being onlined at all.
28  *
29  * Some implementation details worth remembering:
30  *
31  * - Mismatched features are *always* sanitised to a "safe" value, which
32  *   usually indicates that the feature is not supported.
33  *
34  * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35  *   warning when onlining an offending CPU and the kernel will be tainted
36  *   with TAINT_CPU_OUT_OF_SPEC.
37  *
38  * - Features marked as FTR_VISIBLE have their sanitised value visible to
39  *   userspace. FTR_VISIBLE features in registers that are only visible
40  *   to EL0 by trapping *must* have a corresponding HWCAP so that late
41  *   onlining of CPUs cannot lead to features disappearing at runtime.
42  *
43  * - A "feature" is typically a 4-bit register field. A "capability" is the
44  *   high-level description derived from the sanitised field value.
45  *
46  * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47  *   scheme for fields in ID registers") to understand when feature fields
48  *   may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49  *
50  * - KVM exposes its own view of the feature registers to guest operating
51  *   systems regardless of FTR_VISIBLE. This is typically driven from the
52  *   sanitised register values to allow virtual CPUs to be migrated between
53  *   arbitrary physical CPUs, but some features not present on the host are
54  *   also advertised and emulated. Look at sys_reg_descs[] for the gory
55  *   details.
56  *
57  * - If the arm64_ftr_bits[] for a register has a missing field, then this
58  *   field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59  *   This is stronger than FTR_HIDDEN and can be used to hide features from
60  *   KVM guests.
61  */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/types.h>
71 #include <linux/mm.h>
72 #include <linux/cpu.h>
73 #include <asm/cpu.h>
74 #include <asm/cpufeature.h>
75 #include <asm/cpu_ops.h>
76 #include <asm/fpsimd.h>
77 #include <asm/mmu_context.h>
78 #include <asm/processor.h>
79 #include <asm/sysreg.h>
80 #include <asm/traps.h>
81 #include <asm/virt.h>
82
83 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
84 static unsigned long elf_hwcap __read_mostly;
85
86 #ifdef CONFIG_COMPAT
87 #define COMPAT_ELF_HWCAP_DEFAULT        \
88                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
89                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
90                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
91                                  COMPAT_HWCAP_LPAE)
92 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
93 unsigned int compat_elf_hwcap2 __read_mostly;
94 #endif
95
96 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
97 EXPORT_SYMBOL(cpu_hwcaps);
98 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
99
100 /* Need also bit for ARM64_CB_PATCH */
101 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
102
103 bool arm64_use_ng_mappings = false;
104 EXPORT_SYMBOL(arm64_use_ng_mappings);
105
106 /*
107  * Flag to indicate if we have computed the system wide
108  * capabilities based on the boot time active CPUs. This
109  * will be used to determine if a new booting CPU should
110  * go through the verification process to make sure that it
111  * supports the system capabilities, without using a hotplug
112  * notifier. This is also used to decide if we could use
113  * the fast path for checking constant CPU caps.
114  */
115 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
116 EXPORT_SYMBOL(arm64_const_caps_ready);
117 static inline void finalize_system_capabilities(void)
118 {
119         static_branch_enable(&arm64_const_caps_ready);
120 }
121
122 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
123 {
124         /* file-wide pr_fmt adds "CPU features: " prefix */
125         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
126         return 0;
127 }
128
129 static struct notifier_block cpu_hwcaps_notifier = {
130         .notifier_call = dump_cpu_hwcaps
131 };
132
133 static int __init register_cpu_hwcaps_dumper(void)
134 {
135         atomic_notifier_chain_register(&panic_notifier_list,
136                                        &cpu_hwcaps_notifier);
137         return 0;
138 }
139 __initcall(register_cpu_hwcaps_dumper);
140
141 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
142 EXPORT_SYMBOL(cpu_hwcap_keys);
143
144 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
145         {                                               \
146                 .sign = SIGNED,                         \
147                 .visible = VISIBLE,                     \
148                 .strict = STRICT,                       \
149                 .type = TYPE,                           \
150                 .shift = SHIFT,                         \
151                 .width = WIDTH,                         \
152                 .safe_val = SAFE_VAL,                   \
153         }
154
155 /* Define a feature with unsigned values */
156 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
158
159 /* Define a feature with a signed value */
160 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
161         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
162
163 #define ARM64_FTR_END                                   \
164         {                                               \
165                 .width = 0,                             \
166         }
167
168 /* meta feature for alternatives */
169 static bool __maybe_unused
170 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
171
172 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
173
174 static bool __system_matches_cap(unsigned int n);
175
176 /*
177  * NOTE: Any changes to the visibility of features should be kept in
178  * sync with the documentation of the CPU feature register ABI.
179  */
180 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
181         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
182         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
183         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
184         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
185         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
187         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
188         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
189         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
191         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
192         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
193         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
194         ARM64_FTR_END,
195 };
196
197 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
198         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
199         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
200         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
204         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
205                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
206         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
207                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
208         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
209         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
210         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
211         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
212                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
213         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
214                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
215         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
216         ARM64_FTR_END,
217 };
218
219 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
222         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
224         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
225                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
228         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
229         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
234         ARM64_FTR_END,
235 };
236
237 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
239         ARM64_FTR_END,
240 };
241
242 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
243         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
244                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
245         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
246                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
247         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
248                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
249         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
250                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
251         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
252                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
253         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
254                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
255         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
256                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
257         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
258                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
259         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
260                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
261         ARM64_FTR_END,
262 };
263
264 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
265         /*
266          * We already refuse to boot CPUs that don't support our configured
267          * page size, so we can only detect mismatches for a page size other
268          * than the one we're currently using. Unfortunately, SoCs like this
269          * exist in the wild so, even though we don't like it, we'll have to go
270          * along with it and treat them as non-strict.
271          */
272         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
273         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
275
276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
277         /* Linux shouldn't care about secure memory */
278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
281         /*
282          * Differing PARange is fine as long as all peripherals and memory are mapped
283          * within the minimum PARange of all CPUs
284          */
285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
286         ARM64_FTR_END,
287 };
288
289 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
296         ARM64_FTR_END,
297 };
298
299 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
302         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
308         ARM64_FTR_END,
309 };
310
311 static const struct arm64_ftr_bits ftr_ctr[] = {
312         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
313         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
314         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
315         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
316         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
317         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
318         /*
319          * Linux can handle differing I-cache policies. Userspace JITs will
320          * make use of *minLine.
321          * If we have differing I-cache policies, report it as the weakest - VIPT.
322          */
323         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
324         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
325         ARM64_FTR_END,
326 };
327
328 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
329         .name           = "SYS_CTR_EL0",
330         .ftr_bits       = ftr_ctr
331 };
332
333 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
334         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
339         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
342         ARM64_FTR_END,
343 };
344
345 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
346         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0),
347         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
351         /*
352          * We can instantiate multiple PMU instances with different levels
353          * of support.
354          */
355         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
358         ARM64_FTR_END,
359 };
360
361 static const struct arm64_ftr_bits ftr_mvfr2[] = {
362         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
363         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
364         ARM64_FTR_END,
365 };
366
367 static const struct arm64_ftr_bits ftr_dczid[] = {
368         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
369         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
370         ARM64_FTR_END,
371 };
372
373 static const struct arm64_ftr_bits ftr_id_isar0[] = {
374         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
375         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
376         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
377         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
378         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
379         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
380         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
381         ARM64_FTR_END,
382 };
383
384 static const struct arm64_ftr_bits ftr_id_isar5[] = {
385         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
386         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
387         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
388         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
389         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
390         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
391         ARM64_FTR_END,
392 };
393
394 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
395         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
396         ARM64_FTR_END,
397 };
398
399 static const struct arm64_ftr_bits ftr_id_isar4[] = {
400         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
401         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
402         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
403         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
404         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
405         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
406         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
407         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
408         ARM64_FTR_END,
409 };
410
411 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
412         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
413         ARM64_FTR_END,
414 };
415
416 static const struct arm64_ftr_bits ftr_id_isar6[] = {
417         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
418         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
419         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
420         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
421         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
422         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
423         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
424         ARM64_FTR_END,
425 };
426
427 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
428         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
429         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
430         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
431         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
432         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
433         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
434         ARM64_FTR_END,
435 };
436
437 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
438         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
439         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
440         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
441         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
442         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
443         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
444         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
445         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
446         ARM64_FTR_END,
447 };
448
449 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
450         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
451         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
452         ARM64_FTR_END,
453 };
454
455 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
456         /* [31:28] TraceFilt */
457         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
458         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
459         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
460         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
461         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
462         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
463         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
464         ARM64_FTR_END,
465 };
466
467 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
468         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
469         ARM64_FTR_END,
470 };
471
472 static const struct arm64_ftr_bits ftr_zcr[] = {
473         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
474                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
475         ARM64_FTR_END,
476 };
477
478 /*
479  * Common ftr bits for a 32bit register with all hidden, strict
480  * attributes, with 4bit feature fields and a default safe value of
481  * 0. Covers the following 32bit registers:
482  * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
483  */
484 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
485         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
486         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
487         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
488         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
489         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
490         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
491         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
492         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
493         ARM64_FTR_END,
494 };
495
496 /* Table for a single 32bit feature value */
497 static const struct arm64_ftr_bits ftr_single32[] = {
498         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
499         ARM64_FTR_END,
500 };
501
502 static const struct arm64_ftr_bits ftr_raz[] = {
503         ARM64_FTR_END,
504 };
505
506 #define ARM64_FTR_REG(id, table) {              \
507         .sys_id = id,                           \
508         .reg =  &(struct arm64_ftr_reg){        \
509                 .name = #id,                    \
510                 .ftr_bits = &((table)[0]),      \
511         }}
512
513 static const struct __ftr_reg_entry {
514         u32                     sys_id;
515         struct arm64_ftr_reg    *reg;
516 } arm64_ftr_regs[] = {
517
518         /* Op1 = 0, CRn = 0, CRm = 1 */
519         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
520         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
521         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
522         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
523         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
524         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
525         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
526
527         /* Op1 = 0, CRn = 0, CRm = 2 */
528         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
529         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
530         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
531         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
532         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
533         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
534         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
535         ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
536
537         /* Op1 = 0, CRn = 0, CRm = 3 */
538         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
539         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
540         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
541         ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
542         ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
543         ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
544
545         /* Op1 = 0, CRn = 0, CRm = 4 */
546         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
547         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
548         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
549
550         /* Op1 = 0, CRn = 0, CRm = 5 */
551         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
552         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
553
554         /* Op1 = 0, CRn = 0, CRm = 6 */
555         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
556         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
557
558         /* Op1 = 0, CRn = 0, CRm = 7 */
559         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
560         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
561         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
562
563         /* Op1 = 0, CRn = 1, CRm = 2 */
564         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
565
566         /* Op1 = 3, CRn = 0, CRm = 0 */
567         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
568         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
569
570         /* Op1 = 3, CRn = 14, CRm = 0 */
571         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
572 };
573
574 static int search_cmp_ftr_reg(const void *id, const void *regp)
575 {
576         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
577 }
578
579 /*
580  * get_arm64_ftr_reg - Lookup a feature register entry using its
581  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
582  * ascending order of sys_id , we use binary search to find a matching
583  * entry.
584  *
585  * returns - Upon success,  matching ftr_reg entry for id.
586  *         - NULL on failure. It is upto the caller to decide
587  *           the impact of a failure.
588  */
589 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
590 {
591         const struct __ftr_reg_entry *ret;
592
593         ret = bsearch((const void *)(unsigned long)sys_id,
594                         arm64_ftr_regs,
595                         ARRAY_SIZE(arm64_ftr_regs),
596                         sizeof(arm64_ftr_regs[0]),
597                         search_cmp_ftr_reg);
598         if (ret)
599                 return ret->reg;
600         return NULL;
601 }
602
603 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
604                                s64 ftr_val)
605 {
606         u64 mask = arm64_ftr_mask(ftrp);
607
608         reg &= ~mask;
609         reg |= (ftr_val << ftrp->shift) & mask;
610         return reg;
611 }
612
613 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
614                                 s64 cur)
615 {
616         s64 ret = 0;
617
618         switch (ftrp->type) {
619         case FTR_EXACT:
620                 ret = ftrp->safe_val;
621                 break;
622         case FTR_LOWER_SAFE:
623                 ret = new < cur ? new : cur;
624                 break;
625         case FTR_HIGHER_OR_ZERO_SAFE:
626                 if (!cur || !new)
627                         break;
628                 /* Fallthrough */
629         case FTR_HIGHER_SAFE:
630                 ret = new > cur ? new : cur;
631                 break;
632         default:
633                 BUG();
634         }
635
636         return ret;
637 }
638
639 static void __init sort_ftr_regs(void)
640 {
641         int i;
642
643         /* Check that the array is sorted so that we can do the binary search */
644         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
645                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
646 }
647
648 /*
649  * Initialise the CPU feature register from Boot CPU values.
650  * Also initiliases the strict_mask for the register.
651  * Any bits that are not covered by an arm64_ftr_bits entry are considered
652  * RES0 for the system-wide value, and must strictly match.
653  */
654 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
655 {
656         u64 val = 0;
657         u64 strict_mask = ~0x0ULL;
658         u64 user_mask = 0;
659         u64 valid_mask = 0;
660
661         const struct arm64_ftr_bits *ftrp;
662         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
663
664         BUG_ON(!reg);
665
666         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
667                 u64 ftr_mask = arm64_ftr_mask(ftrp);
668                 s64 ftr_new = arm64_ftr_value(ftrp, new);
669
670                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
671
672                 valid_mask |= ftr_mask;
673                 if (!ftrp->strict)
674                         strict_mask &= ~ftr_mask;
675                 if (ftrp->visible)
676                         user_mask |= ftr_mask;
677                 else
678                         reg->user_val = arm64_ftr_set_value(ftrp,
679                                                             reg->user_val,
680                                                             ftrp->safe_val);
681         }
682
683         val &= valid_mask;
684
685         reg->sys_val = val;
686         reg->strict_mask = strict_mask;
687         reg->user_mask = user_mask;
688 }
689
690 extern const struct arm64_cpu_capabilities arm64_errata[];
691 static const struct arm64_cpu_capabilities arm64_features[];
692
693 static void __init
694 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
695 {
696         for (; caps->matches; caps++) {
697                 if (WARN(caps->capability >= ARM64_NCAPS,
698                         "Invalid capability %d\n", caps->capability))
699                         continue;
700                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
701                         "Duplicate entry for capability %d\n",
702                         caps->capability))
703                         continue;
704                 cpu_hwcaps_ptrs[caps->capability] = caps;
705         }
706 }
707
708 static void __init init_cpu_hwcaps_indirect_list(void)
709 {
710         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
711         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
712 }
713
714 static void __init setup_boot_cpu_capabilities(void);
715
716 void __init init_cpu_features(struct cpuinfo_arm64 *info)
717 {
718         /* Before we start using the tables, make sure it is sorted */
719         sort_ftr_regs();
720
721         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
722         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
723         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
724         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
725         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
726         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
727         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
728         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
729         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
730         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
731         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
732         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
733         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
734
735         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
736                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
737                 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
738                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
739                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
740                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
741                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
742                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
743                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
744                 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
745                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
746                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
747                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
748                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
749                 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
750                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
751                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
752                 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
753                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
754                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
755                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
756         }
757
758         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
759                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
760                 sve_init_vq_map();
761         }
762
763         /*
764          * Initialize the indirect array of CPU hwcaps capabilities pointers
765          * before we handle the boot CPU below.
766          */
767         init_cpu_hwcaps_indirect_list();
768
769         /*
770          * Detect and enable early CPU capabilities based on the boot CPU,
771          * after we have initialised the CPU feature infrastructure.
772          */
773         setup_boot_cpu_capabilities();
774 }
775
776 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
777 {
778         const struct arm64_ftr_bits *ftrp;
779
780         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
781                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
782                 s64 ftr_new = arm64_ftr_value(ftrp, new);
783
784                 if (ftr_cur == ftr_new)
785                         continue;
786                 /* Find a safe value */
787                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
788                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
789         }
790
791 }
792
793 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
794 {
795         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
796
797         BUG_ON(!regp);
798         update_cpu_ftr_reg(regp, val);
799         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
800                 return 0;
801         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
802                         regp->name, boot, cpu, val);
803         return 1;
804 }
805
806 static void relax_cpu_ftr_reg(u32 sys_id, int field)
807 {
808         const struct arm64_ftr_bits *ftrp;
809         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
810
811         if (WARN_ON(!regp))
812                 return;
813
814         for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
815                 if (ftrp->shift == field) {
816                         regp->strict_mask &= ~arm64_ftr_mask(ftrp);
817                         break;
818                 }
819         }
820
821         /* Bogus field? */
822         WARN_ON(!ftrp->width);
823 }
824
825 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
826                                      struct cpuinfo_arm64 *boot)
827 {
828         int taint = 0;
829         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
830
831         /*
832          * If we don't have AArch32 at all then skip the checks entirely
833          * as the register values may be UNKNOWN and we're not going to be
834          * using them for anything.
835          */
836         if (!id_aa64pfr0_32bit_el0(pfr0))
837                 return taint;
838
839         /*
840          * If we don't have AArch32 at EL1, then relax the strictness of
841          * EL1-dependent register fields to avoid spurious sanity check fails.
842          */
843         if (!id_aa64pfr0_32bit_el1(pfr0)) {
844                 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
845                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
846                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
847                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
848                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
849                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
850         }
851
852         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
853                                       info->reg_id_dfr0, boot->reg_id_dfr0);
854         taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
855                                       info->reg_id_dfr1, boot->reg_id_dfr1);
856         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
857                                       info->reg_id_isar0, boot->reg_id_isar0);
858         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
859                                       info->reg_id_isar1, boot->reg_id_isar1);
860         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
861                                       info->reg_id_isar2, boot->reg_id_isar2);
862         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
863                                       info->reg_id_isar3, boot->reg_id_isar3);
864         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
865                                       info->reg_id_isar4, boot->reg_id_isar4);
866         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
867                                       info->reg_id_isar5, boot->reg_id_isar5);
868         taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
869                                       info->reg_id_isar6, boot->reg_id_isar6);
870
871         /*
872          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
873          * ACTLR formats could differ across CPUs and therefore would have to
874          * be trapped for virtualization anyway.
875          */
876         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
877                                       info->reg_id_mmfr0, boot->reg_id_mmfr0);
878         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
879                                       info->reg_id_mmfr1, boot->reg_id_mmfr1);
880         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
881                                       info->reg_id_mmfr2, boot->reg_id_mmfr2);
882         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
883                                       info->reg_id_mmfr3, boot->reg_id_mmfr3);
884         taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
885                                       info->reg_id_mmfr5, boot->reg_id_mmfr5);
886         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
887                                       info->reg_id_pfr0, boot->reg_id_pfr0);
888         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
889                                       info->reg_id_pfr1, boot->reg_id_pfr1);
890         taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
891                                       info->reg_id_pfr2, boot->reg_id_pfr2);
892         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
893                                       info->reg_mvfr0, boot->reg_mvfr0);
894         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
895                                       info->reg_mvfr1, boot->reg_mvfr1);
896         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
897                                       info->reg_mvfr2, boot->reg_mvfr2);
898
899         return taint;
900 }
901
902 /*
903  * Update system wide CPU feature registers with the values from a
904  * non-boot CPU. Also performs SANITY checks to make sure that there
905  * aren't any insane variations from that of the boot CPU.
906  */
907 void update_cpu_features(int cpu,
908                          struct cpuinfo_arm64 *info,
909                          struct cpuinfo_arm64 *boot)
910 {
911         int taint = 0;
912
913         /*
914          * The kernel can handle differing I-cache policies, but otherwise
915          * caches should look identical. Userspace JITs will make use of
916          * *minLine.
917          */
918         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
919                                       info->reg_ctr, boot->reg_ctr);
920
921         /*
922          * Userspace may perform DC ZVA instructions. Mismatched block sizes
923          * could result in too much or too little memory being zeroed if a
924          * process is preempted and migrated between CPUs.
925          */
926         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
927                                       info->reg_dczid, boot->reg_dczid);
928
929         /* If different, timekeeping will be broken (especially with KVM) */
930         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
931                                       info->reg_cntfrq, boot->reg_cntfrq);
932
933         /*
934          * The kernel uses self-hosted debug features and expects CPUs to
935          * support identical debug features. We presently need CTX_CMPs, WRPs,
936          * and BRPs to be identical.
937          * ID_AA64DFR1 is currently RES0.
938          */
939         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
940                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
941         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
942                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
943         /*
944          * Even in big.LITTLE, processors should be identical instruction-set
945          * wise.
946          */
947         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
948                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
949         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
950                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
951
952         /*
953          * Differing PARange support is fine as long as all peripherals and
954          * memory are mapped within the minimum PARange of all CPUs.
955          * Linux should not care about secure memory.
956          */
957         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
958                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
959         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
960                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
961         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
962                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
963
964         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
965                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
966         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
967                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
968
969         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
970                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
971
972         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
973                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
974                                         info->reg_zcr, boot->reg_zcr);
975
976                 /* Probe vector lengths, unless we already gave up on SVE */
977                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
978                     !system_capabilities_finalized())
979                         sve_update_vq_map();
980         }
981
982         /*
983          * This relies on a sanitised view of the AArch64 ID registers
984          * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
985          */
986         taint |= update_32bit_cpu_features(cpu, info, boot);
987
988         /*
989          * Mismatched CPU features are a recipe for disaster. Don't even
990          * pretend to support them.
991          */
992         if (taint) {
993                 pr_warn_once("Unsupported CPU feature variation detected.\n");
994                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
995         }
996 }
997
998 u64 read_sanitised_ftr_reg(u32 id)
999 {
1000         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1001
1002         /* We shouldn't get a request for an unsupported register */
1003         BUG_ON(!regp);
1004         return regp->sys_val;
1005 }
1006
1007 #define read_sysreg_case(r)     \
1008         case r:         return read_sysreg_s(r)
1009
1010 /*
1011  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1012  * Read the system register on the current CPU
1013  */
1014 static u64 __read_sysreg_by_encoding(u32 sys_id)
1015 {
1016         switch (sys_id) {
1017         read_sysreg_case(SYS_ID_PFR0_EL1);
1018         read_sysreg_case(SYS_ID_PFR1_EL1);
1019         read_sysreg_case(SYS_ID_PFR2_EL1);
1020         read_sysreg_case(SYS_ID_DFR0_EL1);
1021         read_sysreg_case(SYS_ID_DFR1_EL1);
1022         read_sysreg_case(SYS_ID_MMFR0_EL1);
1023         read_sysreg_case(SYS_ID_MMFR1_EL1);
1024         read_sysreg_case(SYS_ID_MMFR2_EL1);
1025         read_sysreg_case(SYS_ID_MMFR3_EL1);
1026         read_sysreg_case(SYS_ID_MMFR5_EL1);
1027         read_sysreg_case(SYS_ID_ISAR0_EL1);
1028         read_sysreg_case(SYS_ID_ISAR1_EL1);
1029         read_sysreg_case(SYS_ID_ISAR2_EL1);
1030         read_sysreg_case(SYS_ID_ISAR3_EL1);
1031         read_sysreg_case(SYS_ID_ISAR4_EL1);
1032         read_sysreg_case(SYS_ID_ISAR5_EL1);
1033         read_sysreg_case(SYS_ID_ISAR6_EL1);
1034         read_sysreg_case(SYS_MVFR0_EL1);
1035         read_sysreg_case(SYS_MVFR1_EL1);
1036         read_sysreg_case(SYS_MVFR2_EL1);
1037
1038         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1039         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1040         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1041         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1042         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1043         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1044         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1045         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1046         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1047         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1048
1049         read_sysreg_case(SYS_CNTFRQ_EL0);
1050         read_sysreg_case(SYS_CTR_EL0);
1051         read_sysreg_case(SYS_DCZID_EL0);
1052
1053         default:
1054                 BUG();
1055                 return 0;
1056         }
1057 }
1058
1059 #include <linux/irqchip/arm-gic-v3.h>
1060
1061 static bool
1062 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1063 {
1064         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1065
1066         return val >= entry->min_field_value;
1067 }
1068
1069 static bool
1070 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1071 {
1072         u64 val;
1073
1074         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1075         if (scope == SCOPE_SYSTEM)
1076                 val = read_sanitised_ftr_reg(entry->sys_reg);
1077         else
1078                 val = __read_sysreg_by_encoding(entry->sys_reg);
1079
1080         return feature_matches(val, entry);
1081 }
1082
1083 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1084 {
1085         bool has_sre;
1086
1087         if (!has_cpuid_feature(entry, scope))
1088                 return false;
1089
1090         has_sre = gic_enable_sre();
1091         if (!has_sre)
1092                 pr_warn_once("%s present but disabled by higher exception level\n",
1093                              entry->desc);
1094
1095         return has_sre;
1096 }
1097
1098 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1099 {
1100         u32 midr = read_cpuid_id();
1101
1102         /* Cavium ThunderX pass 1.x and 2.x */
1103         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1104                 MIDR_CPU_VAR_REV(0, 0),
1105                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1106 }
1107
1108 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1109 {
1110         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1111
1112         return cpuid_feature_extract_signed_field(pfr0,
1113                                         ID_AA64PFR0_FP_SHIFT) < 0;
1114 }
1115
1116 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1117                           int scope)
1118 {
1119         u64 ctr;
1120
1121         if (scope == SCOPE_SYSTEM)
1122                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1123         else
1124                 ctr = read_cpuid_effective_cachetype();
1125
1126         return ctr & BIT(CTR_IDC_SHIFT);
1127 }
1128
1129 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1130 {
1131         /*
1132          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1133          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1134          * to the CTR_EL0 on this CPU and emulate it with the real/safe
1135          * value.
1136          */
1137         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1138                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1139 }
1140
1141 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1142                           int scope)
1143 {
1144         u64 ctr;
1145
1146         if (scope == SCOPE_SYSTEM)
1147                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1148         else
1149                 ctr = read_cpuid_cachetype();
1150
1151         return ctr & BIT(CTR_DIC_SHIFT);
1152 }
1153
1154 static bool __maybe_unused
1155 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1156 {
1157         /*
1158          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1159          * may share TLB entries with a CPU stuck in the crashed
1160          * kernel.
1161          */
1162          if (is_kdump_kernel())
1163                 return false;
1164
1165         return has_cpuid_feature(entry, scope);
1166 }
1167
1168 /*
1169  * This check is triggered during the early boot before the cpufeature
1170  * is initialised. Checking the status on the local CPU allows the boot
1171  * CPU to detect the need for non-global mappings and thus avoiding a
1172  * pagetable re-write after all the CPUs are booted. This check will be
1173  * anyway run on individual CPUs, allowing us to get the consistent
1174  * state once the SMP CPUs are up and thus make the switch to non-global
1175  * mappings if required.
1176  */
1177 bool kaslr_requires_kpti(void)
1178 {
1179         if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1180                 return false;
1181
1182         /*
1183          * E0PD does a similar job to KPTI so can be used instead
1184          * where available.
1185          */
1186         if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1187                 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1188                 if (cpuid_feature_extract_unsigned_field(mmfr2,
1189                                                 ID_AA64MMFR2_E0PD_SHIFT))
1190                         return false;
1191         }
1192
1193         /*
1194          * Systems affected by Cavium erratum 24756 are incompatible
1195          * with KPTI.
1196          */
1197         if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1198                 extern const struct midr_range cavium_erratum_27456_cpus[];
1199
1200                 if (is_midr_in_range_list(read_cpuid_id(),
1201                                           cavium_erratum_27456_cpus))
1202                         return false;
1203         }
1204
1205         return kaslr_offset() > 0;
1206 }
1207
1208 static bool __meltdown_safe = true;
1209 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1210
1211 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1212                                 int scope)
1213 {
1214         /* List of CPUs that are not vulnerable and don't need KPTI */
1215         static const struct midr_range kpti_safe_list[] = {
1216                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1217                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1218                 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1219                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1220                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1221                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1222                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1223                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1224                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1225                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1226                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1227                 { /* sentinel */ }
1228         };
1229         char const *str = "kpti command line option";
1230         bool meltdown_safe;
1231
1232         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1233
1234         /* Defer to CPU feature registers */
1235         if (has_cpuid_feature(entry, scope))
1236                 meltdown_safe = true;
1237
1238         if (!meltdown_safe)
1239                 __meltdown_safe = false;
1240
1241         /*
1242          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1243          * ThunderX leads to apparent I-cache corruption of kernel text, which
1244          * ends as well as you might imagine. Don't even try.
1245          */
1246         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1247                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1248                 __kpti_forced = -1;
1249         }
1250
1251         /* Useful for KASLR robustness */
1252         if (kaslr_requires_kpti()) {
1253                 if (!__kpti_forced) {
1254                         str = "KASLR";
1255                         __kpti_forced = 1;
1256                 }
1257         }
1258
1259         if (cpu_mitigations_off() && !__kpti_forced) {
1260                 str = "mitigations=off";
1261                 __kpti_forced = -1;
1262         }
1263
1264         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1265                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1266                 return false;
1267         }
1268
1269         /* Forced? */
1270         if (__kpti_forced) {
1271                 pr_info_once("kernel page table isolation forced %s by %s\n",
1272                              __kpti_forced > 0 ? "ON" : "OFF", str);
1273                 return __kpti_forced > 0;
1274         }
1275
1276         return !meltdown_safe;
1277 }
1278
1279 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1280 static void
1281 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1282 {
1283         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1284         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1285         kpti_remap_fn *remap_fn;
1286
1287         int cpu = smp_processor_id();
1288
1289         /*
1290          * We don't need to rewrite the page-tables if either we've done
1291          * it already or we have KASLR enabled and therefore have not
1292          * created any global mappings at all.
1293          */
1294         if (arm64_use_ng_mappings)
1295                 return;
1296
1297         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1298
1299         cpu_install_idmap();
1300         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1301         cpu_uninstall_idmap();
1302
1303         if (!cpu)
1304                 arm64_use_ng_mappings = true;
1305
1306         return;
1307 }
1308 #else
1309 static void
1310 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1311 {
1312 }
1313 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1314
1315 static int __init parse_kpti(char *str)
1316 {
1317         bool enabled;
1318         int ret = strtobool(str, &enabled);
1319
1320         if (ret)
1321                 return ret;
1322
1323         __kpti_forced = enabled ? 1 : -1;
1324         return 0;
1325 }
1326 early_param("kpti", parse_kpti);
1327
1328 #ifdef CONFIG_ARM64_HW_AFDBM
1329 static inline void __cpu_enable_hw_dbm(void)
1330 {
1331         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1332
1333         write_sysreg(tcr, tcr_el1);
1334         isb();
1335 }
1336
1337 static bool cpu_has_broken_dbm(void)
1338 {
1339         /* List of CPUs which have broken DBM support. */
1340         static const struct midr_range cpus[] = {
1341 #ifdef CONFIG_ARM64_ERRATUM_1024718
1342                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1343 #endif
1344                 {},
1345         };
1346
1347         return is_midr_in_range_list(read_cpuid_id(), cpus);
1348 }
1349
1350 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1351 {
1352         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1353                !cpu_has_broken_dbm();
1354 }
1355
1356 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1357 {
1358         if (cpu_can_use_dbm(cap))
1359                 __cpu_enable_hw_dbm();
1360 }
1361
1362 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1363                        int __unused)
1364 {
1365         static bool detected = false;
1366         /*
1367          * DBM is a non-conflicting feature. i.e, the kernel can safely
1368          * run a mix of CPUs with and without the feature. So, we
1369          * unconditionally enable the capability to allow any late CPU
1370          * to use the feature. We only enable the control bits on the
1371          * CPU, if it actually supports.
1372          *
1373          * We have to make sure we print the "feature" detection only
1374          * when at least one CPU actually uses it. So check if this CPU
1375          * can actually use it and print the message exactly once.
1376          *
1377          * This is safe as all CPUs (including secondary CPUs - due to the
1378          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1379          * goes through the "matches" check exactly once. Also if a CPU
1380          * matches the criteria, it is guaranteed that the CPU will turn
1381          * the DBM on, as the capability is unconditionally enabled.
1382          */
1383         if (!detected && cpu_can_use_dbm(cap)) {
1384                 detected = true;
1385                 pr_info("detected: Hardware dirty bit management\n");
1386         }
1387
1388         return true;
1389 }
1390
1391 #endif
1392
1393 #ifdef CONFIG_ARM64_AMU_EXTN
1394
1395 /*
1396  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1397  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1398  * information regarding all the events that it supports. When a CPU bit is
1399  * set in the cpumask, the user of this feature can only rely on the presence
1400  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1401  * counters are enabled or access to these counters is enabled by code
1402  * executed at higher exception levels (firmware).
1403  */
1404 static struct cpumask amu_cpus __read_mostly;
1405
1406 bool cpu_has_amu_feat(int cpu)
1407 {
1408         return cpumask_test_cpu(cpu, &amu_cpus);
1409 }
1410
1411 /* Initialize the use of AMU counters for frequency invariance */
1412 extern void init_cpu_freq_invariance_counters(void);
1413
1414 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1415 {
1416         if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1417                 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1418                         smp_processor_id());
1419                 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1420                 init_cpu_freq_invariance_counters();
1421         }
1422 }
1423
1424 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1425                     int __unused)
1426 {
1427         /*
1428          * The AMU extension is a non-conflicting feature: the kernel can
1429          * safely run a mix of CPUs with and without support for the
1430          * activity monitors extension. Therefore, unconditionally enable
1431          * the capability to allow any late CPU to use the feature.
1432          *
1433          * With this feature unconditionally enabled, the cpu_enable
1434          * function will be called for all CPUs that match the criteria,
1435          * including secondary and hotplugged, marking this feature as
1436          * present on that respective CPU. The enable function will also
1437          * print a detection message.
1438          */
1439
1440         return true;
1441 }
1442 #endif
1443
1444 #ifdef CONFIG_ARM64_VHE
1445 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1446 {
1447         return is_kernel_in_hyp_mode();
1448 }
1449
1450 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1451 {
1452         /*
1453          * Copy register values that aren't redirected by hardware.
1454          *
1455          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1456          * this value to tpidr_el2 before we patch the code. Once we've done
1457          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1458          * do anything here.
1459          */
1460         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1461                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1462 }
1463 #endif
1464
1465 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1466 {
1467         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1468
1469         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1470         WARN_ON(val & (7 << 27 | 7 << 21));
1471 }
1472
1473 #ifdef CONFIG_ARM64_SSBD
1474 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1475 {
1476         if (user_mode(regs))
1477                 return 1;
1478
1479         if (instr & BIT(PSTATE_Imm_shift))
1480                 regs->pstate |= PSR_SSBS_BIT;
1481         else
1482                 regs->pstate &= ~PSR_SSBS_BIT;
1483
1484         arm64_skip_faulting_instruction(regs, 4);
1485         return 0;
1486 }
1487
1488 static struct undef_hook ssbs_emulation_hook = {
1489         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1490         .instr_val      = 0xd500401f | PSTATE_SSBS,
1491         .fn             = ssbs_emulation_handler,
1492 };
1493
1494 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1495 {
1496         static bool undef_hook_registered = false;
1497         static DEFINE_RAW_SPINLOCK(hook_lock);
1498
1499         raw_spin_lock(&hook_lock);
1500         if (!undef_hook_registered) {
1501                 register_undef_hook(&ssbs_emulation_hook);
1502                 undef_hook_registered = true;
1503         }
1504         raw_spin_unlock(&hook_lock);
1505
1506         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1507                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1508                 arm64_set_ssbd_mitigation(false);
1509         } else {
1510                 arm64_set_ssbd_mitigation(true);
1511         }
1512 }
1513 #endif /* CONFIG_ARM64_SSBD */
1514
1515 #ifdef CONFIG_ARM64_PAN
1516 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1517 {
1518         /*
1519          * We modify PSTATE. This won't work from irq context as the PSTATE
1520          * is discarded once we return from the exception.
1521          */
1522         WARN_ON_ONCE(in_interrupt());
1523
1524         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1525         asm(SET_PSTATE_PAN(1));
1526 }
1527 #endif /* CONFIG_ARM64_PAN */
1528
1529 #ifdef CONFIG_ARM64_RAS_EXTN
1530 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1531 {
1532         /* Firmware may have left a deferred SError in this register. */
1533         write_sysreg_s(0, SYS_DISR_EL1);
1534 }
1535 #endif /* CONFIG_ARM64_RAS_EXTN */
1536
1537 #ifdef CONFIG_ARM64_PTR_AUTH
1538 static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
1539                              int __unused)
1540 {
1541         return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
1542                __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF);
1543 }
1544
1545 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1546                              int __unused)
1547 {
1548         return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1549                __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1550 }
1551 #endif /* CONFIG_ARM64_PTR_AUTH */
1552
1553 #ifdef CONFIG_ARM64_E0PD
1554 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1555 {
1556         if (this_cpu_has_cap(ARM64_HAS_E0PD))
1557                 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1558 }
1559 #endif /* CONFIG_ARM64_E0PD */
1560
1561 #ifdef CONFIG_ARM64_PSEUDO_NMI
1562 static bool enable_pseudo_nmi;
1563
1564 static int __init early_enable_pseudo_nmi(char *p)
1565 {
1566         return strtobool(p, &enable_pseudo_nmi);
1567 }
1568 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1569
1570 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1571                                    int scope)
1572 {
1573         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1574 }
1575 #endif
1576
1577 /* Internal helper functions to match cpu capability type */
1578 static bool
1579 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1580 {
1581         return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1582 }
1583
1584 static bool
1585 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1586 {
1587         return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1588 }
1589
1590 static bool
1591 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1592 {
1593         return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1594 }
1595
1596 static const struct arm64_cpu_capabilities arm64_features[] = {
1597         {
1598                 .desc = "GIC system register CPU interface",
1599                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1600                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1601                 .matches = has_useable_gicv3_cpuif,
1602                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1603                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1604                 .sign = FTR_UNSIGNED,
1605                 .min_field_value = 1,
1606         },
1607 #ifdef CONFIG_ARM64_PAN
1608         {
1609                 .desc = "Privileged Access Never",
1610                 .capability = ARM64_HAS_PAN,
1611                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1612                 .matches = has_cpuid_feature,
1613                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1614                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1615                 .sign = FTR_UNSIGNED,
1616                 .min_field_value = 1,
1617                 .cpu_enable = cpu_enable_pan,
1618         },
1619 #endif /* CONFIG_ARM64_PAN */
1620 #ifdef CONFIG_ARM64_LSE_ATOMICS
1621         {
1622                 .desc = "LSE atomic instructions",
1623                 .capability = ARM64_HAS_LSE_ATOMICS,
1624                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1625                 .matches = has_cpuid_feature,
1626                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1627                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1628                 .sign = FTR_UNSIGNED,
1629                 .min_field_value = 2,
1630         },
1631 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1632         {
1633                 .desc = "Software prefetching using PRFM",
1634                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1635                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1636                 .matches = has_no_hw_prefetch,
1637         },
1638 #ifdef CONFIG_ARM64_UAO
1639         {
1640                 .desc = "User Access Override",
1641                 .capability = ARM64_HAS_UAO,
1642                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1643                 .matches = has_cpuid_feature,
1644                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1645                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1646                 .min_field_value = 1,
1647                 /*
1648                  * We rely on stop_machine() calling uao_thread_switch() to set
1649                  * UAO immediately after patching.
1650                  */
1651         },
1652 #endif /* CONFIG_ARM64_UAO */
1653 #ifdef CONFIG_ARM64_PAN
1654         {
1655                 .capability = ARM64_ALT_PAN_NOT_UAO,
1656                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1657                 .matches = cpufeature_pan_not_uao,
1658         },
1659 #endif /* CONFIG_ARM64_PAN */
1660 #ifdef CONFIG_ARM64_VHE
1661         {
1662                 .desc = "Virtualization Host Extensions",
1663                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1664                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1665                 .matches = runs_at_el2,
1666                 .cpu_enable = cpu_copy_el2regs,
1667         },
1668 #endif  /* CONFIG_ARM64_VHE */
1669         {
1670                 .desc = "32-bit EL0 Support",
1671                 .capability = ARM64_HAS_32BIT_EL0,
1672                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1673                 .matches = has_cpuid_feature,
1674                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1675                 .sign = FTR_UNSIGNED,
1676                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1677                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1678         },
1679 #ifdef CONFIG_KVM
1680         {
1681                 .desc = "32-bit EL1 Support",
1682                 .capability = ARM64_HAS_32BIT_EL1,
1683                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1684                 .matches = has_cpuid_feature,
1685                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1686                 .sign = FTR_UNSIGNED,
1687                 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1688                 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1689         },
1690 #endif
1691         {
1692                 .desc = "Kernel page table isolation (KPTI)",
1693                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1694                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1695                 /*
1696                  * The ID feature fields below are used to indicate that
1697                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1698                  * more details.
1699                  */
1700                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1701                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1702                 .min_field_value = 1,
1703                 .matches = unmap_kernel_at_el0,
1704                 .cpu_enable = kpti_install_ng_mappings,
1705         },
1706         {
1707                 /* FP/SIMD is not implemented */
1708                 .capability = ARM64_HAS_NO_FPSIMD,
1709                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1710                 .min_field_value = 0,
1711                 .matches = has_no_fpsimd,
1712         },
1713 #ifdef CONFIG_ARM64_PMEM
1714         {
1715                 .desc = "Data cache clean to Point of Persistence",
1716                 .capability = ARM64_HAS_DCPOP,
1717                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1718                 .matches = has_cpuid_feature,
1719                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1720                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1721                 .min_field_value = 1,
1722         },
1723         {
1724                 .desc = "Data cache clean to Point of Deep Persistence",
1725                 .capability = ARM64_HAS_DCPODP,
1726                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1727                 .matches = has_cpuid_feature,
1728                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1729                 .sign = FTR_UNSIGNED,
1730                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1731                 .min_field_value = 2,
1732         },
1733 #endif
1734 #ifdef CONFIG_ARM64_SVE
1735         {
1736                 .desc = "Scalable Vector Extension",
1737                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1738                 .capability = ARM64_SVE,
1739                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1740                 .sign = FTR_UNSIGNED,
1741                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1742                 .min_field_value = ID_AA64PFR0_SVE,
1743                 .matches = has_cpuid_feature,
1744                 .cpu_enable = sve_kernel_enable,
1745         },
1746 #endif /* CONFIG_ARM64_SVE */
1747 #ifdef CONFIG_ARM64_RAS_EXTN
1748         {
1749                 .desc = "RAS Extension Support",
1750                 .capability = ARM64_HAS_RAS_EXTN,
1751                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1752                 .matches = has_cpuid_feature,
1753                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1754                 .sign = FTR_UNSIGNED,
1755                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1756                 .min_field_value = ID_AA64PFR0_RAS_V1,
1757                 .cpu_enable = cpu_clear_disr,
1758         },
1759 #endif /* CONFIG_ARM64_RAS_EXTN */
1760 #ifdef CONFIG_ARM64_AMU_EXTN
1761         {
1762                 /*
1763                  * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1764                  * Therefore, don't provide .desc as we don't want the detection
1765                  * message to be shown until at least one CPU is detected to
1766                  * support the feature.
1767                  */
1768                 .capability = ARM64_HAS_AMU_EXTN,
1769                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1770                 .matches = has_amu,
1771                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1772                 .sign = FTR_UNSIGNED,
1773                 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1774                 .min_field_value = ID_AA64PFR0_AMU,
1775                 .cpu_enable = cpu_amu_enable,
1776         },
1777 #endif /* CONFIG_ARM64_AMU_EXTN */
1778         {
1779                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1780                 .capability = ARM64_HAS_CACHE_IDC,
1781                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1782                 .matches = has_cache_idc,
1783                 .cpu_enable = cpu_emulate_effective_ctr,
1784         },
1785         {
1786                 .desc = "Instruction cache invalidation not required for I/D coherence",
1787                 .capability = ARM64_HAS_CACHE_DIC,
1788                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1789                 .matches = has_cache_dic,
1790         },
1791         {
1792                 .desc = "Stage-2 Force Write-Back",
1793                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1794                 .capability = ARM64_HAS_STAGE2_FWB,
1795                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1796                 .sign = FTR_UNSIGNED,
1797                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1798                 .min_field_value = 1,
1799                 .matches = has_cpuid_feature,
1800                 .cpu_enable = cpu_has_fwb,
1801         },
1802 #ifdef CONFIG_ARM64_HW_AFDBM
1803         {
1804                 /*
1805                  * Since we turn this on always, we don't want the user to
1806                  * think that the feature is available when it may not be.
1807                  * So hide the description.
1808                  *
1809                  * .desc = "Hardware pagetable Dirty Bit Management",
1810                  *
1811                  */
1812                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1813                 .capability = ARM64_HW_DBM,
1814                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1815                 .sign = FTR_UNSIGNED,
1816                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1817                 .min_field_value = 2,
1818                 .matches = has_hw_dbm,
1819                 .cpu_enable = cpu_enable_hw_dbm,
1820         },
1821 #endif
1822         {
1823                 .desc = "CRC32 instructions",
1824                 .capability = ARM64_HAS_CRC32,
1825                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1826                 .matches = has_cpuid_feature,
1827                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1828                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1829                 .min_field_value = 1,
1830         },
1831 #ifdef CONFIG_ARM64_SSBD
1832         {
1833                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1834                 .capability = ARM64_SSBS,
1835                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1836                 .matches = has_cpuid_feature,
1837                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1838                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1839                 .sign = FTR_UNSIGNED,
1840                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1841                 .cpu_enable = cpu_enable_ssbs,
1842         },
1843 #endif
1844 #ifdef CONFIG_ARM64_CNP
1845         {
1846                 .desc = "Common not Private translations",
1847                 .capability = ARM64_HAS_CNP,
1848                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1849                 .matches = has_useable_cnp,
1850                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1851                 .sign = FTR_UNSIGNED,
1852                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1853                 .min_field_value = 1,
1854                 .cpu_enable = cpu_enable_cnp,
1855         },
1856 #endif
1857         {
1858                 .desc = "Speculation barrier (SB)",
1859                 .capability = ARM64_HAS_SB,
1860                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1861                 .matches = has_cpuid_feature,
1862                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1863                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1864                 .sign = FTR_UNSIGNED,
1865                 .min_field_value = 1,
1866         },
1867 #ifdef CONFIG_ARM64_PTR_AUTH
1868         {
1869                 .desc = "Address authentication (architected algorithm)",
1870                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1871                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1872                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1873                 .sign = FTR_UNSIGNED,
1874                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1875                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1876                 .matches = has_cpuid_feature,
1877         },
1878         {
1879                 .desc = "Address authentication (IMP DEF algorithm)",
1880                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1881                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1882                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1883                 .sign = FTR_UNSIGNED,
1884                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1885                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1886                 .matches = has_cpuid_feature,
1887         },
1888         {
1889                 .capability = ARM64_HAS_ADDRESS_AUTH,
1890                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1891                 .matches = has_address_auth,
1892         },
1893         {
1894                 .desc = "Generic authentication (architected algorithm)",
1895                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1896                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1897                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1898                 .sign = FTR_UNSIGNED,
1899                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1900                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1901                 .matches = has_cpuid_feature,
1902         },
1903         {
1904                 .desc = "Generic authentication (IMP DEF algorithm)",
1905                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1906                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1907                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1908                 .sign = FTR_UNSIGNED,
1909                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1910                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1911                 .matches = has_cpuid_feature,
1912         },
1913         {
1914                 .capability = ARM64_HAS_GENERIC_AUTH,
1915                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1916                 .matches = has_generic_auth,
1917         },
1918 #endif /* CONFIG_ARM64_PTR_AUTH */
1919 #ifdef CONFIG_ARM64_PSEUDO_NMI
1920         {
1921                 /*
1922                  * Depends on having GICv3
1923                  */
1924                 .desc = "IRQ priority masking",
1925                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1926                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1927                 .matches = can_use_gic_priorities,
1928                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1929                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1930                 .sign = FTR_UNSIGNED,
1931                 .min_field_value = 1,
1932         },
1933 #endif
1934 #ifdef CONFIG_ARM64_E0PD
1935         {
1936                 .desc = "E0PD",
1937                 .capability = ARM64_HAS_E0PD,
1938                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1939                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1940                 .sign = FTR_UNSIGNED,
1941                 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1942                 .matches = has_cpuid_feature,
1943                 .min_field_value = 1,
1944                 .cpu_enable = cpu_enable_e0pd,
1945         },
1946 #endif
1947 #ifdef CONFIG_ARCH_RANDOM
1948         {
1949                 .desc = "Random Number Generator",
1950                 .capability = ARM64_HAS_RNG,
1951                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1952                 .matches = has_cpuid_feature,
1953                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1954                 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1955                 .sign = FTR_UNSIGNED,
1956                 .min_field_value = 1,
1957         },
1958 #endif
1959         {},
1960 };
1961
1962 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1963                 .matches = has_cpuid_feature,                                   \
1964                 .sys_reg = reg,                                                 \
1965                 .field_pos = field,                                             \
1966                 .sign = s,                                                      \
1967                 .min_field_value = min_value,
1968
1969 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1970                 .desc = name,                                                   \
1971                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1972                 .hwcap_type = cap_type,                                         \
1973                 .hwcap = cap,                                                   \
1974
1975 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1976         {                                                                       \
1977                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1978                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1979         }
1980
1981 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1982         {                                                                       \
1983                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1984                 .matches = cpucap_multi_entry_cap_matches,                      \
1985                 .match_list = list,                                             \
1986         }
1987
1988 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
1989         {                                                                       \
1990                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1991                 .matches = match,                                               \
1992         }
1993
1994 #ifdef CONFIG_ARM64_PTR_AUTH
1995 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1996         {
1997                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1998                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1999         },
2000         {
2001                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2002                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2003         },
2004         {},
2005 };
2006
2007 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2008         {
2009                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2010                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2011         },
2012         {
2013                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2014                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2015         },
2016         {},
2017 };
2018 #endif
2019
2020 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2021         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2022         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2023         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2024         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2025         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2026         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2027         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2028         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2029         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2030         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2031         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2032         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2033         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2034         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2035         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2036         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2037         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2038         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2039         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2040         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2041         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2042         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2043         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2044         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2045         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2046         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2047         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2048         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2049         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2050         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2051         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2052         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2053         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2054 #ifdef CONFIG_ARM64_SVE
2055         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2056         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2057         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2058         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2059         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2060         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2061         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2062         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2063         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2064         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2065         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2066 #endif
2067         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2068 #ifdef CONFIG_ARM64_PTR_AUTH
2069         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2070         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2071 #endif
2072         {},
2073 };
2074
2075 #ifdef CONFIG_COMPAT
2076 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2077 {
2078         /*
2079          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2080          * in line with that of arm32 as in vfp_init(). We make sure that the
2081          * check is future proof, by making sure value is non-zero.
2082          */
2083         u32 mvfr1;
2084
2085         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2086         if (scope == SCOPE_SYSTEM)
2087                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2088         else
2089                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2090
2091         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2092                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2093                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2094 }
2095 #endif
2096
2097 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2098 #ifdef CONFIG_COMPAT
2099         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2100         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2101         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2102         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2103         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2104         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2105         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2106         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2107         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2108         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2109 #endif
2110         {},
2111 };
2112
2113 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2114 {
2115         switch (cap->hwcap_type) {
2116         case CAP_HWCAP:
2117                 cpu_set_feature(cap->hwcap);
2118                 break;
2119 #ifdef CONFIG_COMPAT
2120         case CAP_COMPAT_HWCAP:
2121                 compat_elf_hwcap |= (u32)cap->hwcap;
2122                 break;
2123         case CAP_COMPAT_HWCAP2:
2124                 compat_elf_hwcap2 |= (u32)cap->hwcap;
2125                 break;
2126 #endif
2127         default:
2128                 WARN_ON(1);
2129                 break;
2130         }
2131 }
2132
2133 /* Check if we have a particular HWCAP enabled */
2134 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2135 {
2136         bool rc;
2137
2138         switch (cap->hwcap_type) {
2139         case CAP_HWCAP:
2140                 rc = cpu_have_feature(cap->hwcap);
2141                 break;
2142 #ifdef CONFIG_COMPAT
2143         case CAP_COMPAT_HWCAP:
2144                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2145                 break;
2146         case CAP_COMPAT_HWCAP2:
2147                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2148                 break;
2149 #endif
2150         default:
2151                 WARN_ON(1);
2152                 rc = false;
2153         }
2154
2155         return rc;
2156 }
2157
2158 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2159 {
2160         /* We support emulation of accesses to CPU ID feature registers */
2161         cpu_set_named_feature(CPUID);
2162         for (; hwcaps->matches; hwcaps++)
2163                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2164                         cap_set_elf_hwcap(hwcaps);
2165 }
2166
2167 static void update_cpu_capabilities(u16 scope_mask)
2168 {
2169         int i;
2170         const struct arm64_cpu_capabilities *caps;
2171
2172         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2173         for (i = 0; i < ARM64_NCAPS; i++) {
2174                 caps = cpu_hwcaps_ptrs[i];
2175                 if (!caps || !(caps->type & scope_mask) ||
2176                     cpus_have_cap(caps->capability) ||
2177                     !caps->matches(caps, cpucap_default_scope(caps)))
2178                         continue;
2179
2180                 if (caps->desc)
2181                         pr_info("detected: %s\n", caps->desc);
2182                 cpus_set_cap(caps->capability);
2183
2184                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2185                         set_bit(caps->capability, boot_capabilities);
2186         }
2187 }
2188
2189 /*
2190  * Enable all the available capabilities on this CPU. The capabilities
2191  * with BOOT_CPU scope are handled separately and hence skipped here.
2192  */
2193 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2194 {
2195         int i;
2196         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2197
2198         for_each_available_cap(i) {
2199                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2200
2201                 if (WARN_ON(!cap))
2202                         continue;
2203
2204                 if (!(cap->type & non_boot_scope))
2205                         continue;
2206
2207                 if (cap->cpu_enable)
2208                         cap->cpu_enable(cap);
2209         }
2210         return 0;
2211 }
2212
2213 /*
2214  * Run through the enabled capabilities and enable() it on all active
2215  * CPUs
2216  */
2217 static void __init enable_cpu_capabilities(u16 scope_mask)
2218 {
2219         int i;
2220         const struct arm64_cpu_capabilities *caps;
2221         bool boot_scope;
2222
2223         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2224         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2225
2226         for (i = 0; i < ARM64_NCAPS; i++) {
2227                 unsigned int num;
2228
2229                 caps = cpu_hwcaps_ptrs[i];
2230                 if (!caps || !(caps->type & scope_mask))
2231                         continue;
2232                 num = caps->capability;
2233                 if (!cpus_have_cap(num))
2234                         continue;
2235
2236                 /* Ensure cpus_have_const_cap(num) works */
2237                 static_branch_enable(&cpu_hwcap_keys[num]);
2238
2239                 if (boot_scope && caps->cpu_enable)
2240                         /*
2241                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
2242                          * before any secondary CPU boots. Thus, each secondary
2243                          * will enable the capability as appropriate via
2244                          * check_local_cpu_capabilities(). The only exception is
2245                          * the boot CPU, for which the capability must be
2246                          * enabled here. This approach avoids costly
2247                          * stop_machine() calls for this case.
2248                          */
2249                         caps->cpu_enable(caps);
2250         }
2251
2252         /*
2253          * For all non-boot scope capabilities, use stop_machine()
2254          * as it schedules the work allowing us to modify PSTATE,
2255          * instead of on_each_cpu() which uses an IPI, giving us a
2256          * PSTATE that disappears when we return.
2257          */
2258         if (!boot_scope)
2259                 stop_machine(cpu_enable_non_boot_scope_capabilities,
2260                              NULL, cpu_online_mask);
2261 }
2262
2263 /*
2264  * Run through the list of capabilities to check for conflicts.
2265  * If the system has already detected a capability, take necessary
2266  * action on this CPU.
2267  */
2268 static void verify_local_cpu_caps(u16 scope_mask)
2269 {
2270         int i;
2271         bool cpu_has_cap, system_has_cap;
2272         const struct arm64_cpu_capabilities *caps;
2273
2274         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2275
2276         for (i = 0; i < ARM64_NCAPS; i++) {
2277                 caps = cpu_hwcaps_ptrs[i];
2278                 if (!caps || !(caps->type & scope_mask))
2279                         continue;
2280
2281                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2282                 system_has_cap = cpus_have_cap(caps->capability);
2283
2284                 if (system_has_cap) {
2285                         /*
2286                          * Check if the new CPU misses an advertised feature,
2287                          * which is not safe to miss.
2288                          */
2289                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2290                                 break;
2291                         /*
2292                          * We have to issue cpu_enable() irrespective of
2293                          * whether the CPU has it or not, as it is enabeld
2294                          * system wide. It is upto the call back to take
2295                          * appropriate action on this CPU.
2296                          */
2297                         if (caps->cpu_enable)
2298                                 caps->cpu_enable(caps);
2299                 } else {
2300                         /*
2301                          * Check if the CPU has this capability if it isn't
2302                          * safe to have when the system doesn't.
2303                          */
2304                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2305                                 break;
2306                 }
2307         }
2308
2309         if (i < ARM64_NCAPS) {
2310                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2311                         smp_processor_id(), caps->capability,
2312                         caps->desc, system_has_cap, cpu_has_cap);
2313
2314                 if (cpucap_panic_on_conflict(caps))
2315                         cpu_panic_kernel();
2316                 else
2317                         cpu_die_early();
2318         }
2319 }
2320
2321 /*
2322  * Check for CPU features that are used in early boot
2323  * based on the Boot CPU value.
2324  */
2325 static void check_early_cpu_features(void)
2326 {
2327         verify_cpu_asid_bits();
2328
2329         verify_local_cpu_caps(SCOPE_BOOT_CPU);
2330 }
2331
2332 static void
2333 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2334 {
2335
2336         for (; caps->matches; caps++)
2337                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2338                         pr_crit("CPU%d: missing HWCAP: %s\n",
2339                                         smp_processor_id(), caps->desc);
2340                         cpu_die_early();
2341                 }
2342 }
2343
2344 static void verify_sve_features(void)
2345 {
2346         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2347         u64 zcr = read_zcr_features();
2348
2349         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2350         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2351
2352         if (len < safe_len || sve_verify_vq_map()) {
2353                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2354                         smp_processor_id());
2355                 cpu_die_early();
2356         }
2357
2358         /* Add checks on other ZCR bits here if necessary */
2359 }
2360
2361 static void verify_hyp_capabilities(void)
2362 {
2363         u64 safe_mmfr1, mmfr0, mmfr1;
2364         int parange, ipa_max;
2365         unsigned int safe_vmid_bits, vmid_bits;
2366
2367         if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST))
2368                 return;
2369
2370         safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2371         mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2372         mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2373
2374         /* Verify VMID bits */
2375         safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2376         vmid_bits = get_vmid_bits(mmfr1);
2377         if (vmid_bits < safe_vmid_bits) {
2378                 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2379                 cpu_die_early();
2380         }
2381
2382         /* Verify IPA range */
2383         parange = cpuid_feature_extract_unsigned_field(mmfr0,
2384                                 ID_AA64MMFR0_PARANGE_SHIFT);
2385         ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2386         if (ipa_max < get_kvm_ipa_limit()) {
2387                 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2388                 cpu_die_early();
2389         }
2390 }
2391
2392 /*
2393  * Run through the enabled system capabilities and enable() it on this CPU.
2394  * The capabilities were decided based on the available CPUs at the boot time.
2395  * Any new CPU should match the system wide status of the capability. If the
2396  * new CPU doesn't have a capability which the system now has enabled, we
2397  * cannot do anything to fix it up and could cause unexpected failures. So
2398  * we park the CPU.
2399  */
2400 static void verify_local_cpu_capabilities(void)
2401 {
2402         /*
2403          * The capabilities with SCOPE_BOOT_CPU are checked from
2404          * check_early_cpu_features(), as they need to be verified
2405          * on all secondary CPUs.
2406          */
2407         verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2408
2409         verify_local_elf_hwcaps(arm64_elf_hwcaps);
2410
2411         if (system_supports_32bit_el0())
2412                 verify_local_elf_hwcaps(compat_elf_hwcaps);
2413
2414         if (system_supports_sve())
2415                 verify_sve_features();
2416
2417         if (is_hyp_mode_available())
2418                 verify_hyp_capabilities();
2419 }
2420
2421 void check_local_cpu_capabilities(void)
2422 {
2423         /*
2424          * All secondary CPUs should conform to the early CPU features
2425          * in use by the kernel based on boot CPU.
2426          */
2427         check_early_cpu_features();
2428
2429         /*
2430          * If we haven't finalised the system capabilities, this CPU gets
2431          * a chance to update the errata work arounds and local features.
2432          * Otherwise, this CPU should verify that it has all the system
2433          * advertised capabilities.
2434          */
2435         if (!system_capabilities_finalized())
2436                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2437         else
2438                 verify_local_cpu_capabilities();
2439 }
2440
2441 static void __init setup_boot_cpu_capabilities(void)
2442 {
2443         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2444         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2445         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2446         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2447 }
2448
2449 bool this_cpu_has_cap(unsigned int n)
2450 {
2451         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2452                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2453
2454                 if (cap)
2455                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2456         }
2457
2458         return false;
2459 }
2460
2461 /*
2462  * This helper function is used in a narrow window when,
2463  * - The system wide safe registers are set with all the SMP CPUs and,
2464  * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2465  * In all other cases cpus_have_{const_}cap() should be used.
2466  */
2467 static bool __system_matches_cap(unsigned int n)
2468 {
2469         if (n < ARM64_NCAPS) {
2470                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2471
2472                 if (cap)
2473                         return cap->matches(cap, SCOPE_SYSTEM);
2474         }
2475         return false;
2476 }
2477
2478 void cpu_set_feature(unsigned int num)
2479 {
2480         WARN_ON(num >= MAX_CPU_FEATURES);
2481         elf_hwcap |= BIT(num);
2482 }
2483 EXPORT_SYMBOL_GPL(cpu_set_feature);
2484
2485 bool cpu_have_feature(unsigned int num)
2486 {
2487         WARN_ON(num >= MAX_CPU_FEATURES);
2488         return elf_hwcap & BIT(num);
2489 }
2490 EXPORT_SYMBOL_GPL(cpu_have_feature);
2491
2492 unsigned long cpu_get_elf_hwcap(void)
2493 {
2494         /*
2495          * We currently only populate the first 32 bits of AT_HWCAP. Please
2496          * note that for userspace compatibility we guarantee that bits 62
2497          * and 63 will always be returned as 0.
2498          */
2499         return lower_32_bits(elf_hwcap);
2500 }
2501
2502 unsigned long cpu_get_elf_hwcap2(void)
2503 {
2504         return upper_32_bits(elf_hwcap);
2505 }
2506
2507 static void __init setup_system_capabilities(void)
2508 {
2509         /*
2510          * We have finalised the system-wide safe feature
2511          * registers, finalise the capabilities that depend
2512          * on it. Also enable all the available capabilities,
2513          * that are not enabled already.
2514          */
2515         update_cpu_capabilities(SCOPE_SYSTEM);
2516         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2517 }
2518
2519 void __init setup_cpu_features(void)
2520 {
2521         u32 cwg;
2522
2523         setup_system_capabilities();
2524         setup_elf_hwcaps(arm64_elf_hwcaps);
2525
2526         if (system_supports_32bit_el0())
2527                 setup_elf_hwcaps(compat_elf_hwcaps);
2528
2529         if (system_uses_ttbr0_pan())
2530                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2531
2532         sve_setup();
2533         minsigstksz_setup();
2534
2535         /* Advertise that we have computed the system capabilities */
2536         finalize_system_capabilities();
2537
2538         /*
2539          * Check for sane CTR_EL0.CWG value.
2540          */
2541         cwg = cache_type_cwg();
2542         if (!cwg)
2543                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2544                         ARCH_DMA_MINALIGN);
2545 }
2546
2547 static bool __maybe_unused
2548 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2549 {
2550         return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
2551 }
2552
2553 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2554 {
2555         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2556 }
2557
2558 /*
2559  * We emulate only the following system register space.
2560  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2561  * See Table C5-6 System instruction encodings for System register accesses,
2562  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2563  */
2564 static inline bool __attribute_const__ is_emulated(u32 id)
2565 {
2566         return (sys_reg_Op0(id) == 0x3 &&
2567                 sys_reg_CRn(id) == 0x0 &&
2568                 sys_reg_Op1(id) == 0x0 &&
2569                 (sys_reg_CRm(id) == 0 ||
2570                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2571 }
2572
2573 /*
2574  * With CRm == 0, reg should be one of :
2575  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2576  */
2577 static inline int emulate_id_reg(u32 id, u64 *valp)
2578 {
2579         switch (id) {
2580         case SYS_MIDR_EL1:
2581                 *valp = read_cpuid_id();
2582                 break;
2583         case SYS_MPIDR_EL1:
2584                 *valp = SYS_MPIDR_SAFE_VAL;
2585                 break;
2586         case SYS_REVIDR_EL1:
2587                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2588                 *valp = 0;
2589                 break;
2590         default:
2591                 return -EINVAL;
2592         }
2593
2594         return 0;
2595 }
2596
2597 static int emulate_sys_reg(u32 id, u64 *valp)
2598 {
2599         struct arm64_ftr_reg *regp;
2600
2601         if (!is_emulated(id))
2602                 return -EINVAL;
2603
2604         if (sys_reg_CRm(id) == 0)
2605                 return emulate_id_reg(id, valp);
2606
2607         regp = get_arm64_ftr_reg(id);
2608         if (regp)
2609                 *valp = arm64_ftr_reg_user_value(regp);
2610         else
2611                 /*
2612                  * The untracked registers are either IMPLEMENTATION DEFINED
2613                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2614                  */
2615                 *valp = 0;
2616         return 0;
2617 }
2618
2619 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2620 {
2621         int rc;
2622         u64 val;
2623
2624         rc = emulate_sys_reg(sys_reg, &val);
2625         if (!rc) {
2626                 pt_regs_write_reg(regs, rt, val);
2627                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2628         }
2629         return rc;
2630 }
2631
2632 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2633 {
2634         u32 sys_reg, rt;
2635
2636         /*
2637          * sys_reg values are defined as used in mrs/msr instruction.
2638          * shift the imm value to get the encoding.
2639          */
2640         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2641         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2642         return do_emulate_mrs(regs, sys_reg, rt);
2643 }
2644
2645 static struct undef_hook mrs_hook = {
2646         .instr_mask = 0xfff00000,
2647         .instr_val  = 0xd5300000,
2648         .pstate_mask = PSR_AA32_MODE_MASK,
2649         .pstate_val = PSR_MODE_EL0t,
2650         .fn = emulate_mrs,
2651 };
2652
2653 static int __init enable_mrs_emulation(void)
2654 {
2655         register_undef_hook(&mrs_hook);
2656         return 0;
2657 }
2658
2659 core_initcall(enable_mrs_emulation);
2660
2661 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2662                           char *buf)
2663 {
2664         if (__meltdown_safe)
2665                 return sprintf(buf, "Not affected\n");
2666
2667         if (arm64_kernel_unmapped_at_el0())
2668                 return sprintf(buf, "Mitigation: PTI\n");
2669
2670         return sprintf(buf, "Vulnerable\n");
2671 }