Merge tag 'powerpc-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[muen/linux.git] / arch / powerpc / platforms / powernv / pci-ioda.c
1 /*
2  * Support PCI/PCIe on PowerNV platforms
3  *
4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/msi.h>
24 #include <linux/memblock.h>
25 #include <linux/iommu.h>
26 #include <linux/rculist.h>
27 #include <linux/sizes.h>
28
29 #include <asm/sections.h>
30 #include <asm/io.h>
31 #include <asm/prom.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <asm/msi_bitmap.h>
35 #include <asm/ppc-pci.h>
36 #include <asm/opal.h>
37 #include <asm/iommu.h>
38 #include <asm/tce.h>
39 #include <asm/xics.h>
40 #include <asm/debugfs.h>
41 #include <asm/firmware.h>
42 #include <asm/pnv-pci.h>
43 #include <asm/mmzone.h>
44
45 #include <misc/cxl-base.h>
46
47 #include "powernv.h"
48 #include "pci.h"
49 #include "../../../../drivers/pci/pci.h"
50
51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54
55 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
56                                               "NPU_OCAPI" };
57
58 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
59                             const char *fmt, ...)
60 {
61         struct va_format vaf;
62         va_list args;
63         char pfix[32];
64
65         va_start(args, fmt);
66
67         vaf.fmt = fmt;
68         vaf.va = &args;
69
70         if (pe->flags & PNV_IODA_PE_DEV)
71                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
72         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
73                 sprintf(pfix, "%04x:%02x     ",
74                         pci_domain_nr(pe->pbus), pe->pbus->number);
75 #ifdef CONFIG_PCI_IOV
76         else if (pe->flags & PNV_IODA_PE_VF)
77                 sprintf(pfix, "%04x:%02x:%2x.%d",
78                         pci_domain_nr(pe->parent_dev->bus),
79                         (pe->rid & 0xff00) >> 8,
80                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
81 #endif /* CONFIG_PCI_IOV*/
82
83         printk("%spci %s: [PE# %.2x] %pV",
84                level, pfix, pe->pe_number, &vaf);
85
86         va_end(args);
87 }
88
89 static bool pnv_iommu_bypass_disabled __read_mostly;
90 static bool pci_reset_phbs __read_mostly;
91
92 static int __init iommu_setup(char *str)
93 {
94         if (!str)
95                 return -EINVAL;
96
97         while (*str) {
98                 if (!strncmp(str, "nobypass", 8)) {
99                         pnv_iommu_bypass_disabled = true;
100                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
101                         break;
102                 }
103                 str += strcspn(str, ",");
104                 if (*str == ',')
105                         str++;
106         }
107
108         return 0;
109 }
110 early_param("iommu", iommu_setup);
111
112 static int __init pci_reset_phbs_setup(char *str)
113 {
114         pci_reset_phbs = true;
115         return 0;
116 }
117
118 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
119
120 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
121 {
122         /*
123          * WARNING: We cannot rely on the resource flags. The Linux PCI
124          * allocation code sometimes decides to put a 64-bit prefetchable
125          * BAR in the 32-bit window, so we have to compare the addresses.
126          *
127          * For simplicity we only test resource start.
128          */
129         return (r->start >= phb->ioda.m64_base &&
130                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
131 }
132
133 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
134 {
135         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
136
137         return (resource_flags & flags) == flags;
138 }
139
140 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
141 {
142         s64 rc;
143
144         phb->ioda.pe_array[pe_no].phb = phb;
145         phb->ioda.pe_array[pe_no].pe_number = pe_no;
146
147         /*
148          * Clear the PE frozen state as it might be put into frozen state
149          * in the last PCI remove path. It's not harmful to do so when the
150          * PE is already in unfrozen state.
151          */
152         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
153                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
154         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
155                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
156                         __func__, rc, phb->hose->global_number, pe_no);
157
158         return &phb->ioda.pe_array[pe_no];
159 }
160
161 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
162 {
163         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
164                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
165                         __func__, pe_no, phb->hose->global_number);
166                 return;
167         }
168
169         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
170                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
171                          __func__, pe_no, phb->hose->global_number);
172
173         pnv_ioda_init_pe(phb, pe_no);
174 }
175
176 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
177 {
178         long pe;
179
180         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
181                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
182                         return pnv_ioda_init_pe(phb, pe);
183         }
184
185         return NULL;
186 }
187
188 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
189 {
190         struct pnv_phb *phb = pe->phb;
191         unsigned int pe_num = pe->pe_number;
192
193         WARN_ON(pe->pdev);
194
195         memset(pe, 0, sizeof(struct pnv_ioda_pe));
196         clear_bit(pe_num, phb->ioda.pe_alloc);
197 }
198
199 /* The default M64 BAR is shared by all PEs */
200 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
201 {
202         const char *desc;
203         struct resource *r;
204         s64 rc;
205
206         /* Configure the default M64 BAR */
207         rc = opal_pci_set_phb_mem_window(phb->opal_id,
208                                          OPAL_M64_WINDOW_TYPE,
209                                          phb->ioda.m64_bar_idx,
210                                          phb->ioda.m64_base,
211                                          0, /* unused */
212                                          phb->ioda.m64_size);
213         if (rc != OPAL_SUCCESS) {
214                 desc = "configuring";
215                 goto fail;
216         }
217
218         /* Enable the default M64 BAR */
219         rc = opal_pci_phb_mmio_enable(phb->opal_id,
220                                       OPAL_M64_WINDOW_TYPE,
221                                       phb->ioda.m64_bar_idx,
222                                       OPAL_ENABLE_M64_SPLIT);
223         if (rc != OPAL_SUCCESS) {
224                 desc = "enabling";
225                 goto fail;
226         }
227
228         /*
229          * Exclude the segments for reserved and root bus PE, which
230          * are first or last two PEs.
231          */
232         r = &phb->hose->mem_resources[1];
233         if (phb->ioda.reserved_pe_idx == 0)
234                 r->start += (2 * phb->ioda.m64_segsize);
235         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
236                 r->end -= (2 * phb->ioda.m64_segsize);
237         else
238                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
239                         phb->ioda.reserved_pe_idx);
240
241         return 0;
242
243 fail:
244         pr_warn("  Failure %lld %s M64 BAR#%d\n",
245                 rc, desc, phb->ioda.m64_bar_idx);
246         opal_pci_phb_mmio_enable(phb->opal_id,
247                                  OPAL_M64_WINDOW_TYPE,
248                                  phb->ioda.m64_bar_idx,
249                                  OPAL_DISABLE_M64);
250         return -EIO;
251 }
252
253 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
254                                          unsigned long *pe_bitmap)
255 {
256         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
257         struct pnv_phb *phb = hose->private_data;
258         struct resource *r;
259         resource_size_t base, sgsz, start, end;
260         int segno, i;
261
262         base = phb->ioda.m64_base;
263         sgsz = phb->ioda.m64_segsize;
264         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
265                 r = &pdev->resource[i];
266                 if (!r->parent || !pnv_pci_is_m64(phb, r))
267                         continue;
268
269                 start = _ALIGN_DOWN(r->start - base, sgsz);
270                 end = _ALIGN_UP(r->end - base, sgsz);
271                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
272                         if (pe_bitmap)
273                                 set_bit(segno, pe_bitmap);
274                         else
275                                 pnv_ioda_reserve_pe(phb, segno);
276                 }
277         }
278 }
279
280 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
281 {
282         struct resource *r;
283         int index;
284
285         /*
286          * There are 16 M64 BARs, each of which has 8 segments. So
287          * there are as many M64 segments as the maximum number of
288          * PEs, which is 128.
289          */
290         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
291                 unsigned long base, segsz = phb->ioda.m64_segsize;
292                 int64_t rc;
293
294                 base = phb->ioda.m64_base +
295                        index * PNV_IODA1_M64_SEGS * segsz;
296                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
297                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
298                                 PNV_IODA1_M64_SEGS * segsz);
299                 if (rc != OPAL_SUCCESS) {
300                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
301                                 rc, phb->hose->global_number, index);
302                         goto fail;
303                 }
304
305                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
306                                 OPAL_M64_WINDOW_TYPE, index,
307                                 OPAL_ENABLE_M64_SPLIT);
308                 if (rc != OPAL_SUCCESS) {
309                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
310                                 rc, phb->hose->global_number, index);
311                         goto fail;
312                 }
313         }
314
315         /*
316          * Exclude the segments for reserved and root bus PE, which
317          * are first or last two PEs.
318          */
319         r = &phb->hose->mem_resources[1];
320         if (phb->ioda.reserved_pe_idx == 0)
321                 r->start += (2 * phb->ioda.m64_segsize);
322         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
323                 r->end -= (2 * phb->ioda.m64_segsize);
324         else
325                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
326                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
327
328         return 0;
329
330 fail:
331         for ( ; index >= 0; index--)
332                 opal_pci_phb_mmio_enable(phb->opal_id,
333                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
334
335         return -EIO;
336 }
337
338 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
339                                     unsigned long *pe_bitmap,
340                                     bool all)
341 {
342         struct pci_dev *pdev;
343
344         list_for_each_entry(pdev, &bus->devices, bus_list) {
345                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
346
347                 if (all && pdev->subordinate)
348                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
349                                                 pe_bitmap, all);
350         }
351 }
352
353 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
354 {
355         struct pci_controller *hose = pci_bus_to_host(bus);
356         struct pnv_phb *phb = hose->private_data;
357         struct pnv_ioda_pe *master_pe, *pe;
358         unsigned long size, *pe_alloc;
359         int i;
360
361         /* Root bus shouldn't use M64 */
362         if (pci_is_root_bus(bus))
363                 return NULL;
364
365         /* Allocate bitmap */
366         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
367         pe_alloc = kzalloc(size, GFP_KERNEL);
368         if (!pe_alloc) {
369                 pr_warn("%s: Out of memory !\n",
370                         __func__);
371                 return NULL;
372         }
373
374         /* Figure out reserved PE numbers by the PE */
375         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
376
377         /*
378          * the current bus might not own M64 window and that's all
379          * contributed by its child buses. For the case, we needn't
380          * pick M64 dependent PE#.
381          */
382         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
383                 kfree(pe_alloc);
384                 return NULL;
385         }
386
387         /*
388          * Figure out the master PE and put all slave PEs to master
389          * PE's list to form compound PE.
390          */
391         master_pe = NULL;
392         i = -1;
393         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
394                 phb->ioda.total_pe_num) {
395                 pe = &phb->ioda.pe_array[i];
396
397                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
398                 if (!master_pe) {
399                         pe->flags |= PNV_IODA_PE_MASTER;
400                         INIT_LIST_HEAD(&pe->slaves);
401                         master_pe = pe;
402                 } else {
403                         pe->flags |= PNV_IODA_PE_SLAVE;
404                         pe->master = master_pe;
405                         list_add_tail(&pe->list, &master_pe->slaves);
406                 }
407
408                 /*
409                  * P7IOC supports M64DT, which helps mapping M64 segment
410                  * to one particular PE#. However, PHB3 has fixed mapping
411                  * between M64 segment and PE#. In order to have same logic
412                  * for P7IOC and PHB3, we enforce fixed mapping between M64
413                  * segment and PE# on P7IOC.
414                  */
415                 if (phb->type == PNV_PHB_IODA1) {
416                         int64_t rc;
417
418                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
419                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
420                                         pe->pe_number / PNV_IODA1_M64_SEGS,
421                                         pe->pe_number % PNV_IODA1_M64_SEGS);
422                         if (rc != OPAL_SUCCESS)
423                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
424                                         __func__, rc, phb->hose->global_number,
425                                         pe->pe_number);
426                 }
427         }
428
429         kfree(pe_alloc);
430         return master_pe;
431 }
432
433 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
434 {
435         struct pci_controller *hose = phb->hose;
436         struct device_node *dn = hose->dn;
437         struct resource *res;
438         u32 m64_range[2], i;
439         const __be32 *r;
440         u64 pci_addr;
441
442         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
443                 pr_info("  Not support M64 window\n");
444                 return;
445         }
446
447         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
448                 pr_info("  Firmware too old to support M64 window\n");
449                 return;
450         }
451
452         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
453         if (!r) {
454                 pr_info("  No <ibm,opal-m64-window> on %pOF\n",
455                         dn);
456                 return;
457         }
458
459         /*
460          * Find the available M64 BAR range and pickup the last one for
461          * covering the whole 64-bits space. We support only one range.
462          */
463         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
464                                        m64_range, 2)) {
465                 /* In absence of the property, assume 0..15 */
466                 m64_range[0] = 0;
467                 m64_range[1] = 16;
468         }
469         /* We only support 64 bits in our allocator */
470         if (m64_range[1] > 63) {
471                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
472                         __func__, m64_range[1], phb->hose->global_number);
473                 m64_range[1] = 63;
474         }
475         /* Empty range, no m64 */
476         if (m64_range[1] <= m64_range[0]) {
477                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
478                         __func__, phb->hose->global_number);
479                 return;
480         }
481
482         /* Configure M64 informations */
483         res = &hose->mem_resources[1];
484         res->name = dn->full_name;
485         res->start = of_translate_address(dn, r + 2);
486         res->end = res->start + of_read_number(r + 4, 2) - 1;
487         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
488         pci_addr = of_read_number(r, 2);
489         hose->mem_offset[1] = res->start - pci_addr;
490
491         phb->ioda.m64_size = resource_size(res);
492         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
493         phb->ioda.m64_base = pci_addr;
494
495         /* This lines up nicely with the display from processing OF ranges */
496         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
497                 res->start, res->end, pci_addr, m64_range[0],
498                 m64_range[0] + m64_range[1] - 1);
499
500         /* Mark all M64 used up by default */
501         phb->ioda.m64_bar_alloc = (unsigned long)-1;
502
503         /* Use last M64 BAR to cover M64 window */
504         m64_range[1]--;
505         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
506
507         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
508
509         /* Mark remaining ones free */
510         for (i = m64_range[0]; i < m64_range[1]; i++)
511                 clear_bit(i, &phb->ioda.m64_bar_alloc);
512
513         /*
514          * Setup init functions for M64 based on IODA version, IODA3 uses
515          * the IODA2 code.
516          */
517         if (phb->type == PNV_PHB_IODA1)
518                 phb->init_m64 = pnv_ioda1_init_m64;
519         else
520                 phb->init_m64 = pnv_ioda2_init_m64;
521         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
522         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
523 }
524
525 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
526 {
527         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
528         struct pnv_ioda_pe *slave;
529         s64 rc;
530
531         /* Fetch master PE */
532         if (pe->flags & PNV_IODA_PE_SLAVE) {
533                 pe = pe->master;
534                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
535                         return;
536
537                 pe_no = pe->pe_number;
538         }
539
540         /* Freeze master PE */
541         rc = opal_pci_eeh_freeze_set(phb->opal_id,
542                                      pe_no,
543                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
544         if (rc != OPAL_SUCCESS) {
545                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
546                         __func__, rc, phb->hose->global_number, pe_no);
547                 return;
548         }
549
550         /* Freeze slave PEs */
551         if (!(pe->flags & PNV_IODA_PE_MASTER))
552                 return;
553
554         list_for_each_entry(slave, &pe->slaves, list) {
555                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
556                                              slave->pe_number,
557                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
558                 if (rc != OPAL_SUCCESS)
559                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
560                                 __func__, rc, phb->hose->global_number,
561                                 slave->pe_number);
562         }
563 }
564
565 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
566 {
567         struct pnv_ioda_pe *pe, *slave;
568         s64 rc;
569
570         /* Find master PE */
571         pe = &phb->ioda.pe_array[pe_no];
572         if (pe->flags & PNV_IODA_PE_SLAVE) {
573                 pe = pe->master;
574                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
575                 pe_no = pe->pe_number;
576         }
577
578         /* Clear frozen state for master PE */
579         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
580         if (rc != OPAL_SUCCESS) {
581                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
582                         __func__, rc, opt, phb->hose->global_number, pe_no);
583                 return -EIO;
584         }
585
586         if (!(pe->flags & PNV_IODA_PE_MASTER))
587                 return 0;
588
589         /* Clear frozen state for slave PEs */
590         list_for_each_entry(slave, &pe->slaves, list) {
591                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
592                                              slave->pe_number,
593                                              opt);
594                 if (rc != OPAL_SUCCESS) {
595                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
596                                 __func__, rc, opt, phb->hose->global_number,
597                                 slave->pe_number);
598                         return -EIO;
599                 }
600         }
601
602         return 0;
603 }
604
605 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
606 {
607         struct pnv_ioda_pe *slave, *pe;
608         u8 fstate, state;
609         __be16 pcierr;
610         s64 rc;
611
612         /* Sanity check on PE number */
613         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
614                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
615
616         /*
617          * Fetch the master PE and the PE instance might be
618          * not initialized yet.
619          */
620         pe = &phb->ioda.pe_array[pe_no];
621         if (pe->flags & PNV_IODA_PE_SLAVE) {
622                 pe = pe->master;
623                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
624                 pe_no = pe->pe_number;
625         }
626
627         /* Check the master PE */
628         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
629                                         &state, &pcierr, NULL);
630         if (rc != OPAL_SUCCESS) {
631                 pr_warn("%s: Failure %lld getting "
632                         "PHB#%x-PE#%x state\n",
633                         __func__, rc,
634                         phb->hose->global_number, pe_no);
635                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
636         }
637
638         /* Check the slave PE */
639         if (!(pe->flags & PNV_IODA_PE_MASTER))
640                 return state;
641
642         list_for_each_entry(slave, &pe->slaves, list) {
643                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
644                                                 slave->pe_number,
645                                                 &fstate,
646                                                 &pcierr,
647                                                 NULL);
648                 if (rc != OPAL_SUCCESS) {
649                         pr_warn("%s: Failure %lld getting "
650                                 "PHB#%x-PE#%x state\n",
651                                 __func__, rc,
652                                 phb->hose->global_number, slave->pe_number);
653                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
654                 }
655
656                 /*
657                  * Override the result based on the ascending
658                  * priority.
659                  */
660                 if (fstate > state)
661                         state = fstate;
662         }
663
664         return state;
665 }
666
667 /* Currently those 2 are only used when MSIs are enabled, this will change
668  * but in the meantime, we need to protect them to avoid warnings
669  */
670 #ifdef CONFIG_PCI_MSI
671 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
672 {
673         struct pci_controller *hose = pci_bus_to_host(dev->bus);
674         struct pnv_phb *phb = hose->private_data;
675         struct pci_dn *pdn = pci_get_pdn(dev);
676
677         if (!pdn)
678                 return NULL;
679         if (pdn->pe_number == IODA_INVALID_PE)
680                 return NULL;
681         return &phb->ioda.pe_array[pdn->pe_number];
682 }
683 #endif /* CONFIG_PCI_MSI */
684
685 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
686                                   struct pnv_ioda_pe *parent,
687                                   struct pnv_ioda_pe *child,
688                                   bool is_add)
689 {
690         const char *desc = is_add ? "adding" : "removing";
691         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
692                               OPAL_REMOVE_PE_FROM_DOMAIN;
693         struct pnv_ioda_pe *slave;
694         long rc;
695
696         /* Parent PE affects child PE */
697         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
698                                 child->pe_number, op);
699         if (rc != OPAL_SUCCESS) {
700                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
701                         rc, desc);
702                 return -ENXIO;
703         }
704
705         if (!(child->flags & PNV_IODA_PE_MASTER))
706                 return 0;
707
708         /* Compound case: parent PE affects slave PEs */
709         list_for_each_entry(slave, &child->slaves, list) {
710                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
711                                         slave->pe_number, op);
712                 if (rc != OPAL_SUCCESS) {
713                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
714                                 rc, desc);
715                         return -ENXIO;
716                 }
717         }
718
719         return 0;
720 }
721
722 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
723                               struct pnv_ioda_pe *pe,
724                               bool is_add)
725 {
726         struct pnv_ioda_pe *slave;
727         struct pci_dev *pdev = NULL;
728         int ret;
729
730         /*
731          * Clear PE frozen state. If it's master PE, we need
732          * clear slave PE frozen state as well.
733          */
734         if (is_add) {
735                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
736                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
737                 if (pe->flags & PNV_IODA_PE_MASTER) {
738                         list_for_each_entry(slave, &pe->slaves, list)
739                                 opal_pci_eeh_freeze_clear(phb->opal_id,
740                                                           slave->pe_number,
741                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
742                 }
743         }
744
745         /*
746          * Associate PE in PELT. We need add the PE into the
747          * corresponding PELT-V as well. Otherwise, the error
748          * originated from the PE might contribute to other
749          * PEs.
750          */
751         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
752         if (ret)
753                 return ret;
754
755         /* For compound PEs, any one affects all of them */
756         if (pe->flags & PNV_IODA_PE_MASTER) {
757                 list_for_each_entry(slave, &pe->slaves, list) {
758                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
759                         if (ret)
760                                 return ret;
761                 }
762         }
763
764         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
765                 pdev = pe->pbus->self;
766         else if (pe->flags & PNV_IODA_PE_DEV)
767                 pdev = pe->pdev->bus->self;
768 #ifdef CONFIG_PCI_IOV
769         else if (pe->flags & PNV_IODA_PE_VF)
770                 pdev = pe->parent_dev;
771 #endif /* CONFIG_PCI_IOV */
772         while (pdev) {
773                 struct pci_dn *pdn = pci_get_pdn(pdev);
774                 struct pnv_ioda_pe *parent;
775
776                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
777                         parent = &phb->ioda.pe_array[pdn->pe_number];
778                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
779                         if (ret)
780                                 return ret;
781                 }
782
783                 pdev = pdev->bus->self;
784         }
785
786         return 0;
787 }
788
789 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
790 {
791         struct pci_dev *parent;
792         uint8_t bcomp, dcomp, fcomp;
793         int64_t rc;
794         long rid_end, rid;
795
796         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
797         if (pe->pbus) {
798                 int count;
799
800                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
801                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
802                 parent = pe->pbus->self;
803                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
804                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
805                 else
806                         count = 1;
807
808                 switch(count) {
809                 case  1: bcomp = OpalPciBusAll;         break;
810                 case  2: bcomp = OpalPciBus7Bits;       break;
811                 case  4: bcomp = OpalPciBus6Bits;       break;
812                 case  8: bcomp = OpalPciBus5Bits;       break;
813                 case 16: bcomp = OpalPciBus4Bits;       break;
814                 case 32: bcomp = OpalPciBus3Bits;       break;
815                 default:
816                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
817                                 count);
818                         /* Do an exact match only */
819                         bcomp = OpalPciBusAll;
820                 }
821                 rid_end = pe->rid + (count << 8);
822         } else {
823 #ifdef CONFIG_PCI_IOV
824                 if (pe->flags & PNV_IODA_PE_VF)
825                         parent = pe->parent_dev;
826                 else
827 #endif
828                         parent = pe->pdev->bus->self;
829                 bcomp = OpalPciBusAll;
830                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
831                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
832                 rid_end = pe->rid + 1;
833         }
834
835         /* Clear the reverse map */
836         for (rid = pe->rid; rid < rid_end; rid++)
837                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
838
839         /* Release from all parents PELT-V */
840         while (parent) {
841                 struct pci_dn *pdn = pci_get_pdn(parent);
842                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
843                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
844                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
845                         /* XXX What to do in case of error ? */
846                 }
847                 parent = parent->bus->self;
848         }
849
850         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
851                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
852
853         /* Disassociate PE in PELT */
854         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
855                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
856         if (rc)
857                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
858         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
859                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
860         if (rc)
861                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
862
863         pe->pbus = NULL;
864         pe->pdev = NULL;
865 #ifdef CONFIG_PCI_IOV
866         pe->parent_dev = NULL;
867 #endif
868
869         return 0;
870 }
871
872 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
873 {
874         struct pci_dev *parent;
875         uint8_t bcomp, dcomp, fcomp;
876         long rc, rid_end, rid;
877
878         /* Bus validation ? */
879         if (pe->pbus) {
880                 int count;
881
882                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
883                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
884                 parent = pe->pbus->self;
885                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
886                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
887                 else
888                         count = 1;
889
890                 switch(count) {
891                 case  1: bcomp = OpalPciBusAll;         break;
892                 case  2: bcomp = OpalPciBus7Bits;       break;
893                 case  4: bcomp = OpalPciBus6Bits;       break;
894                 case  8: bcomp = OpalPciBus5Bits;       break;
895                 case 16: bcomp = OpalPciBus4Bits;       break;
896                 case 32: bcomp = OpalPciBus3Bits;       break;
897                 default:
898                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
899                                 count);
900                         /* Do an exact match only */
901                         bcomp = OpalPciBusAll;
902                 }
903                 rid_end = pe->rid + (count << 8);
904         } else {
905 #ifdef CONFIG_PCI_IOV
906                 if (pe->flags & PNV_IODA_PE_VF)
907                         parent = pe->parent_dev;
908                 else
909 #endif /* CONFIG_PCI_IOV */
910                         parent = pe->pdev->bus->self;
911                 bcomp = OpalPciBusAll;
912                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
913                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
914                 rid_end = pe->rid + 1;
915         }
916
917         /*
918          * Associate PE in PELT. We need add the PE into the
919          * corresponding PELT-V as well. Otherwise, the error
920          * originated from the PE might contribute to other
921          * PEs.
922          */
923         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
924                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
925         if (rc) {
926                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
927                 return -ENXIO;
928         }
929
930         /*
931          * Configure PELTV. NPUs don't have a PELTV table so skip
932          * configuration on them.
933          */
934         if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
935                 pnv_ioda_set_peltv(phb, pe, true);
936
937         /* Setup reverse map */
938         for (rid = pe->rid; rid < rid_end; rid++)
939                 phb->ioda.pe_rmap[rid] = pe->pe_number;
940
941         /* Setup one MVTs on IODA1 */
942         if (phb->type != PNV_PHB_IODA1) {
943                 pe->mve_number = 0;
944                 goto out;
945         }
946
947         pe->mve_number = pe->pe_number;
948         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
949         if (rc != OPAL_SUCCESS) {
950                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
951                        rc, pe->mve_number);
952                 pe->mve_number = -1;
953         } else {
954                 rc = opal_pci_set_mve_enable(phb->opal_id,
955                                              pe->mve_number, OPAL_ENABLE_MVE);
956                 if (rc) {
957                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
958                                rc, pe->mve_number);
959                         pe->mve_number = -1;
960                 }
961         }
962
963 out:
964         return 0;
965 }
966
967 #ifdef CONFIG_PCI_IOV
968 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
969 {
970         struct pci_dn *pdn = pci_get_pdn(dev);
971         int i;
972         struct resource *res, res2;
973         resource_size_t size;
974         u16 num_vfs;
975
976         if (!dev->is_physfn)
977                 return -EINVAL;
978
979         /*
980          * "offset" is in VFs.  The M64 windows are sized so that when they
981          * are segmented, each segment is the same size as the IOV BAR.
982          * Each segment is in a separate PE, and the high order bits of the
983          * address are the PE number.  Therefore, each VF's BAR is in a
984          * separate PE, and changing the IOV BAR start address changes the
985          * range of PEs the VFs are in.
986          */
987         num_vfs = pdn->num_vfs;
988         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
989                 res = &dev->resource[i + PCI_IOV_RESOURCES];
990                 if (!res->flags || !res->parent)
991                         continue;
992
993                 /*
994                  * The actual IOV BAR range is determined by the start address
995                  * and the actual size for num_vfs VFs BAR.  This check is to
996                  * make sure that after shifting, the range will not overlap
997                  * with another device.
998                  */
999                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1000                 res2.flags = res->flags;
1001                 res2.start = res->start + (size * offset);
1002                 res2.end = res2.start + (size * num_vfs) - 1;
1003
1004                 if (res2.end > res->end) {
1005                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1006                                 i, &res2, res, num_vfs, offset);
1007                         return -EBUSY;
1008                 }
1009         }
1010
1011         /*
1012          * Since M64 BAR shares segments among all possible 256 PEs,
1013          * we have to shift the beginning of PF IOV BAR to make it start from
1014          * the segment which belongs to the PE number assigned to the first VF.
1015          * This creates a "hole" in the /proc/iomem which could be used for
1016          * allocating other resources so we reserve this area below and
1017          * release when IOV is released.
1018          */
1019         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1020                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1021                 if (!res->flags || !res->parent)
1022                         continue;
1023
1024                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1025                 res2 = *res;
1026                 res->start += size * offset;
1027
1028                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1029                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1030                          num_vfs, offset);
1031
1032                 if (offset < 0) {
1033                         devm_release_resource(&dev->dev, &pdn->holes[i]);
1034                         memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1035                 }
1036
1037                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1038
1039                 if (offset > 0) {
1040                         pdn->holes[i].start = res2.start;
1041                         pdn->holes[i].end = res2.start + size * offset - 1;
1042                         pdn->holes[i].flags = IORESOURCE_BUS;
1043                         pdn->holes[i].name = "pnv_iov_reserved";
1044                         devm_request_resource(&dev->dev, res->parent,
1045                                         &pdn->holes[i]);
1046                 }
1047         }
1048         return 0;
1049 }
1050 #endif /* CONFIG_PCI_IOV */
1051
1052 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1053 {
1054         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1055         struct pnv_phb *phb = hose->private_data;
1056         struct pci_dn *pdn = pci_get_pdn(dev);
1057         struct pnv_ioda_pe *pe;
1058
1059         if (!pdn) {
1060                 pr_err("%s: Device tree node not associated properly\n",
1061                            pci_name(dev));
1062                 return NULL;
1063         }
1064         if (pdn->pe_number != IODA_INVALID_PE)
1065                 return NULL;
1066
1067         pe = pnv_ioda_alloc_pe(phb);
1068         if (!pe) {
1069                 pr_warn("%s: Not enough PE# available, disabling device\n",
1070                         pci_name(dev));
1071                 return NULL;
1072         }
1073
1074         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1075          * pointer in the PE data structure, both should be destroyed at the
1076          * same time. However, this needs to be looked at more closely again
1077          * once we actually start removing things (Hotplug, SR-IOV, ...)
1078          *
1079          * At some point we want to remove the PDN completely anyways
1080          */
1081         pci_dev_get(dev);
1082         pdn->pe_number = pe->pe_number;
1083         pe->flags = PNV_IODA_PE_DEV;
1084         pe->pdev = dev;
1085         pe->pbus = NULL;
1086         pe->mve_number = -1;
1087         pe->rid = dev->bus->number << 8 | pdn->devfn;
1088
1089         pe_info(pe, "Associated device to PE\n");
1090
1091         if (pnv_ioda_configure_pe(phb, pe)) {
1092                 /* XXX What do we do here ? */
1093                 pnv_ioda_free_pe(pe);
1094                 pdn->pe_number = IODA_INVALID_PE;
1095                 pe->pdev = NULL;
1096                 pci_dev_put(dev);
1097                 return NULL;
1098         }
1099
1100         /* Put PE to the list */
1101         list_add_tail(&pe->list, &phb->ioda.pe_list);
1102
1103         return pe;
1104 }
1105
1106 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1107 {
1108         struct pci_dev *dev;
1109
1110         list_for_each_entry(dev, &bus->devices, bus_list) {
1111                 struct pci_dn *pdn = pci_get_pdn(dev);
1112
1113                 if (pdn == NULL) {
1114                         pr_warn("%s: No device node associated with device !\n",
1115                                 pci_name(dev));
1116                         continue;
1117                 }
1118
1119                 /*
1120                  * In partial hotplug case, the PCI device might be still
1121                  * associated with the PE and needn't attach it to the PE
1122                  * again.
1123                  */
1124                 if (pdn->pe_number != IODA_INVALID_PE)
1125                         continue;
1126
1127                 pe->device_count++;
1128                 pdn->pe_number = pe->pe_number;
1129                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1130                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1131         }
1132 }
1133
1134 /*
1135  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1136  * single PCI bus. Another one that contains the primary PCI bus and its
1137  * subordinate PCI devices and buses. The second type of PE is normally
1138  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1139  */
1140 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1141 {
1142         struct pci_controller *hose = pci_bus_to_host(bus);
1143         struct pnv_phb *phb = hose->private_data;
1144         struct pnv_ioda_pe *pe = NULL;
1145         unsigned int pe_num;
1146
1147         /*
1148          * In partial hotplug case, the PE instance might be still alive.
1149          * We should reuse it instead of allocating a new one.
1150          */
1151         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1152         if (pe_num != IODA_INVALID_PE) {
1153                 pe = &phb->ioda.pe_array[pe_num];
1154                 pnv_ioda_setup_same_PE(bus, pe);
1155                 return NULL;
1156         }
1157
1158         /* PE number for root bus should have been reserved */
1159         if (pci_is_root_bus(bus) &&
1160             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1161                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1162
1163         /* Check if PE is determined by M64 */
1164         if (!pe && phb->pick_m64_pe)
1165                 pe = phb->pick_m64_pe(bus, all);
1166
1167         /* The PE number isn't pinned by M64 */
1168         if (!pe)
1169                 pe = pnv_ioda_alloc_pe(phb);
1170
1171         if (!pe) {
1172                 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1173                         __func__, pci_domain_nr(bus), bus->number);
1174                 return NULL;
1175         }
1176
1177         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1178         pe->pbus = bus;
1179         pe->pdev = NULL;
1180         pe->mve_number = -1;
1181         pe->rid = bus->busn_res.start << 8;
1182
1183         if (all)
1184                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1185                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1186         else
1187                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1188                         bus->busn_res.start, pe->pe_number);
1189
1190         if (pnv_ioda_configure_pe(phb, pe)) {
1191                 /* XXX What do we do here ? */
1192                 pnv_ioda_free_pe(pe);
1193                 pe->pbus = NULL;
1194                 return NULL;
1195         }
1196
1197         /* Associate it with all child devices */
1198         pnv_ioda_setup_same_PE(bus, pe);
1199
1200         /* Put PE to the list */
1201         list_add_tail(&pe->list, &phb->ioda.pe_list);
1202
1203         return pe;
1204 }
1205
1206 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1207 {
1208         int pe_num, found_pe = false, rc;
1209         long rid;
1210         struct pnv_ioda_pe *pe;
1211         struct pci_dev *gpu_pdev;
1212         struct pci_dn *npu_pdn;
1213         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1214         struct pnv_phb *phb = hose->private_data;
1215
1216         /*
1217          * Due to a hardware errata PE#0 on the NPU is reserved for
1218          * error handling. This means we only have three PEs remaining
1219          * which need to be assigned to four links, implying some
1220          * links must share PEs.
1221          *
1222          * To achieve this we assign PEs such that NPUs linking the
1223          * same GPU get assigned the same PE.
1224          */
1225         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1226         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1227                 pe = &phb->ioda.pe_array[pe_num];
1228                 if (!pe->pdev)
1229                         continue;
1230
1231                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1232                         /*
1233                          * This device has the same peer GPU so should
1234                          * be assigned the same PE as the existing
1235                          * peer NPU.
1236                          */
1237                         dev_info(&npu_pdev->dev,
1238                                 "Associating to existing PE %x\n", pe_num);
1239                         pci_dev_get(npu_pdev);
1240                         npu_pdn = pci_get_pdn(npu_pdev);
1241                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1242                         npu_pdn->pe_number = pe_num;
1243                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1244
1245                         /* Map the PE to this link */
1246                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1247                                         OpalPciBusAll,
1248                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1249                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1250                                         OPAL_MAP_PE);
1251                         WARN_ON(rc != OPAL_SUCCESS);
1252                         found_pe = true;
1253                         break;
1254                 }
1255         }
1256
1257         if (!found_pe)
1258                 /*
1259                  * Could not find an existing PE so allocate a new
1260                  * one.
1261                  */
1262                 return pnv_ioda_setup_dev_PE(npu_pdev);
1263         else
1264                 return pe;
1265 }
1266
1267 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1268 {
1269         struct pci_dev *pdev;
1270
1271         list_for_each_entry(pdev, &bus->devices, bus_list)
1272                 pnv_ioda_setup_npu_PE(pdev);
1273 }
1274
1275 static void pnv_pci_ioda_setup_PEs(void)
1276 {
1277         struct pci_controller *hose, *tmp;
1278         struct pnv_phb *phb;
1279         struct pci_bus *bus;
1280         struct pci_dev *pdev;
1281
1282         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1283                 phb = hose->private_data;
1284                 if (phb->type == PNV_PHB_NPU_NVLINK) {
1285                         /* PE#0 is needed for error reporting */
1286                         pnv_ioda_reserve_pe(phb, 0);
1287                         pnv_ioda_setup_npu_PEs(hose->bus);
1288                         if (phb->model == PNV_PHB_MODEL_NPU2)
1289                                 pnv_npu2_init(phb);
1290                 }
1291                 if (phb->type == PNV_PHB_NPU_OCAPI) {
1292                         bus = hose->bus;
1293                         list_for_each_entry(pdev, &bus->devices, bus_list)
1294                                 pnv_ioda_setup_dev_PE(pdev);
1295                 }
1296         }
1297 }
1298
1299 #ifdef CONFIG_PCI_IOV
1300 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1301 {
1302         struct pci_bus        *bus;
1303         struct pci_controller *hose;
1304         struct pnv_phb        *phb;
1305         struct pci_dn         *pdn;
1306         int                    i, j;
1307         int                    m64_bars;
1308
1309         bus = pdev->bus;
1310         hose = pci_bus_to_host(bus);
1311         phb = hose->private_data;
1312         pdn = pci_get_pdn(pdev);
1313
1314         if (pdn->m64_single_mode)
1315                 m64_bars = num_vfs;
1316         else
1317                 m64_bars = 1;
1318
1319         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1320                 for (j = 0; j < m64_bars; j++) {
1321                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1322                                 continue;
1323                         opal_pci_phb_mmio_enable(phb->opal_id,
1324                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1325                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1326                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1327                 }
1328
1329         kfree(pdn->m64_map);
1330         return 0;
1331 }
1332
1333 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1334 {
1335         struct pci_bus        *bus;
1336         struct pci_controller *hose;
1337         struct pnv_phb        *phb;
1338         struct pci_dn         *pdn;
1339         unsigned int           win;
1340         struct resource       *res;
1341         int                    i, j;
1342         int64_t                rc;
1343         int                    total_vfs;
1344         resource_size_t        size, start;
1345         int                    pe_num;
1346         int                    m64_bars;
1347
1348         bus = pdev->bus;
1349         hose = pci_bus_to_host(bus);
1350         phb = hose->private_data;
1351         pdn = pci_get_pdn(pdev);
1352         total_vfs = pci_sriov_get_totalvfs(pdev);
1353
1354         if (pdn->m64_single_mode)
1355                 m64_bars = num_vfs;
1356         else
1357                 m64_bars = 1;
1358
1359         pdn->m64_map = kmalloc_array(m64_bars,
1360                                      sizeof(*pdn->m64_map),
1361                                      GFP_KERNEL);
1362         if (!pdn->m64_map)
1363                 return -ENOMEM;
1364         /* Initialize the m64_map to IODA_INVALID_M64 */
1365         for (i = 0; i < m64_bars ; i++)
1366                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1367                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1368
1369
1370         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1371                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1372                 if (!res->flags || !res->parent)
1373                         continue;
1374
1375                 for (j = 0; j < m64_bars; j++) {
1376                         do {
1377                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1378                                                 phb->ioda.m64_bar_idx + 1, 0);
1379
1380                                 if (win >= phb->ioda.m64_bar_idx + 1)
1381                                         goto m64_failed;
1382                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1383
1384                         pdn->m64_map[j][i] = win;
1385
1386                         if (pdn->m64_single_mode) {
1387                                 size = pci_iov_resource_size(pdev,
1388                                                         PCI_IOV_RESOURCES + i);
1389                                 start = res->start + size * j;
1390                         } else {
1391                                 size = resource_size(res);
1392                                 start = res->start;
1393                         }
1394
1395                         /* Map the M64 here */
1396                         if (pdn->m64_single_mode) {
1397                                 pe_num = pdn->pe_num_map[j];
1398                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1399                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1400                                                 pdn->m64_map[j][i], 0);
1401                         }
1402
1403                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1404                                                  OPAL_M64_WINDOW_TYPE,
1405                                                  pdn->m64_map[j][i],
1406                                                  start,
1407                                                  0, /* unused */
1408                                                  size);
1409
1410
1411                         if (rc != OPAL_SUCCESS) {
1412                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1413                                         win, rc);
1414                                 goto m64_failed;
1415                         }
1416
1417                         if (pdn->m64_single_mode)
1418                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1419                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1420                         else
1421                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1422                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1423
1424                         if (rc != OPAL_SUCCESS) {
1425                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1426                                         win, rc);
1427                                 goto m64_failed;
1428                         }
1429                 }
1430         }
1431         return 0;
1432
1433 m64_failed:
1434         pnv_pci_vf_release_m64(pdev, num_vfs);
1435         return -EBUSY;
1436 }
1437
1438 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1439                 int num);
1440
1441 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1442 {
1443         struct iommu_table    *tbl;
1444         int64_t               rc;
1445
1446         tbl = pe->table_group.tables[0];
1447         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1448         if (rc)
1449                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1450
1451         pnv_pci_ioda2_set_bypass(pe, false);
1452         if (pe->table_group.group) {
1453                 iommu_group_put(pe->table_group.group);
1454                 BUG_ON(pe->table_group.group);
1455         }
1456         iommu_tce_table_put(tbl);
1457 }
1458
1459 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1460 {
1461         struct pci_bus        *bus;
1462         struct pci_controller *hose;
1463         struct pnv_phb        *phb;
1464         struct pnv_ioda_pe    *pe, *pe_n;
1465         struct pci_dn         *pdn;
1466
1467         bus = pdev->bus;
1468         hose = pci_bus_to_host(bus);
1469         phb = hose->private_data;
1470         pdn = pci_get_pdn(pdev);
1471
1472         if (!pdev->is_physfn)
1473                 return;
1474
1475         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1476                 if (pe->parent_dev != pdev)
1477                         continue;
1478
1479                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1480
1481                 /* Remove from list */
1482                 mutex_lock(&phb->ioda.pe_list_mutex);
1483                 list_del(&pe->list);
1484                 mutex_unlock(&phb->ioda.pe_list_mutex);
1485
1486                 pnv_ioda_deconfigure_pe(phb, pe);
1487
1488                 pnv_ioda_free_pe(pe);
1489         }
1490 }
1491
1492 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1493 {
1494         struct pci_bus        *bus;
1495         struct pci_controller *hose;
1496         struct pnv_phb        *phb;
1497         struct pnv_ioda_pe    *pe;
1498         struct pci_dn         *pdn;
1499         u16                    num_vfs, i;
1500
1501         bus = pdev->bus;
1502         hose = pci_bus_to_host(bus);
1503         phb = hose->private_data;
1504         pdn = pci_get_pdn(pdev);
1505         num_vfs = pdn->num_vfs;
1506
1507         /* Release VF PEs */
1508         pnv_ioda_release_vf_PE(pdev);
1509
1510         if (phb->type == PNV_PHB_IODA2) {
1511                 if (!pdn->m64_single_mode)
1512                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1513
1514                 /* Release M64 windows */
1515                 pnv_pci_vf_release_m64(pdev, num_vfs);
1516
1517                 /* Release PE numbers */
1518                 if (pdn->m64_single_mode) {
1519                         for (i = 0; i < num_vfs; i++) {
1520                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1521                                         continue;
1522
1523                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1524                                 pnv_ioda_free_pe(pe);
1525                         }
1526                 } else
1527                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1528                 /* Releasing pe_num_map */
1529                 kfree(pdn->pe_num_map);
1530         }
1531 }
1532
1533 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1534                                        struct pnv_ioda_pe *pe);
1535 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1536 {
1537         struct pci_bus        *bus;
1538         struct pci_controller *hose;
1539         struct pnv_phb        *phb;
1540         struct pnv_ioda_pe    *pe;
1541         int                    pe_num;
1542         u16                    vf_index;
1543         struct pci_dn         *pdn;
1544
1545         bus = pdev->bus;
1546         hose = pci_bus_to_host(bus);
1547         phb = hose->private_data;
1548         pdn = pci_get_pdn(pdev);
1549
1550         if (!pdev->is_physfn)
1551                 return;
1552
1553         /* Reserve PE for each VF */
1554         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1555                 if (pdn->m64_single_mode)
1556                         pe_num = pdn->pe_num_map[vf_index];
1557                 else
1558                         pe_num = *pdn->pe_num_map + vf_index;
1559
1560                 pe = &phb->ioda.pe_array[pe_num];
1561                 pe->pe_number = pe_num;
1562                 pe->phb = phb;
1563                 pe->flags = PNV_IODA_PE_VF;
1564                 pe->pbus = NULL;
1565                 pe->parent_dev = pdev;
1566                 pe->mve_number = -1;
1567                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1568                            pci_iov_virtfn_devfn(pdev, vf_index);
1569
1570                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1571                         hose->global_number, pdev->bus->number,
1572                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1573                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1574
1575                 if (pnv_ioda_configure_pe(phb, pe)) {
1576                         /* XXX What do we do here ? */
1577                         pnv_ioda_free_pe(pe);
1578                         pe->pdev = NULL;
1579                         continue;
1580                 }
1581
1582                 /* Put PE to the list */
1583                 mutex_lock(&phb->ioda.pe_list_mutex);
1584                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1585                 mutex_unlock(&phb->ioda.pe_list_mutex);
1586
1587                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1588         }
1589 }
1590
1591 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1592 {
1593         struct pci_bus        *bus;
1594         struct pci_controller *hose;
1595         struct pnv_phb        *phb;
1596         struct pnv_ioda_pe    *pe;
1597         struct pci_dn         *pdn;
1598         int                    ret;
1599         u16                    i;
1600
1601         bus = pdev->bus;
1602         hose = pci_bus_to_host(bus);
1603         phb = hose->private_data;
1604         pdn = pci_get_pdn(pdev);
1605
1606         if (phb->type == PNV_PHB_IODA2) {
1607                 if (!pdn->vfs_expanded) {
1608                         dev_info(&pdev->dev, "don't support this SRIOV device"
1609                                 " with non 64bit-prefetchable IOV BAR\n");
1610                         return -ENOSPC;
1611                 }
1612
1613                 /*
1614                  * When M64 BARs functions in Single PE mode, the number of VFs
1615                  * could be enabled must be less than the number of M64 BARs.
1616                  */
1617                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1618                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1619                         return -EBUSY;
1620                 }
1621
1622                 /* Allocating pe_num_map */
1623                 if (pdn->m64_single_mode)
1624                         pdn->pe_num_map = kmalloc_array(num_vfs,
1625                                                         sizeof(*pdn->pe_num_map),
1626                                                         GFP_KERNEL);
1627                 else
1628                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1629
1630                 if (!pdn->pe_num_map)
1631                         return -ENOMEM;
1632
1633                 if (pdn->m64_single_mode)
1634                         for (i = 0; i < num_vfs; i++)
1635                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1636
1637                 /* Calculate available PE for required VFs */
1638                 if (pdn->m64_single_mode) {
1639                         for (i = 0; i < num_vfs; i++) {
1640                                 pe = pnv_ioda_alloc_pe(phb);
1641                                 if (!pe) {
1642                                         ret = -EBUSY;
1643                                         goto m64_failed;
1644                                 }
1645
1646                                 pdn->pe_num_map[i] = pe->pe_number;
1647                         }
1648                 } else {
1649                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1650                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1651                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1652                                 0, num_vfs, 0);
1653                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1654                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1655                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1656                                 kfree(pdn->pe_num_map);
1657                                 return -EBUSY;
1658                         }
1659                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1660                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1661                 }
1662                 pdn->num_vfs = num_vfs;
1663
1664                 /* Assign M64 window accordingly */
1665                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1666                 if (ret) {
1667                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1668                         goto m64_failed;
1669                 }
1670
1671                 /*
1672                  * When using one M64 BAR to map one IOV BAR, we need to shift
1673                  * the IOV BAR according to the PE# allocated to the VFs.
1674                  * Otherwise, the PE# for the VF will conflict with others.
1675                  */
1676                 if (!pdn->m64_single_mode) {
1677                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1678                         if (ret)
1679                                 goto m64_failed;
1680                 }
1681         }
1682
1683         /* Setup VF PEs */
1684         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1685
1686         return 0;
1687
1688 m64_failed:
1689         if (pdn->m64_single_mode) {
1690                 for (i = 0; i < num_vfs; i++) {
1691                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1692                                 continue;
1693
1694                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1695                         pnv_ioda_free_pe(pe);
1696                 }
1697         } else
1698                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1699
1700         /* Releasing pe_num_map */
1701         kfree(pdn->pe_num_map);
1702
1703         return ret;
1704 }
1705
1706 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1707 {
1708         pnv_pci_sriov_disable(pdev);
1709
1710         /* Release PCI data */
1711         remove_dev_pci_data(pdev);
1712         return 0;
1713 }
1714
1715 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1716 {
1717         /* Allocate PCI data */
1718         add_dev_pci_data(pdev);
1719
1720         return pnv_pci_sriov_enable(pdev, num_vfs);
1721 }
1722 #endif /* CONFIG_PCI_IOV */
1723
1724 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1725 {
1726         struct pci_dn *pdn = pci_get_pdn(pdev);
1727         struct pnv_ioda_pe *pe;
1728
1729         /*
1730          * The function can be called while the PE#
1731          * hasn't been assigned. Do nothing for the
1732          * case.
1733          */
1734         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1735                 return;
1736
1737         pe = &phb->ioda.pe_array[pdn->pe_number];
1738         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1739         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1740         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1741         /*
1742          * Note: iommu_add_device() will fail here as
1743          * for physical PE: the device is already added by now;
1744          * for virtual PE: sysfs entries are not ready yet and
1745          * tce_iommu_bus_notifier will add the device to a group later.
1746          */
1747 }
1748
1749 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1750 {
1751         unsigned short vendor = 0;
1752         struct pci_dev *pdev;
1753
1754         if (pe->device_count == 1)
1755                 return true;
1756
1757         /* pe->pdev should be set if it's a single device, pe->pbus if not */
1758         if (!pe->pbus)
1759                 return true;
1760
1761         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1762                 if (!vendor) {
1763                         vendor = pdev->vendor;
1764                         continue;
1765                 }
1766
1767                 if (pdev->vendor != vendor)
1768                         return false;
1769         }
1770
1771         return true;
1772 }
1773
1774 /*
1775  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1776  *
1777  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1778  * Devices can only access more than that if bit 59 of the PCI address is set
1779  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1780  * Many PCI devices are not capable of addressing that many bits, and as a
1781  * result are limited to the 4GB of virtual memory made available to 32-bit
1782  * devices in TVE#0.
1783  *
1784  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1785  * devices by configuring the virtual memory past the first 4GB inaccessible
1786  * by 64-bit DMAs.  This should only be used by devices that want more than
1787  * 4GB, and only on PEs that have no 32-bit devices.
1788  *
1789  * Currently this will only work on PHB3 (POWER8).
1790  */
1791 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1792 {
1793         u64 window_size, table_size, tce_count, addr;
1794         struct page *table_pages;
1795         u64 tce_order = 28; /* 256MB TCEs */
1796         __be64 *tces;
1797         s64 rc;
1798
1799         /*
1800          * Window size needs to be a power of two, but needs to account for
1801          * shifting memory by the 4GB offset required to skip 32bit space.
1802          */
1803         window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1804         tce_count = window_size >> tce_order;
1805         table_size = tce_count << 3;
1806
1807         if (table_size < PAGE_SIZE)
1808                 table_size = PAGE_SIZE;
1809
1810         table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1811                                        get_order(table_size));
1812         if (!table_pages)
1813                 goto err;
1814
1815         tces = page_address(table_pages);
1816         if (!tces)
1817                 goto err;
1818
1819         memset(tces, 0, table_size);
1820
1821         for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1822                 tces[(addr + (1ULL << 32)) >> tce_order] =
1823                         cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1824         }
1825
1826         rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1827                                         pe->pe_number,
1828                                         /* reconfigure window 0 */
1829                                         (pe->pe_number << 1) + 0,
1830                                         1,
1831                                         __pa(tces),
1832                                         table_size,
1833                                         1 << tce_order);
1834         if (rc == OPAL_SUCCESS) {
1835                 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1836                 return 0;
1837         }
1838 err:
1839         pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1840         return -EIO;
1841 }
1842
1843 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1844 {
1845         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1846         struct pnv_phb *phb = hose->private_data;
1847         struct pci_dn *pdn = pci_get_pdn(pdev);
1848         struct pnv_ioda_pe *pe;
1849         uint64_t top;
1850         bool bypass = false;
1851         s64 rc;
1852
1853         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1854                 return -ENODEV;
1855
1856         pe = &phb->ioda.pe_array[pdn->pe_number];
1857         if (pe->tce_bypass_enabled) {
1858                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1859                 bypass = (dma_mask >= top);
1860         }
1861
1862         if (bypass) {
1863                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1864                 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1865         } else {
1866                 /*
1867                  * If the device can't set the TCE bypass bit but still wants
1868                  * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1869                  * bypass the 32-bit region and be usable for 64-bit DMAs.
1870                  * The device needs to be able to address all of this space.
1871                  */
1872                 if (dma_mask >> 32 &&
1873                     dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1874                     pnv_pci_ioda_pe_single_vendor(pe) &&
1875                     phb->model == PNV_PHB_MODEL_PHB3) {
1876                         /* Configure the bypass mode */
1877                         rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1878                         if (rc)
1879                                 return rc;
1880                         /* 4GB offset bypasses 32-bit space */
1881                         set_dma_offset(&pdev->dev, (1ULL << 32));
1882                         set_dma_ops(&pdev->dev, &dma_nommu_ops);
1883                 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1884                         /*
1885                          * Fail the request if a DMA mask between 32 and 64 bits
1886                          * was requested but couldn't be fulfilled. Ideally we
1887                          * would do this for 64-bits but historically we have
1888                          * always fallen back to 32-bits.
1889                          */
1890                         return -ENOMEM;
1891                 } else {
1892                         dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1893                         set_dma_ops(&pdev->dev, &dma_iommu_ops);
1894                 }
1895         }
1896         *pdev->dev.dma_mask = dma_mask;
1897
1898         /* Update peer npu devices */
1899         pnv_npu_try_dma_set_bypass(pdev, bypass);
1900
1901         return 0;
1902 }
1903
1904 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1905 {
1906         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1907         struct pnv_phb *phb = hose->private_data;
1908         struct pci_dn *pdn = pci_get_pdn(pdev);
1909         struct pnv_ioda_pe *pe;
1910         u64 end, mask;
1911
1912         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1913                 return 0;
1914
1915         pe = &phb->ioda.pe_array[pdn->pe_number];
1916         if (!pe->tce_bypass_enabled)
1917                 return __dma_get_required_mask(&pdev->dev);
1918
1919
1920         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1921         mask = 1ULL << (fls64(end) - 1);
1922         mask += mask - 1;
1923
1924         return mask;
1925 }
1926
1927 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1928                                    struct pci_bus *bus,
1929                                    bool add_to_group)
1930 {
1931         struct pci_dev *dev;
1932
1933         list_for_each_entry(dev, &bus->devices, bus_list) {
1934                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1935                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1936                 if (add_to_group)
1937                         iommu_add_device(&dev->dev);
1938
1939                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1940                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1941                                         add_to_group);
1942         }
1943 }
1944
1945 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1946                                                      bool real_mode)
1947 {
1948         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1949                 (phb->regs + 0x210);
1950 }
1951
1952 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1953                 unsigned long index, unsigned long npages, bool rm)
1954 {
1955         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1956                         &tbl->it_group_list, struct iommu_table_group_link,
1957                         next);
1958         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1959                         struct pnv_ioda_pe, table_group);
1960         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1961         unsigned long start, end, inc;
1962
1963         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1964         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1965                         npages - 1);
1966
1967         /* p7ioc-style invalidation, 2 TCEs per write */
1968         start |= (1ull << 63);
1969         end |= (1ull << 63);
1970         inc = 16;
1971         end |= inc - 1; /* round up end to be different than start */
1972
1973         mb(); /* Ensure above stores are visible */
1974         while (start <= end) {
1975                 if (rm)
1976                         __raw_rm_writeq_be(start, invalidate);
1977                 else
1978                         __raw_writeq_be(start, invalidate);
1979
1980                 start += inc;
1981         }
1982
1983         /*
1984          * The iommu layer will do another mb() for us on build()
1985          * and we don't care on free()
1986          */
1987 }
1988
1989 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1990                 long npages, unsigned long uaddr,
1991                 enum dma_data_direction direction,
1992                 unsigned long attrs)
1993 {
1994         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1995                         attrs);
1996
1997         if (!ret)
1998                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1999
2000         return ret;
2001 }
2002
2003 #ifdef CONFIG_IOMMU_API
2004 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
2005                 unsigned long *hpa, enum dma_data_direction *direction)
2006 {
2007         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2008
2009         if (!ret)
2010                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
2011
2012         return ret;
2013 }
2014
2015 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
2016                 unsigned long *hpa, enum dma_data_direction *direction)
2017 {
2018         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2019
2020         if (!ret)
2021                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2022
2023         return ret;
2024 }
2025 #endif
2026
2027 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2028                 long npages)
2029 {
2030         pnv_tce_free(tbl, index, npages);
2031
2032         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2033 }
2034
2035 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2036         .set = pnv_ioda1_tce_build,
2037 #ifdef CONFIG_IOMMU_API
2038         .exchange = pnv_ioda1_tce_xchg,
2039         .exchange_rm = pnv_ioda1_tce_xchg_rm,
2040         .useraddrptr = pnv_tce_useraddrptr,
2041 #endif
2042         .clear = pnv_ioda1_tce_free,
2043         .get = pnv_tce_get,
2044 };
2045
2046 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
2047 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
2048 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
2049
2050 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2051 {
2052         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2053         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2054
2055         mb(); /* Ensure previous TCE table stores are visible */
2056         if (rm)
2057                 __raw_rm_writeq_be(val, invalidate);
2058         else
2059                 __raw_writeq_be(val, invalidate);
2060 }
2061
2062 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2063 {
2064         /* 01xb - invalidate TCEs that match the specified PE# */
2065         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2066         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2067
2068         mb(); /* Ensure above stores are visible */
2069         __raw_writeq_be(val, invalidate);
2070 }
2071
2072 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2073                                         unsigned shift, unsigned long index,
2074                                         unsigned long npages)
2075 {
2076         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2077         unsigned long start, end, inc;
2078
2079         /* We'll invalidate DMA address in PE scope */
2080         start = PHB3_TCE_KILL_INVAL_ONE;
2081         start |= (pe->pe_number & 0xFF);
2082         end = start;
2083
2084         /* Figure out the start, end and step */
2085         start |= (index << shift);
2086         end |= ((index + npages - 1) << shift);
2087         inc = (0x1ull << shift);
2088         mb();
2089
2090         while (start <= end) {
2091                 if (rm)
2092                         __raw_rm_writeq_be(start, invalidate);
2093                 else
2094                         __raw_writeq_be(start, invalidate);
2095                 start += inc;
2096         }
2097 }
2098
2099 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2100 {
2101         struct pnv_phb *phb = pe->phb;
2102
2103         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2104                 pnv_pci_phb3_tce_invalidate_pe(pe);
2105         else
2106                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2107                                   pe->pe_number, 0, 0, 0);
2108 }
2109
2110 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2111                 unsigned long index, unsigned long npages, bool rm)
2112 {
2113         struct iommu_table_group_link *tgl;
2114
2115         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2116                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2117                                 struct pnv_ioda_pe, table_group);
2118                 struct pnv_phb *phb = pe->phb;
2119                 unsigned int shift = tbl->it_page_shift;
2120
2121                 /*
2122                  * NVLink1 can use the TCE kill register directly as
2123                  * it's the same as PHB3. NVLink2 is different and
2124                  * should go via the OPAL call.
2125                  */
2126                 if (phb->model == PNV_PHB_MODEL_NPU) {
2127                         /*
2128                          * The NVLink hardware does not support TCE kill
2129                          * per TCE entry so we have to invalidate
2130                          * the entire cache for it.
2131                          */
2132                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2133                         continue;
2134                 }
2135                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2136                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2137                                                     index, npages);
2138                 else
2139                         opal_pci_tce_kill(phb->opal_id,
2140                                           OPAL_PCI_TCE_KILL_PAGES,
2141                                           pe->pe_number, 1u << shift,
2142                                           index << shift, npages);
2143         }
2144 }
2145
2146 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2147 {
2148         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2149                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2150         else
2151                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2152 }
2153
2154 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2155                 long npages, unsigned long uaddr,
2156                 enum dma_data_direction direction,
2157                 unsigned long attrs)
2158 {
2159         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2160                         attrs);
2161
2162         if (!ret)
2163                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2164
2165         return ret;
2166 }
2167
2168 #ifdef CONFIG_IOMMU_API
2169 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2170                 unsigned long *hpa, enum dma_data_direction *direction)
2171 {
2172         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2173
2174         if (!ret)
2175                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2176
2177         return ret;
2178 }
2179
2180 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2181                 unsigned long *hpa, enum dma_data_direction *direction)
2182 {
2183         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2184
2185         if (!ret)
2186                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2187
2188         return ret;
2189 }
2190 #endif
2191
2192 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2193                 long npages)
2194 {
2195         pnv_tce_free(tbl, index, npages);
2196
2197         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2198 }
2199
2200 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2201         .set = pnv_ioda2_tce_build,
2202 #ifdef CONFIG_IOMMU_API
2203         .exchange = pnv_ioda2_tce_xchg,
2204         .exchange_rm = pnv_ioda2_tce_xchg_rm,
2205         .useraddrptr = pnv_tce_useraddrptr,
2206 #endif
2207         .clear = pnv_ioda2_tce_free,
2208         .get = pnv_tce_get,
2209         .free = pnv_pci_ioda2_table_free_pages,
2210 };
2211
2212 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2213 {
2214         unsigned int *weight = (unsigned int *)data;
2215
2216         /* This is quite simplistic. The "base" weight of a device
2217          * is 10. 0 means no DMA is to be accounted for it.
2218          */
2219         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2220                 return 0;
2221
2222         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2223             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2224             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2225                 *weight += 3;
2226         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2227                 *weight += 15;
2228         else
2229                 *weight += 10;
2230
2231         return 0;
2232 }
2233
2234 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2235 {
2236         unsigned int weight = 0;
2237
2238         /* SRIOV VF has same DMA32 weight as its PF */
2239 #ifdef CONFIG_PCI_IOV
2240         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2241                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2242                 return weight;
2243         }
2244 #endif
2245
2246         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2247                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2248         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2249                 struct pci_dev *pdev;
2250
2251                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2252                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2253         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2254                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2255         }
2256
2257         return weight;
2258 }
2259
2260 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2261                                        struct pnv_ioda_pe *pe)
2262 {
2263
2264         struct page *tce_mem = NULL;
2265         struct iommu_table *tbl;
2266         unsigned int weight, total_weight = 0;
2267         unsigned int tce32_segsz, base, segs, avail, i;
2268         int64_t rc;
2269         void *addr;
2270
2271         /* XXX FIXME: Handle 64-bit only DMA devices */
2272         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2273         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2274         weight = pnv_pci_ioda_pe_dma_weight(pe);
2275         if (!weight)
2276                 return;
2277
2278         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2279                      &total_weight);
2280         segs = (weight * phb->ioda.dma32_count) / total_weight;
2281         if (!segs)
2282                 segs = 1;
2283
2284         /*
2285          * Allocate contiguous DMA32 segments. We begin with the expected
2286          * number of segments. With one more attempt, the number of DMA32
2287          * segments to be allocated is decreased by one until one segment
2288          * is allocated successfully.
2289          */
2290         do {
2291                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2292                         for (avail = 0, i = base; i < base + segs; i++) {
2293                                 if (phb->ioda.dma32_segmap[i] ==
2294                                     IODA_INVALID_PE)
2295                                         avail++;
2296                         }
2297
2298                         if (avail == segs)
2299                                 goto found;
2300                 }
2301         } while (--segs);
2302
2303         if (!segs) {
2304                 pe_warn(pe, "No available DMA32 segments\n");
2305                 return;
2306         }
2307
2308 found:
2309         tbl = pnv_pci_table_alloc(phb->hose->node);
2310         if (WARN_ON(!tbl))
2311                 return;
2312
2313         iommu_register_group(&pe->table_group, phb->hose->global_number,
2314                         pe->pe_number);
2315         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2316
2317         /* Grab a 32-bit TCE table */
2318         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2319                 weight, total_weight, base, segs);
2320         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2321                 base * PNV_IODA1_DMA32_SEGSIZE,
2322                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2323
2324         /* XXX Currently, we allocate one big contiguous table for the
2325          * TCEs. We only really need one chunk per 256M of TCE space
2326          * (ie per segment) but that's an optimization for later, it
2327          * requires some added smarts with our get/put_tce implementation
2328          *
2329          * Each TCE page is 4KB in size and each TCE entry occupies 8
2330          * bytes
2331          */
2332         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2333         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2334                                    get_order(tce32_segsz * segs));
2335         if (!tce_mem) {
2336                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2337                 goto fail;
2338         }
2339         addr = page_address(tce_mem);
2340         memset(addr, 0, tce32_segsz * segs);
2341
2342         /* Configure HW */
2343         for (i = 0; i < segs; i++) {
2344                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2345                                               pe->pe_number,
2346                                               base + i, 1,
2347                                               __pa(addr) + tce32_segsz * i,
2348                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2349                 if (rc) {
2350                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2351                                " err %ld\n", rc);
2352                         goto fail;
2353                 }
2354         }
2355
2356         /* Setup DMA32 segment mapping */
2357         for (i = base; i < base + segs; i++)
2358                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2359
2360         /* Setup linux iommu table */
2361         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2362                                   base * PNV_IODA1_DMA32_SEGSIZE,
2363                                   IOMMU_PAGE_SHIFT_4K);
2364
2365         tbl->it_ops = &pnv_ioda1_iommu_ops;
2366         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2367         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2368         iommu_init_table(tbl, phb->hose->node);
2369
2370         if (pe->flags & PNV_IODA_PE_DEV) {
2371                 /*
2372                  * Setting table base here only for carrying iommu_group
2373                  * further down to let iommu_add_device() do the job.
2374                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2375                  */
2376                 set_iommu_table_base(&pe->pdev->dev, tbl);
2377                 iommu_add_device(&pe->pdev->dev);
2378         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2379                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2380
2381         return;
2382  fail:
2383         /* XXX Failure: Try to fallback to 64-bit only ? */
2384         if (tce_mem)
2385                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2386         if (tbl) {
2387                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2388                 iommu_tce_table_put(tbl);
2389         }
2390 }
2391
2392 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2393                 int num, struct iommu_table *tbl)
2394 {
2395         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2396                         table_group);
2397         struct pnv_phb *phb = pe->phb;
2398         int64_t rc;
2399         const unsigned long size = tbl->it_indirect_levels ?
2400                         tbl->it_level_size : tbl->it_size;
2401         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2402         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2403
2404         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2405                         start_addr, start_addr + win_size - 1,
2406                         IOMMU_PAGE_SIZE(tbl));
2407
2408         /*
2409          * Map TCE table through TVT. The TVE index is the PE number
2410          * shifted by 1 bit for 32-bits DMA space.
2411          */
2412         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2413                         pe->pe_number,
2414                         (pe->pe_number << 1) + num,
2415                         tbl->it_indirect_levels + 1,
2416                         __pa(tbl->it_base),
2417                         size << 3,
2418                         IOMMU_PAGE_SIZE(tbl));
2419         if (rc) {
2420                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2421                 return rc;
2422         }
2423
2424         pnv_pci_link_table_and_group(phb->hose->node, num,
2425                         tbl, &pe->table_group);
2426         pnv_pci_ioda2_tce_invalidate_pe(pe);
2427
2428         return 0;
2429 }
2430
2431 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2432 {
2433         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2434         int64_t rc;
2435
2436         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2437         if (enable) {
2438                 phys_addr_t top = memblock_end_of_DRAM();
2439
2440                 top = roundup_pow_of_two(top);
2441                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2442                                                      pe->pe_number,
2443                                                      window_id,
2444                                                      pe->tce_bypass_base,
2445                                                      top);
2446         } else {
2447                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2448                                                      pe->pe_number,
2449                                                      window_id,
2450                                                      pe->tce_bypass_base,
2451                                                      0);
2452         }
2453         if (rc)
2454                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2455         else
2456                 pe->tce_bypass_enabled = enable;
2457 }
2458
2459 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2460                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2461                 bool alloc_userspace_copy, struct iommu_table **ptbl)
2462 {
2463         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2464                         table_group);
2465         int nid = pe->phb->hose->node;
2466         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2467         long ret;
2468         struct iommu_table *tbl;
2469
2470         tbl = pnv_pci_table_alloc(nid);
2471         if (!tbl)
2472                 return -ENOMEM;
2473
2474         tbl->it_ops = &pnv_ioda2_iommu_ops;
2475
2476         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2477                         bus_offset, page_shift, window_size,
2478                         levels, alloc_userspace_copy, tbl);
2479         if (ret) {
2480                 iommu_tce_table_put(tbl);
2481                 return ret;
2482         }
2483
2484         *ptbl = tbl;
2485
2486         return 0;
2487 }
2488
2489 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2490 {
2491         struct iommu_table *tbl = NULL;
2492         long rc;
2493
2494         /*
2495          * crashkernel= specifies the kdump kernel's maximum memory at
2496          * some offset and there is no guaranteed the result is a power
2497          * of 2, which will cause errors later.
2498          */
2499         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2500
2501         /*
2502          * In memory constrained environments, e.g. kdump kernel, the
2503          * DMA window can be larger than available memory, which will
2504          * cause errors later.
2505          */
2506         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2507
2508         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2509                         IOMMU_PAGE_SHIFT_4K,
2510                         window_size,
2511                         POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2512         if (rc) {
2513                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2514                                 rc);
2515                 return rc;
2516         }
2517
2518         iommu_init_table(tbl, pe->phb->hose->node);
2519
2520         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2521         if (rc) {
2522                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2523                                 rc);
2524                 iommu_tce_table_put(tbl);
2525                 return rc;
2526         }
2527
2528         if (!pnv_iommu_bypass_disabled)
2529                 pnv_pci_ioda2_set_bypass(pe, true);
2530
2531         /*
2532          * Setting table base here only for carrying iommu_group
2533          * further down to let iommu_add_device() do the job.
2534          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2535          */
2536         if (pe->flags & PNV_IODA_PE_DEV)
2537                 set_iommu_table_base(&pe->pdev->dev, tbl);
2538
2539         return 0;
2540 }
2541
2542 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2543 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2544                 int num)
2545 {
2546         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2547                         table_group);
2548         struct pnv_phb *phb = pe->phb;
2549         long ret;
2550
2551         pe_info(pe, "Removing DMA window #%d\n", num);
2552
2553         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2554                         (pe->pe_number << 1) + num,
2555                         0/* levels */, 0/* table address */,
2556                         0/* table size */, 0/* page size */);
2557         if (ret)
2558                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2559         else
2560                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2561
2562         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2563
2564         return ret;
2565 }
2566 #endif
2567
2568 #ifdef CONFIG_IOMMU_API
2569 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2570                 __u64 window_size, __u32 levels)
2571 {
2572         unsigned long bytes = 0;
2573         const unsigned window_shift = ilog2(window_size);
2574         unsigned entries_shift = window_shift - page_shift;
2575         unsigned table_shift = entries_shift + 3;
2576         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2577         unsigned long direct_table_size;
2578
2579         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2580                         !is_power_of_2(window_size))
2581                 return 0;
2582
2583         /* Calculate a direct table size from window_size and levels */
2584         entries_shift = (entries_shift + levels - 1) / levels;
2585         table_shift = entries_shift + 3;
2586         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2587         direct_table_size =  1UL << table_shift;
2588
2589         for ( ; levels; --levels) {
2590                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2591
2592                 tce_table_size /= direct_table_size;
2593                 tce_table_size <<= 3;
2594                 tce_table_size = max_t(unsigned long,
2595                                 tce_table_size, direct_table_size);
2596         }
2597
2598         return bytes + bytes; /* one for HW table, one for userspace copy */
2599 }
2600
2601 static long pnv_pci_ioda2_create_table_userspace(
2602                 struct iommu_table_group *table_group,
2603                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2604                 struct iommu_table **ptbl)
2605 {
2606         return pnv_pci_ioda2_create_table(table_group,
2607                         num, page_shift, window_size, levels, true, ptbl);
2608 }
2609
2610 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2611 {
2612         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2613                                                 table_group);
2614         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2615         struct iommu_table *tbl = pe->table_group.tables[0];
2616
2617         pnv_pci_ioda2_set_bypass(pe, false);
2618         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2619         if (pe->pbus)
2620                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2621         iommu_tce_table_put(tbl);
2622 }
2623
2624 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2625 {
2626         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2627                                                 table_group);
2628
2629         pnv_pci_ioda2_setup_default_config(pe);
2630         if (pe->pbus)
2631                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2632 }
2633
2634 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2635         .get_table_size = pnv_pci_ioda2_get_table_size,
2636         .create_table = pnv_pci_ioda2_create_table_userspace,
2637         .set_window = pnv_pci_ioda2_set_window,
2638         .unset_window = pnv_pci_ioda2_unset_window,
2639         .take_ownership = pnv_ioda2_take_ownership,
2640         .release_ownership = pnv_ioda2_release_ownership,
2641 };
2642
2643 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2644 {
2645         struct pci_controller *hose;
2646         struct pnv_phb *phb;
2647         struct pnv_ioda_pe **ptmppe = opaque;
2648         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2649         struct pci_dn *pdn = pci_get_pdn(pdev);
2650
2651         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2652                 return 0;
2653
2654         hose = pci_bus_to_host(pdev->bus);
2655         phb = hose->private_data;
2656         if (phb->type != PNV_PHB_NPU_NVLINK)
2657                 return 0;
2658
2659         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2660
2661         return 1;
2662 }
2663
2664 /*
2665  * This returns PE of associated NPU.
2666  * This assumes that NPU is in the same IOMMU group with GPU and there is
2667  * no other PEs.
2668  */
2669 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2670                 struct iommu_table_group *table_group)
2671 {
2672         struct pnv_ioda_pe *npe = NULL;
2673         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2674                         gpe_table_group_to_npe_cb);
2675
2676         BUG_ON(!ret || !npe);
2677
2678         return npe;
2679 }
2680
2681 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2682                 int num, struct iommu_table *tbl)
2683 {
2684         struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2685         int num2 = (num == 0) ? 1 : 0;
2686         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2687
2688         if (ret)
2689                 return ret;
2690
2691         if (table_group->tables[num2])
2692                 pnv_npu_unset_window(npe, num2);
2693
2694         ret = pnv_npu_set_window(npe, num, tbl);
2695         if (ret) {
2696                 pnv_pci_ioda2_unset_window(table_group, num);
2697                 if (table_group->tables[num2])
2698                         pnv_npu_set_window(npe, num2,
2699                                         table_group->tables[num2]);
2700         }
2701
2702         return ret;
2703 }
2704
2705 static long pnv_pci_ioda2_npu_unset_window(
2706                 struct iommu_table_group *table_group,
2707                 int num)
2708 {
2709         struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2710         int num2 = (num == 0) ? 1 : 0;
2711         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2712
2713         if (ret)
2714                 return ret;
2715
2716         if (!npe->table_group.tables[num])
2717                 return 0;
2718
2719         ret = pnv_npu_unset_window(npe, num);
2720         if (ret)
2721                 return ret;
2722
2723         if (table_group->tables[num2])
2724                 ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]);
2725
2726         return ret;
2727 }
2728
2729 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2730 {
2731         /*
2732          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2733          * the iommu_table if 32bit DMA is enabled.
2734          */
2735         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2736         pnv_ioda2_take_ownership(table_group);
2737 }
2738
2739 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2740         .get_table_size = pnv_pci_ioda2_get_table_size,
2741         .create_table = pnv_pci_ioda2_create_table_userspace,
2742         .set_window = pnv_pci_ioda2_npu_set_window,
2743         .unset_window = pnv_pci_ioda2_npu_unset_window,
2744         .take_ownership = pnv_ioda2_npu_take_ownership,
2745         .release_ownership = pnv_ioda2_release_ownership,
2746 };
2747
2748 static void pnv_pci_ioda_setup_iommu_api(void)
2749 {
2750         struct pci_controller *hose, *tmp;
2751         struct pnv_phb *phb;
2752         struct pnv_ioda_pe *pe, *gpe;
2753
2754         /*
2755          * Now we have all PHBs discovered, time to add NPU devices to
2756          * the corresponding IOMMU groups.
2757          */
2758         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2759                 phb = hose->private_data;
2760
2761                 if (phb->type != PNV_PHB_NPU_NVLINK)
2762                         continue;
2763
2764                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2765                         gpe = pnv_pci_npu_setup_iommu(pe);
2766                         if (gpe)
2767                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2768                 }
2769         }
2770 }
2771 #else /* !CONFIG_IOMMU_API */
2772 static void pnv_pci_ioda_setup_iommu_api(void) { };
2773 #endif
2774
2775 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2776 {
2777         struct pci_controller *hose = phb->hose;
2778         struct device_node *dn = hose->dn;
2779         unsigned long mask = 0;
2780         int i, rc, count;
2781         u32 val;
2782
2783         count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2784         if (count <= 0) {
2785                 mask = SZ_4K | SZ_64K;
2786                 /* Add 16M for POWER8 by default */
2787                 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2788                                 !cpu_has_feature(CPU_FTR_ARCH_300))
2789                         mask |= SZ_16M | SZ_256M;
2790                 return mask;
2791         }
2792
2793         for (i = 0; i < count; i++) {
2794                 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2795                                                 i, &val);
2796                 if (rc == 0)
2797                         mask |= 1ULL << val;
2798         }
2799
2800         return mask;
2801 }
2802
2803 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2804                                        struct pnv_ioda_pe *pe)
2805 {
2806         int64_t rc;
2807
2808         if (!pnv_pci_ioda_pe_dma_weight(pe))
2809                 return;
2810
2811         /* TVE #1 is selected by PCI address bit 59 */
2812         pe->tce_bypass_base = 1ull << 59;
2813
2814         iommu_register_group(&pe->table_group, phb->hose->global_number,
2815                         pe->pe_number);
2816
2817         /* The PE will reserve all possible 32-bits space */
2818         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2819                 phb->ioda.m32_pci_base);
2820
2821         /* Setup linux iommu table */
2822         pe->table_group.tce32_start = 0;
2823         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2824         pe->table_group.max_dynamic_windows_supported =
2825                         IOMMU_TABLE_GROUP_MAX_TABLES;
2826         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2827         pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2828 #ifdef CONFIG_IOMMU_API
2829         pe->table_group.ops = &pnv_pci_ioda2_ops;
2830 #endif
2831
2832         rc = pnv_pci_ioda2_setup_default_config(pe);
2833         if (rc)
2834                 return;
2835
2836         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2837                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2838 }
2839
2840 #ifdef CONFIG_PCI_MSI
2841 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2842 {
2843         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2844                                            ioda.irq_chip);
2845
2846         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2847 }
2848
2849 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2850 {
2851         int64_t rc;
2852         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2853         struct irq_chip *chip = irq_data_get_irq_chip(d);
2854
2855         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2856         WARN_ON_ONCE(rc);
2857
2858         icp_native_eoi(d);
2859 }
2860
2861
2862 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2863 {
2864         struct irq_data *idata;
2865         struct irq_chip *ichip;
2866
2867         /* The MSI EOI OPAL call is only needed on PHB3 */
2868         if (phb->model != PNV_PHB_MODEL_PHB3)
2869                 return;
2870
2871         if (!phb->ioda.irq_chip_init) {
2872                 /*
2873                  * First time we setup an MSI IRQ, we need to setup the
2874                  * corresponding IRQ chip to route correctly.
2875                  */
2876                 idata = irq_get_irq_data(virq);
2877                 ichip = irq_data_get_irq_chip(idata);
2878                 phb->ioda.irq_chip_init = 1;
2879                 phb->ioda.irq_chip = *ichip;
2880                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2881         }
2882         irq_set_chip(virq, &phb->ioda.irq_chip);
2883 }
2884
2885 /*
2886  * Returns true iff chip is something that we could call
2887  * pnv_opal_pci_msi_eoi for.
2888  */
2889 bool is_pnv_opal_msi(struct irq_chip *chip)
2890 {
2891         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2892 }
2893 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2894
2895 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2896                                   unsigned int hwirq, unsigned int virq,
2897                                   unsigned int is_64, struct msi_msg *msg)
2898 {
2899         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2900         unsigned int xive_num = hwirq - phb->msi_base;
2901         __be32 data;
2902         int rc;
2903
2904         /* No PE assigned ? bail out ... no MSI for you ! */
2905         if (pe == NULL)
2906                 return -ENXIO;
2907
2908         /* Check if we have an MVE */
2909         if (pe->mve_number < 0)
2910                 return -ENXIO;
2911
2912         /* Force 32-bit MSI on some broken devices */
2913         if (dev->no_64bit_msi)
2914                 is_64 = 0;
2915
2916         /* Assign XIVE to PE */
2917         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2918         if (rc) {
2919                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2920                         pci_name(dev), rc, xive_num);
2921                 return -EIO;
2922         }
2923
2924         if (is_64) {
2925                 __be64 addr64;
2926
2927                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2928                                      &addr64, &data);
2929                 if (rc) {
2930                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2931                                 pci_name(dev), rc);
2932                         return -EIO;
2933                 }
2934                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2935                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2936         } else {
2937                 __be32 addr32;
2938
2939                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2940                                      &addr32, &data);
2941                 if (rc) {
2942                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2943                                 pci_name(dev), rc);
2944                         return -EIO;
2945                 }
2946                 msg->address_hi = 0;
2947                 msg->address_lo = be32_to_cpu(addr32);
2948         }
2949         msg->data = be32_to_cpu(data);
2950
2951         pnv_set_msi_irq_chip(phb, virq);
2952
2953         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2954                  " address=%x_%08x data=%x PE# %x\n",
2955                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2956                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2957
2958         return 0;
2959 }
2960
2961 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2962 {
2963         unsigned int count;
2964         const __be32 *prop = of_get_property(phb->hose->dn,
2965                                              "ibm,opal-msi-ranges", NULL);
2966         if (!prop) {
2967                 /* BML Fallback */
2968                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2969         }
2970         if (!prop)
2971                 return;
2972
2973         phb->msi_base = be32_to_cpup(prop);
2974         count = be32_to_cpup(prop + 1);
2975         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2976                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2977                        phb->hose->global_number);
2978                 return;
2979         }
2980
2981         phb->msi_setup = pnv_pci_ioda_msi_setup;
2982         phb->msi32_support = 1;
2983         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2984                 count, phb->msi_base);
2985 }
2986 #else
2987 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2988 #endif /* CONFIG_PCI_MSI */
2989
2990 #ifdef CONFIG_PCI_IOV
2991 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2992 {
2993         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2994         struct pnv_phb *phb = hose->private_data;
2995         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2996         struct resource *res;
2997         int i;
2998         resource_size_t size, total_vf_bar_sz;
2999         struct pci_dn *pdn;
3000         int mul, total_vfs;
3001
3002         if (!pdev->is_physfn || pci_dev_is_added(pdev))
3003                 return;
3004
3005         pdn = pci_get_pdn(pdev);
3006         pdn->vfs_expanded = 0;
3007         pdn->m64_single_mode = false;
3008
3009         total_vfs = pci_sriov_get_totalvfs(pdev);
3010         mul = phb->ioda.total_pe_num;
3011         total_vf_bar_sz = 0;
3012
3013         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3014                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3015                 if (!res->flags || res->parent)
3016                         continue;
3017                 if (!pnv_pci_is_m64_flags(res->flags)) {
3018                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
3019                                         " non M64 VF BAR%d: %pR. \n",
3020                                  i, res);
3021                         goto truncate_iov;
3022                 }
3023
3024                 total_vf_bar_sz += pci_iov_resource_size(pdev,
3025                                 i + PCI_IOV_RESOURCES);
3026
3027                 /*
3028                  * If bigger than quarter of M64 segment size, just round up
3029                  * power of two.
3030                  *
3031                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3032                  * with other devices, IOV BAR size is expanded to be
3033                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
3034                  * segment size , the expanded size would equal to half of the
3035                  * whole M64 space size, which will exhaust the M64 Space and
3036                  * limit the system flexibility.  This is a design decision to
3037                  * set the boundary to quarter of the M64 segment size.
3038                  */
3039                 if (total_vf_bar_sz > gate) {
3040                         mul = roundup_pow_of_two(total_vfs);
3041                         dev_info(&pdev->dev,
3042                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3043                                 total_vf_bar_sz, gate, mul);
3044                         pdn->m64_single_mode = true;
3045                         break;
3046                 }
3047         }
3048
3049         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3050                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3051                 if (!res->flags || res->parent)
3052                         continue;
3053
3054                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3055                 /*
3056                  * On PHB3, the minimum size alignment of M64 BAR in single
3057                  * mode is 32MB.
3058                  */
3059                 if (pdn->m64_single_mode && (size < SZ_32M))
3060                         goto truncate_iov;
3061                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3062                 res->end = res->start + size * mul - 1;
3063                 dev_dbg(&pdev->dev, "                       %pR\n", res);
3064                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3065                          i, res, mul);
3066         }
3067         pdn->vfs_expanded = mul;
3068
3069         return;
3070
3071 truncate_iov:
3072         /* To save MMIO space, IOV BAR is truncated. */
3073         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3074                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3075                 res->flags = 0;
3076                 res->end = res->start - 1;
3077         }
3078 }
3079 #endif /* CONFIG_PCI_IOV */
3080
3081 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3082                                   struct resource *res)
3083 {
3084         struct pnv_phb *phb = pe->phb;
3085         struct pci_bus_region region;
3086         int index;
3087         int64_t rc;
3088
3089         if (!res || !res->flags || res->start > res->end)
3090                 return;
3091
3092         if (res->flags & IORESOURCE_IO) {
3093                 region.start = res->start - phb->ioda.io_pci_base;
3094                 region.end   = res->end - phb->ioda.io_pci_base;
3095                 index = region.start / phb->ioda.io_segsize;
3096
3097                 while (index < phb->ioda.total_pe_num &&
3098                        region.start <= region.end) {
3099                         phb->ioda.io_segmap[index] = pe->pe_number;
3100                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3101                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3102                         if (rc != OPAL_SUCCESS) {
3103                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3104                                        __func__, rc, index, pe->pe_number);
3105                                 break;
3106                         }
3107
3108                         region.start += phb->ioda.io_segsize;
3109                         index++;
3110                 }
3111         } else if ((res->flags & IORESOURCE_MEM) &&
3112                    !pnv_pci_is_m64(phb, res)) {
3113                 region.start = res->start -