x86/io: Define readq()/writeq() to use 64-bit type
[muen/linux.git] / arch / x86 / include / asm / io.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_IO_H
3 #define _ASM_X86_IO_H
4
5 /*
6  * This file contains the definitions for the x86 IO instructions
7  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
8  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
9  * versions of the single-IO instructions (inb_p/inw_p/..).
10  *
11  * This file is not meant to be obfuscating: it's just complicated
12  * to (a) handle it all in a way that makes gcc able to optimize it
13  * as well as possible and (b) trying to avoid writing the same thing
14  * over and over again with slight variations and possibly making a
15  * mistake somewhere.
16  */
17
18 /*
19  * Thanks to James van Artsdalen for a better timing-fix than
20  * the two short jumps: using outb's to a nonexistent port seems
21  * to guarantee better timings even on fast machines.
22  *
23  * On the other hand, I'd like to be sure of a non-existent port:
24  * I feel a bit unsafe about using 0x80 (should be safe, though)
25  *
26  *              Linus
27  */
28
29  /*
30   *  Bit simplified and optimized by Jan Hubicka
31   *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
32   *
33   *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
34   *  isa_read[wl] and isa_write[wl] fixed
35   *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
36   */
37
38 #define ARCH_HAS_IOREMAP_WC
39 #define ARCH_HAS_IOREMAP_WT
40
41 #include <linux/string.h>
42 #include <linux/compiler.h>
43 #include <asm/page.h>
44 #include <asm/early_ioremap.h>
45 #include <asm/pgtable_types.h>
46
47 #define build_mmio_read(name, size, type, reg, barrier) \
48 static inline type name(const volatile void __iomem *addr) \
49 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
50 :"m" (*(volatile type __force *)addr) barrier); return ret; }
51
52 #define build_mmio_write(name, size, type, reg, barrier) \
53 static inline void name(type val, volatile void __iomem *addr) \
54 { asm volatile("mov" size " %0,%1": :reg (val), \
55 "m" (*(volatile type __force *)addr) barrier); }
56
57 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
58 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
59 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
60
61 build_mmio_read(__readb, "b", unsigned char, "=q", )
62 build_mmio_read(__readw, "w", unsigned short, "=r", )
63 build_mmio_read(__readl, "l", unsigned int, "=r", )
64
65 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
66 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
67 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
68
69 build_mmio_write(__writeb, "b", unsigned char, "q", )
70 build_mmio_write(__writew, "w", unsigned short, "r", )
71 build_mmio_write(__writel, "l", unsigned int, "r", )
72
73 #define readb readb
74 #define readw readw
75 #define readl readl
76 #define readb_relaxed(a) __readb(a)
77 #define readw_relaxed(a) __readw(a)
78 #define readl_relaxed(a) __readl(a)
79 #define __raw_readb __readb
80 #define __raw_readw __readw
81 #define __raw_readl __readl
82
83 #define writeb writeb
84 #define writew writew
85 #define writel writel
86 #define writeb_relaxed(v, a) __writeb(v, a)
87 #define writew_relaxed(v, a) __writew(v, a)
88 #define writel_relaxed(v, a) __writel(v, a)
89 #define __raw_writeb __writeb
90 #define __raw_writew __writew
91 #define __raw_writel __writel
92
93 #define mmiowb() barrier()
94
95 #ifdef CONFIG_X86_64
96
97 build_mmio_read(readq, "q", u64, "=r", :"memory")
98 build_mmio_read(__readq, "q", u64, "=r", )
99 build_mmio_write(writeq, "q", u64, "r", :"memory")
100 build_mmio_write(__writeq, "q", u64, "r", )
101
102 #define readq_relaxed(a)        __readq(a)
103 #define writeq_relaxed(v, a)    __writeq(v, a)
104
105 #define __raw_readq             __readq
106 #define __raw_writeq            __writeq
107
108 /* Let people know that we have them */
109 #define readq                   readq
110 #define writeq                  writeq
111
112 #endif
113
114 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
115 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
116 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
117
118 /**
119  *      virt_to_phys    -       map virtual addresses to physical
120  *      @address: address to remap
121  *
122  *      The returned physical address is the physical (CPU) mapping for
123  *      the memory address given. It is only valid to use this function on
124  *      addresses directly mapped or allocated via kmalloc.
125  *
126  *      This function does not give bus mappings for DMA transfers. In
127  *      almost all conceivable cases a device driver should not be using
128  *      this function
129  */
130
131 static inline phys_addr_t virt_to_phys(volatile void *address)
132 {
133         return __pa(address);
134 }
135 #define virt_to_phys virt_to_phys
136
137 /**
138  *      phys_to_virt    -       map physical address to virtual
139  *      @address: address to remap
140  *
141  *      The returned virtual address is a current CPU mapping for
142  *      the memory address given. It is only valid to use this function on
143  *      addresses that have a kernel mapping
144  *
145  *      This function does not handle bus mappings for DMA transfers. In
146  *      almost all conceivable cases a device driver should not be using
147  *      this function
148  */
149
150 static inline void *phys_to_virt(phys_addr_t address)
151 {
152         return __va(address);
153 }
154 #define phys_to_virt phys_to_virt
155
156 /*
157  * Change "struct page" to physical address.
158  */
159 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
160
161 /*
162  * ISA I/O bus memory addresses are 1:1 with the physical address.
163  * However, we truncate the address to unsigned int to avoid undesirable
164  * promitions in legacy drivers.
165  */
166 static inline unsigned int isa_virt_to_bus(volatile void *address)
167 {
168         return (unsigned int)virt_to_phys(address);
169 }
170 #define isa_page_to_bus(page)   ((unsigned int)page_to_phys(page))
171 #define isa_bus_to_virt         phys_to_virt
172
173 /*
174  * However PCI ones are not necessarily 1:1 and therefore these interfaces
175  * are forbidden in portable PCI drivers.
176  *
177  * Allow them on x86 for legacy drivers, though.
178  */
179 #define virt_to_bus virt_to_phys
180 #define bus_to_virt phys_to_virt
181
182 /*
183  * The default ioremap() behavior is non-cached; if you need something
184  * else, you probably want one of the following.
185  */
186 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
187 #define ioremap_nocache ioremap_nocache
188 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
189 #define ioremap_uc ioremap_uc
190
191 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
192 #define ioremap_cache ioremap_cache
193 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
194 #define ioremap_prot ioremap_prot
195
196 /**
197  * ioremap     -   map bus memory into CPU space
198  * @offset:    bus address of the memory
199  * @size:      size of the resource to map
200  *
201  * ioremap performs a platform specific sequence of operations to
202  * make bus memory CPU accessible via the readb/readw/readl/writeb/
203  * writew/writel functions and the other mmio helpers. The returned
204  * address is not guaranteed to be usable directly as a virtual
205  * address.
206  *
207  * If the area you are trying to map is a PCI BAR you should have a
208  * look at pci_iomap().
209  */
210 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
211 {
212         return ioremap_nocache(offset, size);
213 }
214 #define ioremap ioremap
215
216 extern void iounmap(volatile void __iomem *addr);
217 #define iounmap iounmap
218
219 extern void set_iounmap_nonlazy(void);
220
221 #ifdef __KERNEL__
222
223 #include <asm-generic/iomap.h>
224
225 /*
226  * ISA space is 'always mapped' on a typical x86 system, no need to
227  * explicitly ioremap() it. The fact that the ISA IO space is mapped
228  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
229  * are physical addresses. The following constant pointer can be
230  * used as the IO-area pointer (it can be iounmapped as well, so the
231  * analogy with PCI is quite large):
232  */
233 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
234
235 #endif /* __KERNEL__ */
236
237 extern void native_io_delay(void);
238
239 extern int io_delay_type;
240 extern void io_delay_init(void);
241
242 #if defined(CONFIG_PARAVIRT)
243 #include <asm/paravirt.h>
244 #else
245
246 static inline void slow_down_io(void)
247 {
248         native_io_delay();
249 #ifdef REALLY_SLOW_IO
250         native_io_delay();
251         native_io_delay();
252         native_io_delay();
253 #endif
254 }
255
256 #endif
257
258 #ifdef CONFIG_AMD_MEM_ENCRYPT
259 #include <linux/jump_label.h>
260
261 extern struct static_key_false sev_enable_key;
262 static inline bool sev_key_active(void)
263 {
264         return static_branch_unlikely(&sev_enable_key);
265 }
266
267 #else /* !CONFIG_AMD_MEM_ENCRYPT */
268
269 static inline bool sev_key_active(void) { return false; }
270
271 #endif /* CONFIG_AMD_MEM_ENCRYPT */
272
273 #define BUILDIO(bwl, bw, type)                                          \
274 static inline void out##bwl(unsigned type value, int port)              \
275 {                                                                       \
276         asm volatile("out" #bwl " %" #bw "0, %w1"                       \
277                      : : "a"(value), "Nd"(port));                       \
278 }                                                                       \
279                                                                         \
280 static inline unsigned type in##bwl(int port)                           \
281 {                                                                       \
282         unsigned type value;                                            \
283         asm volatile("in" #bwl " %w1, %" #bw "0"                        \
284                      : "=a"(value) : "Nd"(port));                       \
285         return value;                                                   \
286 }                                                                       \
287                                                                         \
288 static inline void out##bwl##_p(unsigned type value, int port)          \
289 {                                                                       \
290         out##bwl(value, port);                                          \
291         slow_down_io();                                                 \
292 }                                                                       \
293                                                                         \
294 static inline unsigned type in##bwl##_p(int port)                       \
295 {                                                                       \
296         unsigned type value = in##bwl(port);                            \
297         slow_down_io();                                                 \
298         return value;                                                   \
299 }                                                                       \
300                                                                         \
301 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
302 {                                                                       \
303         if (sev_key_active()) {                                         \
304                 unsigned type *value = (unsigned type *)addr;           \
305                 while (count) {                                         \
306                         out##bwl(*value, port);                         \
307                         value++;                                        \
308                         count--;                                        \
309                 }                                                       \
310         } else {                                                        \
311                 asm volatile("rep; outs" #bwl                           \
312                              : "+S"(addr), "+c"(count)                  \
313                              : "d"(port) : "memory");                   \
314         }                                                               \
315 }                                                                       \
316                                                                         \
317 static inline void ins##bwl(int port, void *addr, unsigned long count)  \
318 {                                                                       \
319         if (sev_key_active()) {                                         \
320                 unsigned type *value = (unsigned type *)addr;           \
321                 while (count) {                                         \
322                         *value = in##bwl(port);                         \
323                         value++;                                        \
324                         count--;                                        \
325                 }                                                       \
326         } else {                                                        \
327                 asm volatile("rep; ins" #bwl                            \
328                              : "+D"(addr), "+c"(count)                  \
329                              : "d"(port) : "memory");                   \
330         }                                                               \
331 }
332
333 BUILDIO(b, b, char)
334 BUILDIO(w, w, short)
335 BUILDIO(l, , int)
336
337 #define inb inb
338 #define inw inw
339 #define inl inl
340 #define inb_p inb_p
341 #define inw_p inw_p
342 #define inl_p inl_p
343 #define insb insb
344 #define insw insw
345 #define insl insl
346
347 #define outb outb
348 #define outw outw
349 #define outl outl
350 #define outb_p outb_p
351 #define outw_p outw_p
352 #define outl_p outl_p
353 #define outsb outsb
354 #define outsw outsw
355 #define outsl outsl
356
357 extern void *xlate_dev_mem_ptr(phys_addr_t phys);
358 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
359
360 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
361 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
362
363 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
364                                 enum page_cache_mode pcm);
365 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
366 #define ioremap_wc ioremap_wc
367 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
368 #define ioremap_wt ioremap_wt
369
370 extern bool is_early_ioremap_ptep(pte_t *ptep);
371
372 #ifdef CONFIG_XEN
373 #include <xen/xen.h>
374 struct bio_vec;
375
376 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
377                                       const struct bio_vec *vec2);
378
379 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
380         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
381          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
382 #endif  /* CONFIG_XEN */
383
384 #define IO_SPACE_LIMIT 0xffff
385
386 #include <asm-generic/io.h>
387 #undef PCI_IOBASE
388
389 #ifdef CONFIG_MTRR
390 extern int __must_check arch_phys_wc_index(int handle);
391 #define arch_phys_wc_index arch_phys_wc_index
392
393 extern int __must_check arch_phys_wc_add(unsigned long base,
394                                          unsigned long size);
395 extern void arch_phys_wc_del(int handle);
396 #define arch_phys_wc_add arch_phys_wc_add
397 #endif
398
399 #ifdef CONFIG_X86_PAT
400 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
401 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
402 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
403 #endif
404
405 extern bool arch_memremap_can_ram_remap(resource_size_t offset,
406                                         unsigned long size,
407                                         unsigned long flags);
408 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
409
410 extern bool phys_mem_access_encrypted(unsigned long phys_addr,
411                                       unsigned long size);
412
413 #endif /* _ASM_X86_IO_H */