Merge tag 'acpi-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[muen/linux.git] / drivers / acpi / cppc_acpi.c
1 /*
2  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
3  *
4  * (C) Copyright 2014, 2015 Linaro Ltd.
5  * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; version 2
10  * of the License.
11  *
12  * CPPC describes a few methods for controlling CPU performance using
13  * information from a per CPU table called CPC. This table is described in
14  * the ACPI v5.0+ specification. The table consists of a list of
15  * registers which may be memory mapped or hardware registers and also may
16  * include some static integer values.
17  *
18  * CPU performance is on an abstract continuous scale as against a discretized
19  * P-state scale which is tied to CPU frequency only. In brief, the basic
20  * operation involves:
21  *
22  * - OS makes a CPU performance request. (Can provide min and max bounds)
23  *
24  * - Platform (such as BMC) is free to optimize request within requested bounds
25  *   depending on power/thermal budgets etc.
26  *
27  * - Platform conveys its decision back to OS
28  *
29  * The communication between OS and platform occurs through another medium
30  * called (PCC) Platform Communication Channel. This is a generic mailbox like
31  * mechanism which includes doorbell semantics to indicate register updates.
32  * See drivers/mailbox/pcc.c for details on PCC.
33  *
34  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
35  * above specifications.
36  */
37
38 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
39
40 #include <linux/cpufreq.h>
41 #include <linux/delay.h>
42 #include <linux/iopoll.h>
43 #include <linux/ktime.h>
44 #include <linux/rwsem.h>
45 #include <linux/wait.h>
46
47 #include <acpi/cppc_acpi.h>
48
49 struct cppc_pcc_data {
50         struct mbox_chan *pcc_channel;
51         void __iomem *pcc_comm_addr;
52         bool pcc_channel_acquired;
53         unsigned int deadline_us;
54         unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
55
56         bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
57         bool platform_owns_pcc;         /* Ownership of PCC subspace */
58         unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
59
60         /*
61          * Lock to provide controlled access to the PCC channel.
62          *
63          * For performance critical usecases(currently cppc_set_perf)
64          *      We need to take read_lock and check if channel belongs to OSPM
65          * before reading or writing to PCC subspace
66          *      We need to take write_lock before transferring the channel
67          * ownership to the platform via a Doorbell
68          *      This allows us to batch a number of CPPC requests if they happen
69          * to originate in about the same time
70          *
71          * For non-performance critical usecases(init)
72          *      Take write_lock for all purposes which gives exclusive access
73          */
74         struct rw_semaphore pcc_lock;
75
76         /* Wait queue for CPUs whose requests were batched */
77         wait_queue_head_t pcc_write_wait_q;
78         ktime_t last_cmd_cmpl_time;
79         ktime_t last_mpar_reset;
80         int mpar_count;
81         int refcount;
82 };
83
84 /* Array  to represent the PCC channel per subspace id */
85 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
86 /* The cpu_pcc_subspace_idx containsper CPU subspace id */
87 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
88
89 /*
90  * The cpc_desc structure contains the ACPI register details
91  * as described in the per CPU _CPC tables. The details
92  * include the type of register (e.g. PCC, System IO, FFH etc.)
93  * and destination addresses which lets us READ/WRITE CPU performance
94  * information using the appropriate I/O methods.
95  */
96 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
97
98 /* pcc mapped address + header size + offset within PCC subspace */
99 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
100                                                 0x8 + (offs))
101
102 /* Check if a CPC register is in PCC */
103 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
104                                 (cpc)->cpc_entry.reg.space_id ==        \
105                                 ACPI_ADR_SPACE_PLATFORM_COMM)
106
107 /* Evalutes to True if reg is a NULL register descriptor */
108 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
109                                 (reg)->address == 0 &&                  \
110                                 (reg)->bit_width == 0 &&                \
111                                 (reg)->bit_offset == 0 &&               \
112                                 (reg)->access_width == 0)
113
114 /* Evalutes to True if an optional cpc field is supported */
115 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
116                                 !!(cpc)->cpc_entry.int_value :          \
117                                 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
118 /*
119  * Arbitrary Retries in case the remote processor is slow to respond
120  * to PCC commands. Keeping it high enough to cover emulators where
121  * the processors run painfully slow.
122  */
123 #define NUM_RETRIES 500ULL
124
125 struct cppc_attr {
126         struct attribute attr;
127         ssize_t (*show)(struct kobject *kobj,
128                         struct attribute *attr, char *buf);
129         ssize_t (*store)(struct kobject *kobj,
130                         struct attribute *attr, const char *c, ssize_t count);
131 };
132
133 #define define_one_cppc_ro(_name)               \
134 static struct cppc_attr _name =                 \
135 __ATTR(_name, 0444, show_##_name, NULL)
136
137 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
138
139 #define show_cppc_data(access_fn, struct_name, member_name)             \
140         static ssize_t show_##member_name(struct kobject *kobj,         \
141                                         struct attribute *attr, char *buf) \
142         {                                                               \
143                 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);           \
144                 struct struct_name st_name = {0};                       \
145                 int ret;                                                \
146                                                                         \
147                 ret = access_fn(cpc_ptr->cpu_id, &st_name);             \
148                 if (ret)                                                \
149                         return ret;                                     \
150                                                                         \
151                 return scnprintf(buf, PAGE_SIZE, "%llu\n",              \
152                                 (u64)st_name.member_name);              \
153         }                                                               \
154         define_one_cppc_ro(member_name)
155
156 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
157 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
158 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
159 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
160 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
161 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
162
163 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
164 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
165
166 static ssize_t show_feedback_ctrs(struct kobject *kobj,
167                 struct attribute *attr, char *buf)
168 {
169         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
170         struct cppc_perf_fb_ctrs fb_ctrs = {0};
171         int ret;
172
173         ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
174         if (ret)
175                 return ret;
176
177         return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
178                         fb_ctrs.reference, fb_ctrs.delivered);
179 }
180 define_one_cppc_ro(feedback_ctrs);
181
182 static struct attribute *cppc_attrs[] = {
183         &feedback_ctrs.attr,
184         &reference_perf.attr,
185         &wraparound_time.attr,
186         &highest_perf.attr,
187         &lowest_perf.attr,
188         &lowest_nonlinear_perf.attr,
189         &nominal_perf.attr,
190         &nominal_freq.attr,
191         &lowest_freq.attr,
192         NULL
193 };
194
195 static struct kobj_type cppc_ktype = {
196         .sysfs_ops = &kobj_sysfs_ops,
197         .default_attrs = cppc_attrs,
198 };
199
200 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
201 {
202         int ret, status;
203         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
204         struct acpi_pcct_shared_memory __iomem *generic_comm_base =
205                 pcc_ss_data->pcc_comm_addr;
206
207         if (!pcc_ss_data->platform_owns_pcc)
208                 return 0;
209
210         /*
211          * Poll PCC status register every 3us(delay_us) for maximum of
212          * deadline_us(timeout_us) until PCC command complete bit is set(cond)
213          */
214         ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
215                                         status & PCC_CMD_COMPLETE_MASK, 3,
216                                         pcc_ss_data->deadline_us);
217
218         if (likely(!ret)) {
219                 pcc_ss_data->platform_owns_pcc = false;
220                 if (chk_err_bit && (status & PCC_ERROR_MASK))
221                         ret = -EIO;
222         }
223
224         if (unlikely(ret))
225                 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
226                        pcc_ss_id, ret);
227
228         return ret;
229 }
230
231 /*
232  * This function transfers the ownership of the PCC to the platform
233  * So it must be called while holding write_lock(pcc_lock)
234  */
235 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
236 {
237         int ret = -EIO, i;
238         struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
239         struct acpi_pcct_shared_memory *generic_comm_base =
240                 (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr;
241         unsigned int time_delta;
242
243         /*
244          * For CMD_WRITE we know for a fact the caller should have checked
245          * the channel before writing to PCC space
246          */
247         if (cmd == CMD_READ) {
248                 /*
249                  * If there are pending cpc_writes, then we stole the channel
250                  * before write completion, so first send a WRITE command to
251                  * platform
252                  */
253                 if (pcc_ss_data->pending_pcc_write_cmd)
254                         send_pcc_cmd(pcc_ss_id, CMD_WRITE);
255
256                 ret = check_pcc_chan(pcc_ss_id, false);
257                 if (ret)
258                         goto end;
259         } else /* CMD_WRITE */
260                 pcc_ss_data->pending_pcc_write_cmd = FALSE;
261
262         /*
263          * Handle the Minimum Request Turnaround Time(MRTT)
264          * "The minimum amount of time that OSPM must wait after the completion
265          * of a command before issuing the next command, in microseconds"
266          */
267         if (pcc_ss_data->pcc_mrtt) {
268                 time_delta = ktime_us_delta(ktime_get(),
269                                             pcc_ss_data->last_cmd_cmpl_time);
270                 if (pcc_ss_data->pcc_mrtt > time_delta)
271                         udelay(pcc_ss_data->pcc_mrtt - time_delta);
272         }
273
274         /*
275          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
276          * "The maximum number of periodic requests that the subspace channel can
277          * support, reported in commands per minute. 0 indicates no limitation."
278          *
279          * This parameter should be ideally zero or large enough so that it can
280          * handle maximum number of requests that all the cores in the system can
281          * collectively generate. If it is not, we will follow the spec and just
282          * not send the request to the platform after hitting the MPAR limit in
283          * any 60s window
284          */
285         if (pcc_ss_data->pcc_mpar) {
286                 if (pcc_ss_data->mpar_count == 0) {
287                         time_delta = ktime_ms_delta(ktime_get(),
288                                                     pcc_ss_data->last_mpar_reset);
289                         if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
290                                 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
291                                          pcc_ss_id);
292                                 ret = -EIO;
293                                 goto end;
294                         }
295                         pcc_ss_data->last_mpar_reset = ktime_get();
296                         pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
297                 }
298                 pcc_ss_data->mpar_count--;
299         }
300
301         /* Write to the shared comm region. */
302         writew_relaxed(cmd, &generic_comm_base->command);
303
304         /* Flip CMD COMPLETE bit */
305         writew_relaxed(0, &generic_comm_base->status);
306
307         pcc_ss_data->platform_owns_pcc = true;
308
309         /* Ring doorbell */
310         ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
311         if (ret < 0) {
312                 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
313                        pcc_ss_id, cmd, ret);
314                 goto end;
315         }
316
317         /* wait for completion and check for PCC errro bit */
318         ret = check_pcc_chan(pcc_ss_id, true);
319
320         if (pcc_ss_data->pcc_mrtt)
321                 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
322
323         if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
324                 mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
325         else
326                 mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
327
328 end:
329         if (cmd == CMD_WRITE) {
330                 if (unlikely(ret)) {
331                         for_each_possible_cpu(i) {
332                                 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
333                                 if (!desc)
334                                         continue;
335
336                                 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
337                                         desc->write_cmd_status = ret;
338                         }
339                 }
340                 pcc_ss_data->pcc_write_cnt++;
341                 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
342         }
343
344         return ret;
345 }
346
347 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
348 {
349         if (ret < 0)
350                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
351                                 *(u16 *)msg, ret);
352         else
353                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
354                                 *(u16 *)msg, ret);
355 }
356
357 struct mbox_client cppc_mbox_cl = {
358         .tx_done = cppc_chan_tx_done,
359         .knows_txdone = true,
360 };
361
362 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
363 {
364         int result = -EFAULT;
365         acpi_status status = AE_OK;
366         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
367         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
368         struct acpi_buffer state = {0, NULL};
369         union acpi_object  *psd = NULL;
370         struct acpi_psd_package *pdomain;
371
372         status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer,
373                         ACPI_TYPE_PACKAGE);
374         if (ACPI_FAILURE(status))
375                 return -ENODEV;
376
377         psd = buffer.pointer;
378         if (!psd || psd->package.count != 1) {
379                 pr_debug("Invalid _PSD data\n");
380                 goto end;
381         }
382
383         pdomain = &(cpc_ptr->domain_info);
384
385         state.length = sizeof(struct acpi_psd_package);
386         state.pointer = pdomain;
387
388         status = acpi_extract_package(&(psd->package.elements[0]),
389                 &format, &state);
390         if (ACPI_FAILURE(status)) {
391                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
392                 goto end;
393         }
394
395         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
396                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
397                 goto end;
398         }
399
400         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
401                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
402                 goto end;
403         }
404
405         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
406             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
407             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
408                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
409                 goto end;
410         }
411
412         result = 0;
413 end:
414         kfree(buffer.pointer);
415         return result;
416 }
417
418 /**
419  * acpi_get_psd_map - Map the CPUs in a common freq domain.
420  * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
421  *
422  *      Return: 0 for success or negative value for err.
423  */
424 int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
425 {
426         int count_target;
427         int retval = 0;
428         unsigned int i, j;
429         cpumask_var_t covered_cpus;
430         struct cppc_cpudata *pr, *match_pr;
431         struct acpi_psd_package *pdomain;
432         struct acpi_psd_package *match_pdomain;
433         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
434
435         if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
436                 return -ENOMEM;
437
438         /*
439          * Now that we have _PSD data from all CPUs, lets setup P-state
440          * domain info.
441          */
442         for_each_possible_cpu(i) {
443                 pr = all_cpu_data[i];
444                 if (!pr)
445                         continue;
446
447                 if (cpumask_test_cpu(i, covered_cpus))
448                         continue;
449
450                 cpc_ptr = per_cpu(cpc_desc_ptr, i);
451                 if (!cpc_ptr) {
452                         retval = -EFAULT;
453                         goto err_ret;
454                 }
455
456                 pdomain = &(cpc_ptr->domain_info);
457                 cpumask_set_cpu(i, pr->shared_cpu_map);
458                 cpumask_set_cpu(i, covered_cpus);
459                 if (pdomain->num_processors <= 1)
460                         continue;
461
462                 /* Validate the Domain info */
463                 count_target = pdomain->num_processors;
464                 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
465                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
466                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
467                         pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
468                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
469                         pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
470
471                 for_each_possible_cpu(j) {
472                         if (i == j)
473                                 continue;
474
475                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
476                         if (!match_cpc_ptr) {
477                                 retval = -EFAULT;
478                                 goto err_ret;
479                         }
480
481                         match_pdomain = &(match_cpc_ptr->domain_info);
482                         if (match_pdomain->domain != pdomain->domain)
483                                 continue;
484
485                         /* Here i and j are in the same domain */
486                         if (match_pdomain->num_processors != count_target) {
487                                 retval = -EFAULT;
488                                 goto err_ret;
489                         }
490
491                         if (pdomain->coord_type != match_pdomain->coord_type) {
492                                 retval = -EFAULT;
493                                 goto err_ret;
494                         }
495
496                         cpumask_set_cpu(j, covered_cpus);
497                         cpumask_set_cpu(j, pr->shared_cpu_map);
498                 }
499
500                 for_each_possible_cpu(j) {
501                         if (i == j)
502                                 continue;
503
504                         match_pr = all_cpu_data[j];
505                         if (!match_pr)
506                                 continue;
507
508                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
509                         if (!match_cpc_ptr) {
510                                 retval = -EFAULT;
511                                 goto err_ret;
512                         }
513
514                         match_pdomain = &(match_cpc_ptr->domain_info);
515                         if (match_pdomain->domain != pdomain->domain)
516                                 continue;
517
518                         match_pr->shared_type = pr->shared_type;
519                         cpumask_copy(match_pr->shared_cpu_map,
520                                      pr->shared_cpu_map);
521                 }
522         }
523
524 err_ret:
525         for_each_possible_cpu(i) {
526                 pr = all_cpu_data[i];
527                 if (!pr)
528                         continue;
529
530                 /* Assume no coordination on any error parsing domain info */
531                 if (retval) {
532                         cpumask_clear(pr->shared_cpu_map);
533                         cpumask_set_cpu(i, pr->shared_cpu_map);
534                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
535                 }
536         }
537
538         free_cpumask_var(covered_cpus);
539         return retval;
540 }
541 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
542
543 static int register_pcc_channel(int pcc_ss_idx)
544 {
545         struct acpi_pcct_hw_reduced *cppc_ss;
546         u64 usecs_lat;
547
548         if (pcc_ss_idx >= 0) {
549                 pcc_data[pcc_ss_idx]->pcc_channel =
550                         pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
551
552                 if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
553                         pr_err("Failed to find PCC channel for subspace %d\n",
554                                pcc_ss_idx);
555                         return -ENODEV;
556                 }
557
558                 /*
559                  * The PCC mailbox controller driver should
560                  * have parsed the PCCT (global table of all
561                  * PCC channels) and stored pointers to the
562                  * subspace communication region in con_priv.
563                  */
564                 cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
565
566                 if (!cppc_ss) {
567                         pr_err("No PCC subspace found for %d CPPC\n",
568                                pcc_ss_idx);
569                         return -ENODEV;
570                 }
571
572                 /*
573                  * cppc_ss->latency is just a Nominal value. In reality
574                  * the remote processor could be much slower to reply.
575                  * So add an arbitrary amount of wait on top of Nominal.
576                  */
577                 usecs_lat = NUM_RETRIES * cppc_ss->latency;
578                 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
579                 pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
580                 pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
581                 pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
582
583                 pcc_data[pcc_ss_idx]->pcc_comm_addr =
584                         acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
585                 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
586                         pr_err("Failed to ioremap PCC comm region mem for %d\n",
587                                pcc_ss_idx);
588                         return -ENOMEM;
589                 }
590
591                 /* Set flag so that we dont come here for each CPU. */
592                 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
593         }
594
595         return 0;
596 }
597
598 /**
599  * cpc_ffh_supported() - check if FFH reading supported
600  *
601  * Check if the architecture has support for functional fixed hardware
602  * read/write capability.
603  *
604  * Return: true for supported, false for not supported
605  */
606 bool __weak cpc_ffh_supported(void)
607 {
608         return false;
609 }
610
611 /**
612  * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
613  *
614  * Check and allocate the cppc_pcc_data memory.
615  * In some processor configurations it is possible that same subspace
616  * is shared between multiple CPU's. This is seen especially in CPU's
617  * with hardware multi-threading support.
618  *
619  * Return: 0 for success, errno for failure
620  */
621 int pcc_data_alloc(int pcc_ss_id)
622 {
623         if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
624                 return -EINVAL;
625
626         if (pcc_data[pcc_ss_id]) {
627                 pcc_data[pcc_ss_id]->refcount++;
628         } else {
629                 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
630                                               GFP_KERNEL);
631                 if (!pcc_data[pcc_ss_id])
632                         return -ENOMEM;
633                 pcc_data[pcc_ss_id]->refcount++;
634         }
635
636         return 0;
637 }
638
639 /* Check if CPPC revision + num_ent combination is supported */
640 static bool is_cppc_supported(int revision, int num_ent)
641 {
642         int expected_num_ent;
643
644         switch (revision) {
645         case CPPC_V2_REV:
646                 expected_num_ent = CPPC_V2_NUM_ENT;
647                 break;
648         case CPPC_V3_REV:
649                 expected_num_ent = CPPC_V3_NUM_ENT;
650                 break;
651         default:
652                 pr_debug("Firmware exports unsupported CPPC revision: %d\n",
653                         revision);
654                 return false;
655         }
656
657         if (expected_num_ent != num_ent) {
658                 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
659                         num_ent, expected_num_ent, revision);
660                 return false;
661         }
662
663         return true;
664 }
665
666 /*
667  * An example CPC table looks like the following.
668  *
669  *      Name(_CPC, Package()
670  *                      {
671  *                      17,
672  *                      NumEntries
673  *                      1,
674  *                      // Revision
675  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
676  *                      // Highest Performance
677  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
678  *                      // Nominal Performance
679  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
680  *                      // Lowest Nonlinear Performance
681  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
682  *                      // Lowest Performance
683  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
684  *                      // Guaranteed Performance Register
685  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
686  *                      // Desired Performance Register
687  *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
688  *                      ..
689  *                      ..
690  *                      ..
691  *
692  *              }
693  * Each Register() encodes how to access that specific register.
694  * e.g. a sample PCC entry has the following encoding:
695  *
696  *      Register (
697  *              PCC,
698  *              AddressSpaceKeyword
699  *              8,
700  *              //RegisterBitWidth
701  *              8,
702  *              //RegisterBitOffset
703  *              0x30,
704  *              //RegisterAddress
705  *              9
706  *              //AccessSize (subspace ID)
707  *              0
708  *              )
709  *      }
710  */
711
712 /**
713  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
714  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
715  *
716  *      Return: 0 for success or negative value for err.
717  */
718 int acpi_cppc_processor_probe(struct acpi_processor *pr)
719 {
720         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
721         union acpi_object *out_obj, *cpc_obj;
722         struct cpc_desc *cpc_ptr;
723         struct cpc_reg *gas_t;
724         struct device *cpu_dev;
725         acpi_handle handle = pr->handle;
726         unsigned int num_ent, i, cpc_rev;
727         int pcc_subspace_id = -1;
728         acpi_status status;
729         int ret = -EFAULT;
730
731         /* Parse the ACPI _CPC table for this cpu. */
732         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
733                         ACPI_TYPE_PACKAGE);
734         if (ACPI_FAILURE(status)) {
735                 ret = -ENODEV;
736                 goto out_buf_free;
737         }
738
739         out_obj = (union acpi_object *) output.pointer;
740
741         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
742         if (!cpc_ptr) {
743                 ret = -ENOMEM;
744                 goto out_buf_free;
745         }
746
747         /* First entry is NumEntries. */
748         cpc_obj = &out_obj->package.elements[0];
749         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
750                 num_ent = cpc_obj->integer.value;
751         } else {
752                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
753                                 cpc_obj->type);
754                 goto out_free;
755         }
756         cpc_ptr->num_entries = num_ent;
757
758         /* Second entry should be revision. */
759         cpc_obj = &out_obj->package.elements[1];
760         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
761                 cpc_rev = cpc_obj->integer.value;
762         } else {
763                 pr_debug("Unexpected entry type(%d) for Revision\n",
764                                 cpc_obj->type);
765                 goto out_free;
766         }
767         cpc_ptr->version = cpc_rev;
768
769         if (!is_cppc_supported(cpc_rev, num_ent))
770                 goto out_free;
771
772         /* Iterate through remaining entries in _CPC */
773         for (i = 2; i < num_ent; i++) {
774                 cpc_obj = &out_obj->package.elements[i];
775
776                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
777                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
778                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
779                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
780                         gas_t = (struct cpc_reg *)
781                                 cpc_obj->buffer.pointer;
782
783                         /*
784                          * The PCC Subspace index is encoded inside
785                          * the CPC table entries. The same PCC index
786                          * will be used for all the PCC entries,
787                          * so extract it only once.
788                          */
789                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
790                                 if (pcc_subspace_id < 0) {
791                                         pcc_subspace_id = gas_t->access_width;
792                                         if (pcc_data_alloc(pcc_subspace_id))
793                                                 goto out_free;
794                                 } else if (pcc_subspace_id != gas_t->access_width) {
795                                         pr_debug("Mismatched PCC ids.\n");
796                                         goto out_free;
797                                 }
798                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
799                                 if (gas_t->address) {
800                                         void __iomem *addr;
801
802                                         addr = ioremap(gas_t->address, gas_t->bit_width/8);
803                                         if (!addr)
804                                                 goto out_free;
805                                         cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
806                                 }
807                         } else {
808                                 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
809                                         /* Support only PCC ,SYS MEM and FFH type regs */
810                                         pr_debug("Unsupported register type: %d\n", gas_t->space_id);
811                                         goto out_free;
812                                 }
813                         }
814
815                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
816                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
817                 } else {
818                         pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
819                         goto out_free;
820                 }
821         }
822         per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
823
824         /*
825          * Initialize the remaining cpc_regs as unsupported.
826          * Example: In case FW exposes CPPC v2, the below loop will initialize
827          * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
828          */
829         for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
830                 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
831                 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
832         }
833
834
835         /* Store CPU Logical ID */
836         cpc_ptr->cpu_id = pr->id;
837
838         /* Parse PSD data for this CPU */
839         ret = acpi_get_psd(cpc_ptr, handle);
840         if (ret)
841                 goto out_free;
842
843         /* Register PCC channel once for all PCC subspace id. */
844         if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
845                 ret = register_pcc_channel(pcc_subspace_id);
846                 if (ret)
847                         goto out_free;
848
849                 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
850                 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
851         }
852
853         /* Everything looks okay */
854         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
855
856         /* Add per logical CPU nodes for reading its feedback counters. */
857         cpu_dev = get_cpu_device(pr->id);
858         if (!cpu_dev) {
859                 ret = -EINVAL;
860                 goto out_free;
861         }
862
863         /* Plug PSD data into this CPUs CPC descriptor. */
864         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
865
866         ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
867                         "acpi_cppc");
868         if (ret) {
869                 per_cpu(cpc_desc_ptr, pr->id) = NULL;
870                 goto out_free;
871         }
872
873         kfree(output.pointer);
874         return 0;
875
876 out_free:
877         /* Free all the mapped sys mem areas for this CPU */
878         for (i = 2; i < cpc_ptr->num_entries; i++) {
879                 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
880
881                 if (addr)
882                         iounmap(addr);
883         }
884         kfree(cpc_ptr);
885
886 out_buf_free:
887         kfree(output.pointer);
888         return ret;
889 }
890 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
891
892 /**
893  * acpi_cppc_processor_exit - Cleanup CPC structs.
894  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
895  *
896  * Return: Void
897  */
898 void acpi_cppc_processor_exit(struct acpi_processor *pr)
899 {
900         struct cpc_desc *cpc_ptr;
901         unsigned int i;
902         void __iomem *addr;
903         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
904
905         if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) {
906                 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
907                         pcc_data[pcc_ss_id]->refcount--;
908                         if (!pcc_data[pcc_ss_id]->refcount) {
909                                 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
910                                 pcc_data[pcc_ss_id]->pcc_channel_acquired = 0;
911                                 kfree(pcc_data[pcc_ss_id]);
912                         }
913                 }
914         }
915
916         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
917         if (!cpc_ptr)
918                 return;
919
920         /* Free all the mapped sys mem areas for this CPU */
921         for (i = 2; i < cpc_ptr->num_entries; i++) {
922                 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
923                 if (addr)
924                         iounmap(addr);
925         }
926
927         kobject_put(&cpc_ptr->kobj);
928         kfree(cpc_ptr);
929 }
930 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
931
932 /**
933  * cpc_read_ffh() - Read FFH register
934  * @cpunum:     cpu number to read
935  * @reg:        cppc register information
936  * @val:        place holder for return value
937  *
938  * Read bit_width bits from a specified address and bit_offset
939  *
940  * Return: 0 for success and error code
941  */
942 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
943 {
944         return -ENOTSUPP;
945 }
946
947 /**
948  * cpc_write_ffh() - Write FFH register
949  * @cpunum:     cpu number to write
950  * @reg:        cppc register information
951  * @val:        value to write
952  *
953  * Write value of bit_width bits to a specified address and bit_offset
954  *
955  * Return: 0 for success and error code
956  */
957 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
958 {
959         return -ENOTSUPP;
960 }
961
962 /*
963  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
964  * as fast as possible. We have already mapped the PCC subspace during init, so
965  * we can directly write to it.
966  */
967
968 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
969 {
970         int ret_val = 0;
971         void __iomem *vaddr = 0;
972         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
973         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
974
975         if (reg_res->type == ACPI_TYPE_INTEGER) {
976                 *val = reg_res->cpc_entry.int_value;
977                 return ret_val;
978         }
979
980         *val = 0;
981         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
982                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
983         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
984                 vaddr = reg_res->sys_mem_vaddr;
985         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
986                 return cpc_read_ffh(cpu, reg, val);
987         else
988                 return acpi_os_read_memory((acpi_physical_address)reg->address,
989                                 val, reg->bit_width);
990
991         switch (reg->bit_width) {
992                 case 8:
993                         *val = readb_relaxed(vaddr);
994                         break;
995                 case 16:
996                         *val = readw_relaxed(vaddr);
997                         break;
998                 case 32:
999                         *val = readl_relaxed(vaddr);
1000                         break;
1001                 case 64:
1002                         *val = readq_relaxed(vaddr);
1003                         break;
1004                 default:
1005                         pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1006                                  reg->bit_width, pcc_ss_id);
1007                         ret_val = -EFAULT;
1008         }
1009
1010         return ret_val;
1011 }
1012
1013 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1014 {
1015         int ret_val = 0;
1016         void __iomem *vaddr = 0;
1017         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1018         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
1019
1020         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
1021                 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1022         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1023                 vaddr = reg_res->sys_mem_vaddr;
1024         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1025                 return cpc_write_ffh(cpu, reg, val);
1026         else
1027                 return acpi_os_write_memory((acpi_physical_address)reg->address,
1028                                 val, reg->bit_width);
1029
1030         switch (reg->bit_width) {
1031                 case 8:
1032                         writeb_relaxed(val, vaddr);
1033                         break;
1034                 case 16:
1035                         writew_relaxed(val, vaddr);
1036                         break;
1037                 case 32:
1038                         writel_relaxed(val, vaddr);
1039                         break;
1040                 case 64:
1041                         writeq_relaxed(val, vaddr);
1042                         break;
1043                 default:
1044                         pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1045                                  reg->bit_width, pcc_ss_id);
1046                         ret_val = -EFAULT;
1047                         break;
1048         }
1049
1050         return ret_val;
1051 }
1052
1053 /**
1054  * cppc_get_perf_caps - Get a CPUs performance capabilities.
1055  * @cpunum: CPU from which to get capabilities info.
1056  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1057  *
1058  * Return: 0 for success with perf_caps populated else -ERRNO.
1059  */
1060 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1061 {
1062         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1063         struct cpc_register_resource *highest_reg, *lowest_reg,
1064                 *lowest_non_linear_reg, *nominal_reg,
1065                 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1066         u64 high, low, nom, min_nonlinear, low_f = 0, nom_f = 0;
1067         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1068         struct cppc_pcc_data *pcc_ss_data = NULL;
1069         int ret = 0, regs_in_pcc = 0;
1070
1071         if (!cpc_desc) {
1072                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1073                 return -ENODEV;
1074         }
1075
1076         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1077         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1078         lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1079         nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1080         low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1081         nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1082
1083         /* Are any of the regs PCC ?*/
1084         if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1085                 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1086                 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1087                 if (pcc_ss_id < 0) {
1088                         pr_debug("Invalid pcc_ss_id\n");
1089                         return -ENODEV;
1090                 }
1091                 pcc_ss_data = pcc_data[pcc_ss_id];
1092                 regs_in_pcc = 1;
1093                 down_write(&pcc_ss_data->pcc_lock);
1094                 /* Ring doorbell once to update PCC subspace */
1095                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1096                         ret = -EIO;
1097                         goto out_err;
1098                 }
1099         }
1100
1101         cpc_read(cpunum, highest_reg, &high);
1102         perf_caps->highest_perf = high;
1103
1104         cpc_read(cpunum, lowest_reg, &low);
1105         perf_caps->lowest_perf = low;
1106
1107         cpc_read(cpunum, nominal_reg, &nom);
1108         perf_caps->nominal_perf = nom;
1109
1110         cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1111         perf_caps->lowest_nonlinear_perf = min_nonlinear;
1112
1113         if (!high || !low || !nom || !min_nonlinear)
1114                 ret = -EFAULT;
1115
1116         /* Read optional lowest and nominal frequencies if present */
1117         if (CPC_SUPPORTED(low_freq_reg))
1118                 cpc_read(cpunum, low_freq_reg, &low_f);
1119
1120         if (CPC_SUPPORTED(nom_freq_reg))
1121                 cpc_read(cpunum, nom_freq_reg, &nom_f);
1122
1123         perf_caps->lowest_freq = low_f;
1124         perf_caps->nominal_freq = nom_f;
1125
1126
1127 out_err:
1128         if (regs_in_pcc)
1129                 up_write(&pcc_ss_data->pcc_lock);
1130         return ret;
1131 }
1132 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1133
1134 /**
1135  * cppc_get_perf_ctrs - Read a CPUs performance feedback counters.
1136  * @cpunum: CPU from which to read counters.
1137  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1138  *
1139  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1140  */
1141 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1142 {
1143         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1144         struct cpc_register_resource *delivered_reg, *reference_reg,
1145                 *ref_perf_reg, *ctr_wrap_reg;
1146         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1147         struct cppc_pcc_data *pcc_ss_data = NULL;
1148         u64 delivered, reference, ref_perf, ctr_wrap_time;
1149         int ret = 0, regs_in_pcc = 0;
1150
1151         if (!cpc_desc) {
1152                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1153                 return -ENODEV;
1154         }
1155
1156         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1157         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1158         ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1159         ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1160
1161         /*
1162          * If refernce perf register is not supported then we should
1163          * use the nominal perf value
1164          */
1165         if (!CPC_SUPPORTED(ref_perf_reg))
1166                 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1167
1168         /* Are any of the regs PCC ?*/
1169         if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1170                 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1171                 if (pcc_ss_id < 0) {
1172                         pr_debug("Invalid pcc_ss_id\n");
1173                         return -ENODEV;
1174                 }
1175                 pcc_ss_data = pcc_data[pcc_ss_id];
1176                 down_write(&pcc_ss_data->pcc_lock);
1177                 regs_in_pcc = 1;
1178                 /* Ring doorbell once to update PCC subspace */
1179                 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1180                         ret = -EIO;
1181                         goto out_err;
1182                 }
1183         }
1184
1185         cpc_read(cpunum, delivered_reg, &delivered);
1186         cpc_read(cpunum, reference_reg, &reference);
1187         cpc_read(cpunum, ref_perf_reg, &ref_perf);
1188
1189         /*
1190          * Per spec, if ctr_wrap_time optional register is unsupported, then the
1191          * performance counters are assumed to never wrap during the lifetime of
1192          * platform
1193          */
1194         ctr_wrap_time = (u64)(~((u64)0));
1195         if (CPC_SUPPORTED(ctr_wrap_reg))
1196                 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1197
1198         if (!delivered || !reference || !ref_perf) {
1199                 ret = -EFAULT;
1200                 goto out_err;
1201         }
1202
1203         perf_fb_ctrs->delivered = delivered;
1204         perf_fb_ctrs->reference = reference;
1205         perf_fb_ctrs->reference_perf = ref_perf;
1206         perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1207 out_err:
1208         if (regs_in_pcc)
1209                 up_write(&pcc_ss_data->pcc_lock);
1210         return ret;
1211 }
1212 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1213
1214 /**
1215  * cppc_set_perf - Set a CPUs performance controls.
1216  * @cpu: CPU for which to set performance controls.
1217  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1218  *
1219  * Return: 0 for success, -ERRNO otherwise.
1220  */
1221 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1222 {
1223         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1224         struct cpc_register_resource *desired_reg;
1225         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1226         struct cppc_pcc_data *pcc_ss_data = NULL;
1227         int ret = 0;
1228
1229         if (!cpc_desc) {
1230                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1231                 return -ENODEV;
1232         }
1233
1234         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1235
1236         /*
1237          * This is Phase-I where we want to write to CPC registers
1238          * -> We want all CPUs to be able to execute this phase in parallel
1239          *
1240          * Since read_lock can be acquired by multiple CPUs simultaneously we
1241          * achieve that goal here
1242          */
1243         if (CPC_IN_PCC(desired_reg)) {
1244                 if (pcc_ss_id < 0) {
1245                         pr_debug("Invalid pcc_ss_id\n");
1246                         return -ENODEV;
1247                 }
1248                 pcc_ss_data = pcc_data[pcc_ss_id];
1249                 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1250                 if (pcc_ss_data->platform_owns_pcc) {
1251                         ret = check_pcc_chan(pcc_ss_id, false);
1252                         if (ret) {
1253                                 up_read(&pcc_ss_data->pcc_lock);
1254                                 return ret;
1255                         }
1256                 }
1257                 /*
1258                  * Update the pending_write to make sure a PCC CMD_READ will not
1259                  * arrive and steal the channel during the switch to write lock
1260                  */
1261                 pcc_ss_data->pending_pcc_write_cmd = true;
1262                 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1263                 cpc_desc->write_cmd_status = 0;
1264         }
1265
1266         /*
1267          * Skip writing MIN/MAX until Linux knows how to come up with
1268          * useful values.
1269          */
1270         cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1271
1272         if (CPC_IN_PCC(desired_reg))
1273                 up_read(&pcc_ss_data->pcc_lock);        /* END Phase-I */
1274         /*
1275          * This is Phase-II where we transfer the ownership of PCC to Platform
1276          *
1277          * Short Summary: Basically if we think of a group of cppc_set_perf
1278          * requests that happened in short overlapping interval. The last CPU to
1279          * come out of Phase-I will enter Phase-II and ring the doorbell.
1280          *
1281          * We have the following requirements for Phase-II:
1282          *     1. We want to execute Phase-II only when there are no CPUs
1283          * currently executing in Phase-I
1284          *     2. Once we start Phase-II we want to avoid all other CPUs from
1285          * entering Phase-I.
1286          *     3. We want only one CPU among all those who went through Phase-I
1287          * to run phase-II
1288          *
1289          * If write_trylock fails to get the lock and doesn't transfer the
1290          * PCC ownership to the platform, then one of the following will be TRUE
1291          *     1. There is at-least one CPU in Phase-I which will later execute
1292          * write_trylock, so the CPUs in Phase-I will be responsible for
1293          * executing the Phase-II.
1294          *     2. Some other CPU has beaten this CPU to successfully execute the
1295          * write_trylock and has already acquired the write_lock. We know for a
1296          * fact it(other CPU acquiring the write_lock) couldn't have happened
1297          * before this CPU's Phase-I as we held the read_lock.
1298          *     3. Some other CPU executing pcc CMD_READ has stolen the
1299          * down_write, in which case, send_pcc_cmd will check for pending
1300          * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1301          * So this CPU can be certain that its request will be delivered
1302          *    So in all cases, this CPU knows that its request will be delivered
1303          * by another CPU and can return
1304          *
1305          * After getting the down_write we still need to check for
1306          * pending_pcc_write_cmd to take care of the following scenario
1307          *    The thread running this code could be scheduled out between
1308          * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1309          * could have delivered the request to Platform by triggering the
1310          * doorbell and transferred the ownership of PCC to platform. So this
1311          * avoids triggering an unnecessary doorbell and more importantly before
1312          * triggering the doorbell it makes sure that the PCC channel ownership
1313          * is still with OSPM.
1314          *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1315          * there was a pcc CMD_READ waiting on down_write and it steals the lock
1316          * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
1317          * case during a CMD_READ and if there are pending writes it delivers
1318          * the write command before servicing the read command
1319          */
1320         if (CPC_IN_PCC(desired_reg)) {
1321                 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1322                         /* Update only if there are pending write commands */
1323                         if (pcc_ss_data->pending_pcc_write_cmd)
1324                                 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1325                         up_write(&pcc_ss_data->pcc_lock);       /* END Phase-II */
1326                 } else
1327                         /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1328                         wait_event(pcc_ss_data->pcc_write_wait_q,
1329                                    cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1330
1331                 /* send_pcc_cmd updates the status in case of failure */
1332                 ret = cpc_desc->write_cmd_status;
1333         }
1334         return ret;
1335 }
1336 EXPORT_SYMBOL_GPL(cppc_set_perf);
1337
1338 /**
1339  * cppc_get_transition_latency - returns frequency transition latency in ns
1340  *
1341  * ACPI CPPC does not explicitly specifiy how a platform can specify the
1342  * transition latency for perfromance change requests. The closest we have
1343  * is the timing information from the PCCT tables which provides the info
1344  * on the number and frequency of PCC commands the platform can handle.
1345  */
1346 unsigned int cppc_get_transition_latency(int cpu_num)
1347 {
1348         /*
1349          * Expected transition latency is based on the PCCT timing values
1350          * Below are definition from ACPI spec:
1351          * pcc_nominal- Expected latency to process a command, in microseconds
1352          * pcc_mpar   - The maximum number of periodic requests that the subspace
1353          *              channel can support, reported in commands per minute. 0
1354          *              indicates no limitation.
1355          * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1356          *              completion of a command before issuing the next command,
1357          *              in microseconds.
1358          */
1359         unsigned int latency_ns = 0;
1360         struct cpc_desc *cpc_desc;
1361         struct cpc_register_resource *desired_reg;
1362         int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1363         struct cppc_pcc_data *pcc_ss_data;
1364
1365         cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1366         if (!cpc_desc)
1367                 return CPUFREQ_ETERNAL;
1368
1369         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1370         if (!CPC_IN_PCC(desired_reg))
1371                 return CPUFREQ_ETERNAL;
1372
1373         if (pcc_ss_id < 0)
1374                 return CPUFREQ_ETERNAL;
1375
1376         pcc_ss_data = pcc_data[pcc_ss_id];
1377         if (pcc_ss_data->pcc_mpar)
1378                 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1379
1380         latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1381         latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1382
1383         return latency_ns;
1384 }
1385 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);