ahci: imx: add the imx8qm ahci sata support
[muen/linux.git] / drivers / ata / ahci_imx.c
1 /*
2  * copyright (c) 2013 Freescale Semiconductor, Inc.
3  * Freescale IMX AHCI SATA platform driver
4  *
5  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program. If not, see <http://www.gnu.org/licenses/>.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/ahci_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/of_gpio.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
29 #include <linux/libata.h>
30 #include <linux/hwmon.h>
31 #include <linux/hwmon-sysfs.h>
32 #include <linux/thermal.h>
33 #include "ahci.h"
34
35 #define DRV_NAME "ahci-imx"
36
37 enum {
38         /* Timer 1-ms Register */
39         IMX_TIMER1MS                            = 0x00e0,
40         /* Port0 PHY Control Register */
41         IMX_P0PHYCR                             = 0x0178,
42         IMX_P0PHYCR_TEST_PDDQ                   = 1 << 20,
43         IMX_P0PHYCR_CR_READ                     = 1 << 19,
44         IMX_P0PHYCR_CR_WRITE                    = 1 << 18,
45         IMX_P0PHYCR_CR_CAP_DATA                 = 1 << 17,
46         IMX_P0PHYCR_CR_CAP_ADDR                 = 1 << 16,
47         /* Port0 PHY Status Register */
48         IMX_P0PHYSR                             = 0x017c,
49         IMX_P0PHYSR_CR_ACK                      = 1 << 18,
50         IMX_P0PHYSR_CR_DATA_OUT                 = 0xffff << 0,
51         /* Lane0 Output Status Register */
52         IMX_LANE0_OUT_STAT                      = 0x2003,
53         IMX_LANE0_OUT_STAT_RX_PLL_STATE         = 1 << 1,
54         /* Clock Reset Register */
55         IMX_CLOCK_RESET                         = 0x7f3f,
56         IMX_CLOCK_RESET_RESET                   = 1 << 0,
57         /* IMX8QM HSIO AHCI definitions */
58         IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET   = 0x03,
59         IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET   = 0x09,
60         IMX8QM_SATA_PHY_IMPED_RATIO_85OHM       = 0x6c,
61         IMX8QM_LPCG_PHYX2_OFFSET                = 0x00000,
62         IMX8QM_CSR_PHYX2_OFFSET                 = 0x90000,
63         IMX8QM_CSR_PHYX1_OFFSET                 = 0xa0000,
64         IMX8QM_CSR_PHYX_STTS0_OFFSET            = 0x4,
65         IMX8QM_CSR_PCIEA_OFFSET                 = 0xb0000,
66         IMX8QM_CSR_PCIEB_OFFSET                 = 0xc0000,
67         IMX8QM_CSR_SATA_OFFSET                  = 0xd0000,
68         IMX8QM_CSR_PCIE_CTRL2_OFFSET            = 0x8,
69         IMX8QM_CSR_MISC_OFFSET                  = 0xe0000,
70
71         IMX8QM_LPCG_PHYX2_PCLK0_MASK            = (0x3 << 16),
72         IMX8QM_LPCG_PHYX2_PCLK1_MASK            = (0x3 << 20),
73         IMX8QM_PHY_APB_RSTN_0                   = BIT(0),
74         IMX8QM_PHY_MODE_SATA                    = BIT(19),
75         IMX8QM_PHY_MODE_MASK                    = (0xf << 17),
76         IMX8QM_PHY_PIPE_RSTN_0                  = BIT(24),
77         IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0         = BIT(25),
78         IMX8QM_PHY_PIPE_RSTN_1                  = BIT(26),
79         IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1         = BIT(27),
80         IMX8QM_STTS0_LANE0_TX_PLL_LOCK          = BIT(4),
81         IMX8QM_MISC_IOB_RXENA                   = BIT(0),
82         IMX8QM_MISC_IOB_TXENA                   = BIT(1),
83         IMX8QM_MISC_PHYX1_EPCS_SEL              = BIT(12),
84         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1      = BIT(24),
85         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0      = BIT(25),
86         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1       = BIT(28),
87         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0       = BIT(29),
88         IMX8QM_SATA_CTRL_RESET_N                = BIT(12),
89         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N        = BIT(7),
90         IMX8QM_CTRL_BUTTON_RST_N                = BIT(21),
91         IMX8QM_CTRL_POWER_UP_RST_N              = BIT(23),
92         IMX8QM_CTRL_LTSSM_ENABLE                = BIT(4),
93 };
94
95 enum ahci_imx_type {
96         AHCI_IMX53,
97         AHCI_IMX6Q,
98         AHCI_IMX6QP,
99         AHCI_IMX8QM,
100 };
101
102 struct imx_ahci_priv {
103         struct platform_device *ahci_pdev;
104         enum ahci_imx_type type;
105         struct clk *sata_clk;
106         struct clk *sata_ref_clk;
107         struct clk *ahb_clk;
108         struct clk *epcs_tx_clk;
109         struct clk *epcs_rx_clk;
110         struct clk *phy_apbclk;
111         struct clk *phy_pclk0;
112         struct clk *phy_pclk1;
113         void __iomem *phy_base;
114         int clkreq_gpio;
115         struct regmap *gpr;
116         bool no_device;
117         bool first_time;
118         u32 phy_params;
119         u32 imped_ratio;
120 };
121
122 static int ahci_imx_hotplug;
123 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
124 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
125
126 static void ahci_imx_host_stop(struct ata_host *host);
127
128 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
129 {
130         int timeout = 10;
131         u32 crval;
132         u32 srval;
133
134         /* Assert or deassert the bit */
135         crval = readl(mmio + IMX_P0PHYCR);
136         if (assert)
137                 crval |= bit;
138         else
139                 crval &= ~bit;
140         writel(crval, mmio + IMX_P0PHYCR);
141
142         /* Wait for the cr_ack signal */
143         do {
144                 srval = readl(mmio + IMX_P0PHYSR);
145                 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
146                         break;
147                 usleep_range(100, 200);
148         } while (--timeout);
149
150         return timeout ? 0 : -ETIMEDOUT;
151 }
152
153 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
154 {
155         u32 crval = addr;
156         int ret;
157
158         /* Supply the address on cr_data_in */
159         writel(crval, mmio + IMX_P0PHYCR);
160
161         /* Assert the cr_cap_addr signal */
162         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
163         if (ret)
164                 return ret;
165
166         /* Deassert cr_cap_addr */
167         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
168         if (ret)
169                 return ret;
170
171         return 0;
172 }
173
174 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
175 {
176         u32 crval = val;
177         int ret;
178
179         /* Supply the data on cr_data_in */
180         writel(crval, mmio + IMX_P0PHYCR);
181
182         /* Assert the cr_cap_data signal */
183         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
184         if (ret)
185                 return ret;
186
187         /* Deassert cr_cap_data */
188         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
189         if (ret)
190                 return ret;
191
192         if (val & IMX_CLOCK_RESET_RESET) {
193                 /*
194                  * In case we're resetting the phy, it's unable to acknowledge,
195                  * so we return immediately here.
196                  */
197                 crval |= IMX_P0PHYCR_CR_WRITE;
198                 writel(crval, mmio + IMX_P0PHYCR);
199                 goto out;
200         }
201
202         /* Assert the cr_write signal */
203         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
204         if (ret)
205                 return ret;
206
207         /* Deassert cr_write */
208         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
209         if (ret)
210                 return ret;
211
212 out:
213         return 0;
214 }
215
216 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
217 {
218         int ret;
219
220         /* Assert the cr_read signal */
221         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
222         if (ret)
223                 return ret;
224
225         /* Capture the data from cr_data_out[] */
226         *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
227
228         /* Deassert cr_read */
229         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
230         if (ret)
231                 return ret;
232
233         return 0;
234 }
235
236 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
237 {
238         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
239         void __iomem *mmio = hpriv->mmio;
240         int timeout = 10;
241         u16 val;
242         int ret;
243
244         if (imxpriv->type == AHCI_IMX6QP) {
245                 /* 6qp adds the sata reset mechanism, use it for 6qp sata */
246                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
247                                    IMX6Q_GPR5_SATA_SW_PD, 0);
248
249                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
250                                    IMX6Q_GPR5_SATA_SW_RST, 0);
251                 udelay(50);
252                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
253                                    IMX6Q_GPR5_SATA_SW_RST,
254                                    IMX6Q_GPR5_SATA_SW_RST);
255                 return 0;
256         }
257
258         /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
259         ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
260         if (ret)
261                 return ret;
262         ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
263         if (ret)
264                 return ret;
265
266         /* Wait for PHY RX_PLL to be stable */
267         do {
268                 usleep_range(100, 200);
269                 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
270                 if (ret)
271                         return ret;
272                 ret = imx_phy_reg_read(&val, mmio);
273                 if (ret)
274                         return ret;
275                 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
276                         break;
277         } while (--timeout);
278
279         return timeout ? 0 : -ETIMEDOUT;
280 }
281
282 enum {
283         /* SATA PHY Register */
284         SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
285         SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
286         SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
287         SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
288         SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
289 };
290
291 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
292 {
293         u16 adc_out_reg, read_sum;
294         u32 index, read_attempt;
295         const u32 attempt_limit = 200;
296
297         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
298         imx_phy_reg_write(rtune_ctl_reg, mmio);
299
300         /* two dummy read */
301         index = 0;
302         read_attempt = 0;
303         adc_out_reg = 0;
304         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
305         while (index < 2) {
306                 imx_phy_reg_read(&adc_out_reg, mmio);
307                 /* check if valid */
308                 if (adc_out_reg & 0x400)
309                         index++;
310
311                 read_attempt++;
312                 if (read_attempt > attempt_limit) {
313                         dev_err(dev, "Read REG more than %d times!\n",
314                                 attempt_limit);
315                         break;
316                 }
317         }
318
319         index = 0;
320         read_attempt = 0;
321         read_sum = 0;
322         while (index < 80) {
323                 imx_phy_reg_read(&adc_out_reg, mmio);
324                 if (adc_out_reg & 0x400) {
325                         read_sum = read_sum + (adc_out_reg & 0x3FF);
326                         index++;
327                 }
328                 read_attempt++;
329                 if (read_attempt > attempt_limit) {
330                         dev_err(dev, "Read REG more than %d times!\n",
331                                 attempt_limit);
332                         break;
333                 }
334         }
335
336         /* Use the U32 to make 1000 precision */
337         return (read_sum * 1000) / 80;
338 }
339
340 /* SATA AHCI temperature monitor */
341 static int sata_ahci_read_temperature(void *dev, int *temp)
342 {
343         u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
344         u32 str1, str2, str3, str4;
345         int m1, m2, a;
346         struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
347         void __iomem *mmio = hpriv->mmio;
348
349         /* check rd-wr to reg */
350         read_sum = 0;
351         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
352         imx_phy_reg_write(read_sum, mmio);
353         imx_phy_reg_read(&read_sum, mmio);
354         if ((read_sum & 0xffff) != 0)
355                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
356
357         imx_phy_reg_write(0x5A5A, mmio);
358         imx_phy_reg_read(&read_sum, mmio);
359         if ((read_sum & 0xffff) != 0x5A5A)
360                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
361
362         imx_phy_reg_write(0x1234, mmio);
363         imx_phy_reg_read(&read_sum, mmio);
364         if ((read_sum & 0xffff) != 0x1234)
365                 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
366
367         /* start temperature test */
368         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
369         imx_phy_reg_read(&mpll_test_reg, mmio);
370         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
371         imx_phy_reg_read(&rtune_ctl_reg, mmio);
372         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
373         imx_phy_reg_read(&dac_ctl_reg, mmio);
374
375         /* mpll_tst.meas_iv   ([12:2]) */
376         str1 = (mpll_test_reg >> 2) & 0x7FF;
377         /* rtune_ctl.mode     ([1:0]) */
378         str2 = (rtune_ctl_reg) & 0x3;
379         /* dac_ctl.dac_mode   ([14:12]) */
380         str3 = (dac_ctl_reg >> 12)  & 0x7;
381         /* rtune_ctl.sel_atbp ([4]) */
382         str4 = (rtune_ctl_reg >> 4);
383
384         /* Calculate the m1 */
385         /* mpll_tst.meas_iv */
386         mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
387         /* rtune_ctl.mode */
388         rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
389         /* dac_ctl.dac_mode */
390         dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
391         /* rtune_ctl.sel_atbp */
392         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
393         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
394         imx_phy_reg_write(mpll_test_reg, mmio);
395         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
396         imx_phy_reg_write(dac_ctl_reg, mmio);
397         m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
398
399         /* Calculate the m2 */
400         /* rtune_ctl.sel_atbp */
401         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
402         m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
403
404         /* restore the status  */
405         /* mpll_tst.meas_iv */
406         mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
407         /* rtune_ctl.mode */
408         rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
409         /* dac_ctl.dac_mode */
410         dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
411         /* rtune_ctl.sel_atbp */
412         rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
413
414         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
415         imx_phy_reg_write(mpll_test_reg, mmio);
416         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
417         imx_phy_reg_write(dac_ctl_reg, mmio);
418         imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
419         imx_phy_reg_write(rtune_ctl_reg, mmio);
420
421         /* Compute temperature */
422         if (!(m2 / 1000))
423                 m2 = 1000;
424         a = (m2 - m1) / (m2/1000);
425         *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
426
427         return 0;
428 }
429
430 static ssize_t sata_ahci_show_temp(struct device *dev,
431                                    struct device_attribute *da,
432                                    char *buf)
433 {
434         unsigned int temp = 0;
435         int err;
436
437         err = sata_ahci_read_temperature(dev, &temp);
438         if (err < 0)
439                 return err;
440
441         return sprintf(buf, "%u\n", temp);
442 }
443
444 static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = {
445         .get_temp = sata_ahci_read_temperature,
446 };
447
448 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
449
450 static struct attribute *fsl_sata_ahci_attrs[] = {
451         &sensor_dev_attr_temp1_input.dev_attr.attr,
452         NULL
453 };
454 ATTRIBUTE_GROUPS(fsl_sata_ahci);
455
456 static int imx8_sata_enable(struct ahci_host_priv *hpriv)
457 {
458         u32 val, reg;
459         int i, ret;
460         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
461         struct device *dev = &imxpriv->ahci_pdev->dev;
462
463         /* configure the hsio for sata */
464         ret = clk_prepare_enable(imxpriv->phy_pclk0);
465         if (ret < 0) {
466                 dev_err(dev, "can't enable phy_pclk0.\n");
467                 return ret;
468         }
469         ret = clk_prepare_enable(imxpriv->phy_pclk1);
470         if (ret < 0) {
471                 dev_err(dev, "can't enable phy_pclk1.\n");
472                 goto disable_phy_pclk0;
473         }
474         ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
475         if (ret < 0) {
476                 dev_err(dev, "can't enable epcs_tx_clk.\n");
477                 goto disable_phy_pclk1;
478         }
479         ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
480         if (ret < 0) {
481                 dev_err(dev, "can't enable epcs_rx_clk.\n");
482                 goto disable_epcs_tx_clk;
483         }
484         ret = clk_prepare_enable(imxpriv->phy_apbclk);
485         if (ret < 0) {
486                 dev_err(dev, "can't enable phy_apbclk.\n");
487                 goto disable_epcs_rx_clk;
488         }
489         /* Configure PHYx2 PIPE_RSTN */
490         regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
491                         IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
492         if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
493                 /* The link of the PCIEA of HSIO is down */
494                 regmap_update_bits(imxpriv->gpr,
495                                 IMX8QM_CSR_PHYX2_OFFSET,
496                                 IMX8QM_PHY_PIPE_RSTN_0 |
497                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
498                                 IMX8QM_PHY_PIPE_RSTN_0 |
499                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
500         }
501         regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
502                         IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
503         if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
504                 /* The link of the PCIEB of HSIO is down */
505                 regmap_update_bits(imxpriv->gpr,
506                                 IMX8QM_CSR_PHYX2_OFFSET,
507                                 IMX8QM_PHY_PIPE_RSTN_1 |
508                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
509                                 IMX8QM_PHY_PIPE_RSTN_1 |
510                                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
511         }
512         if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
513                 /* The links of both PCIA and PCIEB of HSIO are down */
514                 regmap_update_bits(imxpriv->gpr,
515                                 IMX8QM_LPCG_PHYX2_OFFSET,
516                                 IMX8QM_LPCG_PHYX2_PCLK0_MASK |
517                                 IMX8QM_LPCG_PHYX2_PCLK1_MASK,
518                                 0);
519         }
520
521         /* set PWR_RST and BT_RST of csr_pciea */
522         val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
523         regmap_update_bits(imxpriv->gpr,
524                         val,
525                         IMX8QM_CTRL_BUTTON_RST_N,
526                         IMX8QM_CTRL_BUTTON_RST_N);
527         regmap_update_bits(imxpriv->gpr,
528                         val,
529                         IMX8QM_CTRL_POWER_UP_RST_N,
530                         IMX8QM_CTRL_POWER_UP_RST_N);
531
532         /* PHYX1_MODE to SATA */
533         regmap_update_bits(imxpriv->gpr,
534                         IMX8QM_CSR_PHYX1_OFFSET,
535                         IMX8QM_PHY_MODE_MASK,
536                         IMX8QM_PHY_MODE_SATA);
537
538         /*
539          * BIT0 RXENA 1, BIT1 TXENA 0
540          * BIT12 PHY_X1_EPCS_SEL 1.
541          */
542         regmap_update_bits(imxpriv->gpr,
543                         IMX8QM_CSR_MISC_OFFSET,
544                         IMX8QM_MISC_IOB_RXENA,
545                         IMX8QM_MISC_IOB_RXENA);
546         regmap_update_bits(imxpriv->gpr,
547                         IMX8QM_CSR_MISC_OFFSET,
548                         IMX8QM_MISC_IOB_TXENA,
549                         0);
550         regmap_update_bits(imxpriv->gpr,
551                         IMX8QM_CSR_MISC_OFFSET,
552                         IMX8QM_MISC_PHYX1_EPCS_SEL,
553                         IMX8QM_MISC_PHYX1_EPCS_SEL);
554         /*
555          * It is possible, for PCIe and SATA are sharing
556          * the same clock source, HPLL or external oscillator.
557          * When PCIe is in low power modes (L1.X or L2 etc),
558          * the clock source can be turned off. In this case,
559          * if this clock source is required to be toggling by
560          * SATA, then SATA functions will be abnormal.
561          * Set the override here to avoid it.
562          */
563         regmap_update_bits(imxpriv->gpr,
564                         IMX8QM_CSR_MISC_OFFSET,
565                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
566                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
567                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
568                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
569                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
570                         IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
571                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
572                         IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
573
574         /* clear PHY RST, then set it */
575         regmap_update_bits(imxpriv->gpr,
576                         IMX8QM_CSR_SATA_OFFSET,
577                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
578                         0);
579
580         regmap_update_bits(imxpriv->gpr,
581                         IMX8QM_CSR_SATA_OFFSET,
582                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
583                         IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
584
585         /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
586         regmap_update_bits(imxpriv->gpr,
587                         IMX8QM_CSR_SATA_OFFSET,
588                         IMX8QM_SATA_CTRL_RESET_N,
589                         IMX8QM_SATA_CTRL_RESET_N);
590         udelay(1);
591         regmap_update_bits(imxpriv->gpr,
592                         IMX8QM_CSR_SATA_OFFSET,
593                         IMX8QM_SATA_CTRL_RESET_N,
594                         0);
595         regmap_update_bits(imxpriv->gpr,
596                         IMX8QM_CSR_SATA_OFFSET,
597                         IMX8QM_SATA_CTRL_RESET_N,
598                         IMX8QM_SATA_CTRL_RESET_N);
599
600         /* APB reset */
601         regmap_update_bits(imxpriv->gpr,
602                         IMX8QM_CSR_PHYX1_OFFSET,
603                         IMX8QM_PHY_APB_RSTN_0,
604                         IMX8QM_PHY_APB_RSTN_0);
605
606         for (i = 0; i < 100; i++) {
607                 reg = IMX8QM_CSR_PHYX1_OFFSET +
608                         IMX8QM_CSR_PHYX_STTS0_OFFSET;
609                 regmap_read(imxpriv->gpr, reg, &val);
610                 val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
611                 if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
612                         break;
613                 udelay(1);
614         }
615
616         if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
617                 dev_err(dev, "TX PLL of the PHY is not locked\n");
618                 ret = -ENODEV;
619         } else {
620                 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
621                                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
622                 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
623                                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
624                 reg = readb(imxpriv->phy_base +
625                                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
626                 if (unlikely(reg != imxpriv->imped_ratio))
627                         dev_info(dev, "Can't set PHY RX impedance ratio.\n");
628                 reg = readb(imxpriv->phy_base +
629                                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
630                 if (unlikely(reg != imxpriv->imped_ratio))
631                         dev_info(dev, "Can't set PHY TX impedance ratio.\n");
632                 usleep_range(50, 100);
633
634                 /*
635                  * To reduce the power consumption, gate off
636                  * the PHY clks
637                  */
638                 clk_disable_unprepare(imxpriv->phy_apbclk);
639                 clk_disable_unprepare(imxpriv->phy_pclk1);
640                 clk_disable_unprepare(imxpriv->phy_pclk0);
641                 return ret;
642         }
643
644         clk_disable_unprepare(imxpriv->phy_apbclk);
645 disable_epcs_rx_clk:
646         clk_disable_unprepare(imxpriv->epcs_rx_clk);
647 disable_epcs_tx_clk:
648         clk_disable_unprepare(imxpriv->epcs_tx_clk);
649 disable_phy_pclk1:
650         clk_disable_unprepare(imxpriv->phy_pclk1);
651 disable_phy_pclk0:
652         clk_disable_unprepare(imxpriv->phy_pclk0);
653
654         return ret;
655 }
656
657 static int imx_sata_enable(struct ahci_host_priv *hpriv)
658 {
659         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
660         struct device *dev = &imxpriv->ahci_pdev->dev;
661         int ret;
662
663         if (imxpriv->no_device)
664                 return 0;
665
666         ret = ahci_platform_enable_regulators(hpriv);
667         if (ret)
668                 return ret;
669
670         ret = clk_prepare_enable(imxpriv->sata_ref_clk);
671         if (ret < 0)
672                 goto disable_regulator;
673
674         if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
675                 /*
676                  * set PHY Paremeters, two steps to configure the GPR13,
677                  * one write for rest of parameters, mask of first write
678                  * is 0x07ffffff, and the other one write for setting
679                  * the mpll_clk_en.
680                  */
681                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
682                                    IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
683                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
684                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
685                                    IMX6Q_GPR13_SATA_SPD_MODE_MASK |
686                                    IMX6Q_GPR13_SATA_MPLL_SS_EN |
687                                    IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
688                                    IMX6Q_GPR13_SATA_TX_BOOST_MASK |
689                                    IMX6Q_GPR13_SATA_TX_LVL_MASK |
690                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN |
691                                    IMX6Q_GPR13_SATA_TX_EDGE_RATE,
692                                    imxpriv->phy_params);
693                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
694                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
695                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN);
696
697                 usleep_range(100, 200);
698
699                 ret = imx_sata_phy_reset(hpriv);
700                 if (ret) {
701                         dev_err(dev, "failed to reset phy: %d\n", ret);
702                         goto disable_clk;
703                 }
704         } else if (imxpriv->type == AHCI_IMX8QM) {
705                 ret = imx8_sata_enable(hpriv);
706         }
707
708         usleep_range(1000, 2000);
709
710         return 0;
711
712 disable_clk:
713         clk_disable_unprepare(imxpriv->sata_ref_clk);
714 disable_regulator:
715         ahci_platform_disable_regulators(hpriv);
716
717         return ret;
718 }
719
720 static void imx_sata_disable(struct ahci_host_priv *hpriv)
721 {
722         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
723
724         if (imxpriv->no_device)
725                 return;
726
727         switch (imxpriv->type) {
728         case AHCI_IMX6QP:
729                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
730                                    IMX6Q_GPR5_SATA_SW_PD,
731                                    IMX6Q_GPR5_SATA_SW_PD);
732                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
733                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
734                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
735                 break;
736
737         case AHCI_IMX6Q:
738                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
739                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
740                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
741                 break;
742
743         case AHCI_IMX8QM:
744                 clk_disable_unprepare(imxpriv->epcs_rx_clk);
745                 clk_disable_unprepare(imxpriv->epcs_tx_clk);
746                 break;
747
748         default:
749                 break;
750         }
751
752         clk_disable_unprepare(imxpriv->sata_ref_clk);
753
754         ahci_platform_disable_regulators(hpriv);
755 }
756
757 static void ahci_imx_error_handler(struct ata_port *ap)
758 {
759         u32 reg_val;
760         struct ata_device *dev;
761         struct ata_host *host = dev_get_drvdata(ap->dev);
762         struct ahci_host_priv *hpriv = host->private_data;
763         void __iomem *mmio = hpriv->mmio;
764         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
765
766         ahci_error_handler(ap);
767
768         if (!(imxpriv->first_time) || ahci_imx_hotplug)
769                 return;
770
771         imxpriv->first_time = false;
772
773         ata_for_each_dev(dev, &ap->link, ENABLED)
774                 return;
775         /*
776          * Disable link to save power.  An imx ahci port can't be recovered
777          * without full reset once the pddq mode is enabled making it
778          * impossible to use as part of libata LPM.
779          */
780         reg_val = readl(mmio + IMX_P0PHYCR);
781         writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
782         imx_sata_disable(hpriv);
783         imxpriv->no_device = true;
784
785         dev_info(ap->dev, "no device found, disabling link.\n");
786         dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
787 }
788
789 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
790                        unsigned long deadline)
791 {
792         struct ata_port *ap = link->ap;
793         struct ata_host *host = dev_get_drvdata(ap->dev);
794         struct ahci_host_priv *hpriv = host->private_data;
795         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
796         int ret = -EIO;
797
798         if (imxpriv->type == AHCI_IMX53)
799                 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
800         else
801                 ret = ahci_ops.softreset(link, class, deadline);
802
803         return ret;
804 }
805
806 static struct ata_port_operations ahci_imx_ops = {
807         .inherits       = &ahci_ops,
808         .host_stop      = ahci_imx_host_stop,
809         .error_handler  = ahci_imx_error_handler,
810         .softreset      = ahci_imx_softreset,
811 };
812
813 static const struct ata_port_info ahci_imx_port_info = {
814         .flags          = AHCI_FLAG_COMMON,
815         .pio_mask       = ATA_PIO4,
816         .udma_mask      = ATA_UDMA6,
817         .port_ops       = &ahci_imx_ops,
818 };
819
820 static const struct of_device_id imx_ahci_of_match[] = {
821         { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
822         { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
823         { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
824         { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
825         {},
826 };
827 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
828
829 struct reg_value {
830         u32 of_value;
831         u32 reg_value;
832 };
833
834 struct reg_property {
835         const char *name;
836         const struct reg_value *values;
837         size_t num_values;
838         u32 def_value;
839         u32 set_value;
840 };
841
842 static const struct reg_value gpr13_tx_level[] = {
843         {  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
844         {  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
845         {  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
846         {  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
847         {  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
848         {  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
849         {  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
850         { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
851         { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
852         { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
853         { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
854         { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
855         { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
856         { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
857         { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
858         { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
859         { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
860         { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
861         { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
862         { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
863         { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
864         { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
865         { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
866         { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
867         { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
868         { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
869         { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
870         { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
871         { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
872         { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
873         { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
874         { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
875 };
876
877 static const struct reg_value gpr13_tx_boost[] = {
878         {    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
879         {  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
880         {  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
881         { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
882         { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
883         { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
884         { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
885         { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
886         { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
887         { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
888         { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
889         { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
890         { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
891         { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
892         { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
893         { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
894 };
895
896 static const struct reg_value gpr13_tx_atten[] = {
897         {  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
898         {  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
899         { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
900         { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
901         { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
902         { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
903 };
904
905 static const struct reg_value gpr13_rx_eq[] = {
906         {  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
907         { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
908         { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
909         { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
910         { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
911         { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
912         { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
913         { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
914 };
915
916 static const struct reg_property gpr13_props[] = {
917         {
918                 .name = "fsl,transmit-level-mV",
919                 .values = gpr13_tx_level,
920                 .num_values = ARRAY_SIZE(gpr13_tx_level),
921                 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
922         }, {
923                 .name = "fsl,transmit-boost-mdB",
924                 .values = gpr13_tx_boost,
925                 .num_values = ARRAY_SIZE(gpr13_tx_boost),
926                 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
927         }, {
928                 .name = "fsl,transmit-atten-16ths",
929                 .values = gpr13_tx_atten,
930                 .num_values = ARRAY_SIZE(gpr13_tx_atten),
931                 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
932         }, {
933                 .name = "fsl,receive-eq-mdB",
934                 .values = gpr13_rx_eq,
935                 .num_values = ARRAY_SIZE(gpr13_rx_eq),
936                 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
937         }, {
938                 .name = "fsl,no-spread-spectrum",
939                 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
940                 .set_value = 0,
941         },
942 };
943
944 static u32 imx_ahci_parse_props(struct device *dev,
945                                 const struct reg_property *prop, size_t num)
946 {
947         struct device_node *np = dev->of_node;
948         u32 reg_value = 0;
949         int i, j;
950
951         for (i = 0; i < num; i++, prop++) {
952                 u32 of_val;
953
954                 if (prop->num_values == 0) {
955                         if (of_property_read_bool(np, prop->name))
956                                 reg_value |= prop->set_value;
957                         else
958                                 reg_value |= prop->def_value;
959                         continue;
960                 }
961
962                 if (of_property_read_u32(np, prop->name, &of_val)) {
963                         dev_info(dev, "%s not specified, using %08x\n",
964                                 prop->name, prop->def_value);
965                         reg_value |= prop->def_value;
966                         continue;
967                 }
968
969                 for (j = 0; j < prop->num_values; j++) {
970                         if (prop->values[j].of_value == of_val) {
971                                 dev_info(dev, "%s value %u, using %08x\n",
972                                         prop->name, of_val, prop->values[j].reg_value);
973                                 reg_value |= prop->values[j].reg_value;
974                                 break;
975                         }
976                 }
977
978                 if (j == prop->num_values) {
979                         dev_err(dev, "DT property %s is not a valid value\n",
980                                 prop->name);
981                         reg_value |= prop->def_value;
982                 }
983         }
984
985         return reg_value;
986 }
987
988 static struct scsi_host_template ahci_platform_sht = {
989         AHCI_SHT(DRV_NAME),
990 };
991
992 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
993 {
994         int ret;
995         struct resource *phy_res;
996         struct platform_device *pdev = imxpriv->ahci_pdev;
997         struct device_node *np = dev->of_node;
998
999         if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
1000                 imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
1001         phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1002         if (phy_res) {
1003                 imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
1004                                         resource_size(phy_res));
1005                 if (!imxpriv->phy_base) {
1006                         dev_err(dev, "error with ioremap\n");
1007                         return -ENOMEM;
1008                 }
1009         } else {
1010                 dev_err(dev, "missing *phy* reg region.\n");
1011                 return -ENOMEM;
1012         }
1013         imxpriv->gpr =
1014                  syscon_regmap_lookup_by_phandle(np, "hsio");
1015         if (IS_ERR(imxpriv->gpr)) {
1016                 dev_err(dev, "unable to find gpr registers\n");
1017                 return PTR_ERR(imxpriv->gpr);
1018         }
1019
1020         imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
1021         if (IS_ERR(imxpriv->epcs_tx_clk)) {
1022                 dev_err(dev, "can't get epcs_tx_clk clock.\n");
1023                 return PTR_ERR(imxpriv->epcs_tx_clk);
1024         }
1025         imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
1026         if (IS_ERR(imxpriv->epcs_rx_clk)) {
1027                 dev_err(dev, "can't get epcs_rx_clk clock.\n");
1028                 return PTR_ERR(imxpriv->epcs_rx_clk);
1029         }
1030         imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
1031         if (IS_ERR(imxpriv->phy_pclk0)) {
1032                 dev_err(dev, "can't get phy_pclk0 clock.\n");
1033                 return PTR_ERR(imxpriv->phy_pclk0);
1034         }
1035         imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
1036         if (IS_ERR(imxpriv->phy_pclk1)) {
1037                 dev_err(dev, "can't get phy_pclk1 clock.\n");
1038                 return PTR_ERR(imxpriv->phy_pclk1);
1039         }
1040         imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
1041         if (IS_ERR(imxpriv->phy_apbclk)) {
1042                 dev_err(dev, "can't get phy_apbclk clock.\n");
1043                 return PTR_ERR(imxpriv->phy_apbclk);
1044         }
1045
1046         /* Fetch GPIO, then enable the external OSC */
1047         imxpriv->clkreq_gpio = of_get_named_gpio(np, "clkreq-gpio", 0);
1048         if (gpio_is_valid(imxpriv->clkreq_gpio)) {
1049                 ret = devm_gpio_request_one(dev, imxpriv->clkreq_gpio,
1050                                             GPIOF_OUT_INIT_LOW,
1051                                             "SATA CLKREQ");
1052                 if (ret == -EBUSY) {
1053                         dev_info(dev, "clkreq had been initialized.\n");
1054                 } else if (ret) {
1055                         dev_err(dev, "%d unable to get clkreq.\n", ret);
1056                         return ret;
1057                 }
1058         } else if (imxpriv->clkreq_gpio == -EPROBE_DEFER) {
1059                 return imxpriv->clkreq_gpio;
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int imx_ahci_probe(struct platform_device *pdev)
1066 {
1067         struct device *dev = &pdev->dev;
1068         const struct of_device_id *of_id;
1069         struct ahci_host_priv *hpriv;
1070         struct imx_ahci_priv *imxpriv;
1071         unsigned int reg_val;
1072         int ret;
1073
1074         of_id = of_match_device(imx_ahci_of_match, dev);
1075         if (!of_id)
1076                 return -EINVAL;
1077
1078         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
1079         if (!imxpriv)
1080                 return -ENOMEM;
1081
1082         imxpriv->ahci_pdev = pdev;
1083         imxpriv->no_device = false;
1084         imxpriv->first_time = true;
1085         imxpriv->type = (enum ahci_imx_type)of_id->data;
1086
1087         imxpriv->sata_clk = devm_clk_get(dev, "sata");
1088         if (IS_ERR(imxpriv->sata_clk)) {
1089                 dev_err(dev, "can't get sata clock.\n");
1090                 return PTR_ERR(imxpriv->sata_clk);
1091         }
1092
1093         imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
1094         if (IS_ERR(imxpriv->sata_ref_clk)) {
1095                 dev_err(dev, "can't get sata_ref clock.\n");
1096                 return PTR_ERR(imxpriv->sata_ref_clk);
1097         }
1098
1099         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
1100         if (IS_ERR(imxpriv->ahb_clk)) {
1101                 dev_err(dev, "can't get ahb clock.\n");
1102                 return PTR_ERR(imxpriv->ahb_clk);
1103         }
1104
1105         if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
1106                 u32 reg_value;
1107
1108                 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
1109                                                         "fsl,imx6q-iomuxc-gpr");
1110                 if (IS_ERR(imxpriv->gpr)) {
1111                         dev_err(dev,
1112                                 "failed to find fsl,imx6q-iomux-gpr regmap\n");
1113                         return PTR_ERR(imxpriv->gpr);
1114                 }
1115
1116                 reg_value = imx_ahci_parse_props(dev, gpr13_props,
1117                                                  ARRAY_SIZE(gpr13_props));
1118
1119                 imxpriv->phy_params =
1120                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
1121                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
1122                                    IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
1123                                    reg_value;
1124         } else if (imxpriv->type == AHCI_IMX8QM) {
1125                 ret =  imx8_sata_probe(dev, imxpriv);
1126                 if (ret)
1127                         return ret;
1128         }
1129
1130         hpriv = ahci_platform_get_resources(pdev);
1131         if (IS_ERR(hpriv))
1132                 return PTR_ERR(hpriv);
1133
1134         hpriv->plat_data = imxpriv;
1135
1136         ret = clk_prepare_enable(imxpriv->sata_clk);
1137         if (ret)
1138                 return ret;
1139
1140         if (imxpriv->type == AHCI_IMX53 &&
1141             IS_ENABLED(CONFIG_HWMON)) {
1142                 /* Add the temperature monitor */
1143                 struct device *hwmon_dev;
1144
1145                 hwmon_dev =
1146                         devm_hwmon_device_register_with_groups(dev,
1147                                                         "sata_ahci",
1148                                                         hpriv,
1149                                                         fsl_sata_ahci_groups);
1150                 if (IS_ERR(hwmon_dev)) {
1151                         ret = PTR_ERR(hwmon_dev);
1152                         goto disable_clk;
1153                 }
1154                 devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev,
1155                                              &fsl_sata_ahci_of_thermal_ops);
1156                 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
1157         }
1158
1159         ret = imx_sata_enable(hpriv);
1160         if (ret)
1161                 goto disable_clk;
1162
1163         /*
1164          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
1165          * and IP vendor specific register IMX_TIMER1MS.
1166          * Configure CAP_SSS (support stagered spin up).
1167          * Implement the port0.
1168          * Get the ahb clock rate, and configure the TIMER1MS register.
1169          */
1170         reg_val = readl(hpriv->mmio + HOST_CAP);
1171         if (!(reg_val & HOST_CAP_SSS)) {
1172                 reg_val |= HOST_CAP_SSS;
1173                 writel(reg_val, hpriv->mmio + HOST_CAP);
1174         }
1175         reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
1176         if (!(reg_val & 0x1)) {
1177                 reg_val |= 0x1;
1178                 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
1179         }
1180
1181         reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
1182         writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
1183
1184         ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
1185                                       &ahci_platform_sht);
1186         if (ret)
1187                 goto disable_sata;
1188
1189         return 0;
1190
1191 disable_sata:
1192         imx_sata_disable(hpriv);
1193 disable_clk:
1194         clk_disable_unprepare(imxpriv->sata_clk);
1195         return ret;
1196 }
1197
1198 static void ahci_imx_host_stop(struct ata_host *host)
1199 {
1200         struct ahci_host_priv *hpriv = host->private_data;
1201         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
1202
1203         imx_sata_disable(hpriv);
1204         clk_disable_unprepare(imxpriv->sata_clk);
1205 }
1206
1207 #ifdef CONFIG_PM_SLEEP
1208 static int imx_ahci_suspend(struct device *dev)
1209 {
1210         struct ata_host *host = dev_get_drvdata(dev);
1211         struct ahci_host_priv *hpriv = host->private_data;
1212         int ret;
1213
1214         ret = ahci_platform_suspend_host(dev);
1215         if (ret)
1216                 return ret;
1217
1218         imx_sata_disable(hpriv);
1219
1220         return 0;
1221 }
1222
1223 static int imx_ahci_resume(struct device *dev)
1224 {
1225         struct ata_host *host = dev_get_drvdata(dev);
1226         struct ahci_host_priv *hpriv = host->private_data;
1227         int ret;
1228
1229         ret = imx_sata_enable(hpriv);
1230         if (ret)
1231                 return ret;
1232
1233         return ahci_platform_resume_host(dev);
1234 }
1235 #endif
1236
1237 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
1238
1239 static struct platform_driver imx_ahci_driver = {
1240         .probe = imx_ahci_probe,
1241         .remove = ata_platform_remove_one,
1242         .driver = {
1243                 .name = DRV_NAME,
1244                 .of_match_table = imx_ahci_of_match,
1245                 .pm = &ahci_imx_pm_ops,
1246         },
1247 };
1248 module_platform_driver(imx_ahci_driver);
1249
1250 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
1251 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
1252 MODULE_LICENSE("GPL");
1253 MODULE_ALIAS("ahci:imx");